CN110391196A - 半导体装置 - Google Patents
半导体装置 Download PDFInfo
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- CN110391196A CN110391196A CN201910221467.1A CN201910221467A CN110391196A CN 110391196 A CN110391196 A CN 110391196A CN 201910221467 A CN201910221467 A CN 201910221467A CN 110391196 A CN110391196 A CN 110391196A
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Abstract
一种半导体装置,在印刷电路基板安装半导体芯片。半导体芯片在基板的与印刷电路基板对置的第一面形成有源元件。在与有源元件不同的位置设置由热传导率比基板高的材料构成的热传导膜。在第一面上配置覆盖有源元件以及热传导膜的绝缘膜。在绝缘膜上设置与热传导膜电连接的凸块。设置从与第一面相反侧的第二面到达热传导膜的贯通导通孔。从在俯视时与有源元件重叠的第二面的区域到贯通导通孔的内面连续地配置由热传导率比基板高的材料构成的热传导部件。半导体芯片的凸块与印刷电路基板的连接盘连接,半导体芯片被密封树脂密封。
Description
技术领域
本发明涉及半导体装置。
背景技术
有在设置于半导体芯片的功率放大器的动作时晶体管自发热,而半导体芯片的性能随着晶体管的动作温度的上升而劣化的情况。为了抑制半导体芯片的劣化,期望从作为发热源的晶体管向半导体芯片的外部高效地散热。
在专利文献1有对从安装于模块基板的半导体芯片开始的导热路径的记载。在专利文献1所记载的发明中,形成从半导体芯片的凸块经由形成在模块基板的上面的端子以及从模块基板的上面到达下面的散热贯通孔到达形成在模块基板的下表面的接地用的电极的导热路径。
在接地用的电极连接有晶体管的发射极或者源极。因此,发射极或者源极包含于导热路径的一部分。与凸块连接并成为导热路径的发射极或者源极通常为小面积,导热路径中与发射极或者源极连接的位置成为窄路。因此,难以充分降低导热路径的热阻。
在专利文献2公开了使散热特性提高的半导体装置。在专利文献2所公开的半导体装置中,设置从外部连接焊盘到达形成了有源元件的半导体基板的上面的散热结构。在形成在半导体基板的上面的晶体管产生的热量沿着半导体基板的上面向横向传递到配置了散热结构的位置,其后,经由散热结构进行散热。
专利文献1:日本特开2011-198866号公报
专利文献2:日本特开2014-99470号公报
在晶体管等发热源产生的热量除了沿着半导体基板的上面向横向传递之外,还在半导体基板向厚度方向传递。在以往的半导体装置中,难以将在半导体基板的表面的发热源产生并扩散到半导体基板的内部的热量高效地散热到外部。
发明内容
本发明的目的在于提供能够将在基板的内部扩散的热量高效地散热到外部的半导体装置。
根据本发明的一观点提供一种半导体装置,具有:
印刷电路基板,其在安装面设置有连接盘;以及
半导体芯片,其安装于上述印刷电路基板,
上述半导体芯片具有:
有源元件,其形成在基板的与上述印刷电路基板对置的第一面;
热传导膜,其设置在上述基板的上述第一面的与上述有源元件不同的位置且由热传导率比上述基板高的材料构成;
绝缘膜,其配置在上述基板的上述第一面上并覆盖上述有源元件以及上述热传导膜;
凸块,其配置在上述绝缘膜上并与上述热传导膜电连接;
贯通导通孔,其从上述基板的与上述第一面相反侧的第二面到达上述热传导膜;以及
热传导部件,其从在俯视时与上述有源元件重叠的上述第二面的区域连续地配置至上述贯通导通孔的内面,且由热传导率比上述基板高的材料构成,
上述凸块与上述连接盘连接,上述半导体芯片被密封树脂密封。
根据本发明的其它的观点,提供一种半导体装置,具有:
有源元件,其形成在基板的第一面;
热传导膜,其设置在上述基板的上述第一面的与上述有源元件不同的位置且由热传导率比上述基板高的材料构成;
绝缘膜,其配置在上述基板的上述第一面上并覆盖上述有源元件以及上述热传导膜;
凸块,其配置在上述绝缘膜上并与上述热传导膜电连接;
凹部,其设置在上述基板的与上述第一面相反侧的第二面,且在俯视时与上述有源元件以及上述热传导膜至少部分重叠;以及
热传导部件,其设置在上述凹部的内面且由热传导率比上述基板高的材料构成,
配置在上述凹部的底面的上述热传导部件与上述热传导膜隔着上述基板的一部分对置。
在有源元件产生并向基板侧扩散的热量通过热传导部件、热传导膜以及凸块散热到外部。因此,能够将向基板的内部扩散的热量高效地散热到外部。
附图说明
图1A是第一实施例的半导体装置的框图,图1B是表示第一实施例的半导体装置的各电路的布局的俯视图,图1C是第一实施例的半导体装置的示意剖视图。
图2A是在第一实施例的半导体装置所包含的半导体芯片上形成的输出级放大电路的俯视图,图2B是图2A的点划线2B-2B上的剖视图。
图3是第一实施例的半导体装置的凸块的附近的剖视图。
图4是第二实施例的半导体装置所包含的半导体芯片的剖视图。
图5A是在第三实施例的半导体装置所包含的半导体芯片上形成的输出级放大电路的俯视图,图5B是图5A的点划线5B-5B上的剖视图。
图6是第四实施例的半导体装置所包含的半导体芯片的剖视图。
图7A是第五实施例的半导体装置所包含的半导体芯片的剖视图,图7B是表示第五实施例的半导体装置的各电路的布局的俯视图。
图8是第六实施例的半导体装置所包含的半导体芯片的剖视图。
图9是第七实施例的半导体装置所包含的半导体芯片的剖视图。
附图标记说明
10…阻抗匹配电路,11…驱动级放大电路,12…阻抗匹配电路,13…输出级放大电路,14…控制电路,15…输入端子,16…输出端子,17、18…电感器,20…印刷电路基板,21…连接盘,23…外部连接用的电极,24…贯通孔导体,25…内层的布线,28…密封树脂,30…半导体芯片,31…凸块,32…Cu柱,33…焊料凸块,40…半导体基板,41…贯通导通孔,42…晶体管(有源元件),43…热传导膜,45、46、47…绝缘膜,48…发热源,49…热传导性膏体,51…热传导部件,60…凹部,61、62…热传导性膏体,B0…基极电极,B1…第一层基极布线,C0…集电极电极,C1…第一层集电极布线,C2…第二层集电极布线,E0…发射极电极,E1…第一层发射极布线,E2…第二层集电极布线,T0、T1、T2、T3…热路径。
具体实施方式
[第一实施例]
参照图1A~图3的附图,对第一实施例的半导体装置进行说明。
图1A是第一实施例的半导体装置的框图。输入信号从输入端子15经由阻抗匹配电路10输入到驱动级放大电路11。被驱动级放大电路11放大的信号经由阻抗匹配电路12输入到输出级放大电路13。被输出级放大电路13放大的信号从输出端子16输出。经由电感器17对驱动级放大电路11供给直流电力。经由电感器18对输出级放大电路13供给直流电力。
图1B是表示第一实施例的半导体装置所包含的半导体芯片30的各电路的布局的俯视图。在半导体基板40的表面形成阻抗匹配电路10、12、驱动级放大电路11、输出级放大电路13、以及控制电路14。在形成输出级放大电路13的区域设置在厚度方向贯通半导体基板40的贯通导通孔41。
如后述那样,贯通导通孔41具有使在构成输出级放大电路13的晶体管产生的热量高效地传导到半导体芯片30的外部的功能。驱动级放大电路11的晶体管的发热量与输出级放大电路13的晶体管的发热量相比较少。因此,优选与输出级放大电路13对应地设置贯通导通孔41。既可以对驱动级放大电路11设置贯通导通孔,也可以不设置。
图1C是第一实施例的半导体装置的示意剖视图。在印刷电路基板20的安装面(在图1B中为上面)安装半导体芯片30。半导体芯片30包含形成在半导体基板40的与印刷电路基板20对置的面(以下,称为第一面。)的多个凸块31。印刷电路基板20包含形成在安装面的多个连接盘21、以及形成在下面(与安装面相反侧的面)的外部连接用的多个电极23。
多个连接盘21中的至少一个为接地用的连接盘21,多个电极23中的至少一个为接地用的电极23。接地用的连接盘21与接地用的电极23经由多个贯通孔导体24以及内层的布线25电连接。
半导体芯片30的凸块31与印刷电路基板20的连接盘21连接。半导体芯片30的多个凸块31中至少一个为接地用的凸块31,接地用的凸块31与印刷电路基板20的接地用的连接盘21连接。半导体芯片30被密封树脂28密封。
图2A是在第一实施例的半导体装置所包含的半导体芯片30上形成的输出级放大电路13(图1A)的俯视图。输出级放大电路13例如包含相互并联连接,且排列成一列的四个晶体管42(有源元件)。以下,将晶体管42排列的方向仅称为“排列方向”。晶体管42例如是异质结双极晶体管。
晶体管42的各个包含发射极电极E0,基极电极B0,以及集电极电极C0。在图2A中,对发射极电极E0、基极电极B0、以及集电极电极C0的区域附加影线。若着眼于一个晶体管42,则关于排列方向在发射极电极E0的两侧分别配置基极电极B0的一部分,并在其两侧分别配置集电极电极C0。配置在发射极电极E0的两侧的基极电极B0的一部分在发射极电极E0的外侧相互连续。例如,基极电极B0在俯视时从三个方向以U形包围发射极电极E0。相互相邻的晶体管42共享一个集电极电极C0。
多个第一层发射极布线E1分别配置为与多个发射极电极E0重叠。多个第一层基极布线B1分别与多个基极电极B0的一部分重叠,并从重叠的位置引出到外侧。包含线状部和多个梳齿部的第一层集电极布线C1的多个梳齿部分别与多个集电极电极C0重叠。集电极布线C1的线状部与集电极电极C0相邻,且关于排列方向从配置一端的晶体管42的位置到达配置另一端的晶体管42的位置,并与多个梳齿部的各个连接。
在与晶体管42不同的位置配置热传导膜43。例如,在从晶体管42观察与第一层集电极布线C1的线状部相反侧配置热传导膜43。热传导膜43具有在排列方向较长的形状,关于排列方向从配置一端的晶体管42的位置到达配置另一端的晶体管42的位置。热传导膜43由与第一层基极布线B1、发射极布线E1、以及集电极布线C1相同的金属材料,例如Au形成,并利用同一工序成膜。在俯视使在热传导膜43的内侧配置贯通导通孔41。
第二层集电极布线C2配置为与第一层集电极布线C1的线状部重叠。第二层发射极布线E2配置为与第一层发射极布线E1以及热传导膜43重叠。
在最上层配置凸块31。凸块31在俯视时与第二层发射极布线E2重叠,并且与多个发射极电极E0以及热传导膜43部分重叠,或者与多个发射极电极E0以及热传导膜43的整体重叠。
图2B是图2A的点划线2B-2B上的剖视图。在半导体基板40的上面(第一面)形成晶体管42。半导体基板40例如包含由半绝缘性的GaAs构成的支承基板、和在其上外延生长的由GaAs构成的外延生长层。对外延生长层中配置了晶体管42的区域给予导电性,其它的区域为绝缘性。
晶体管42包含由集电极层、基极层以及发射极层构成的半导体台面、基极电极B0以及发射极电极E0。集电极电极C0(图2A)在图2B的剖面未显现。在半导体基板40的上面上配置覆盖晶体管42的SiN等绝缘膜45。在绝缘膜45上配置第一层发射极布线E1、基极布线B1、集电极布线C1、以及热传导膜43。第一层发射极布线E1以及基极布线B1分别经由设置在绝缘膜45的开口内与发射极电极E0以及基极电极B0连接。在图2B所示的剖面中,在第一层集电极布线C1的正下的绝缘膜45未设置开口。热传导膜43经由设置在绝缘膜45的开口内与半导体基板40的上面相接。
第一层发射极布线E1、基极布线B1、集电极布线C1以及热传导膜43例如使用Au等金属。热传导膜43所使用的金属的热传导率比半导体基板40的热传导率高。
在绝缘膜45上配置绝缘膜46,以覆盖第一层发射极布线E1、基极布线B1、集电极布线C1、以及热传导膜43。绝缘膜46例如具有SiN膜与树脂膜的双层结构,绝缘膜46的上面被平坦化。
在绝缘膜46上配置第二层发射极布线E2以及第二层集电极布线C2。第二层发射极布线E2经由设置在绝缘膜46的开口内与第一层发射极布线E1连接,并且也经由其它的开口内与热传导膜43连接。第二层集电极布线C2经由设置在绝缘膜46的开口内与第一层集电极布线C1连接。
在绝缘膜46上配置绝缘膜47。在绝缘膜47设置使第二层发射极布线E2的一部分露出的开口,在开口内的第二层发射极布线E2上以及开口的周围的绝缘膜47上配置凸块31。凸块31例如使用包含Cu柱32和设置在其上面的焊料凸块33的Cu柱凸块。经由发射极布线E2、E1与发射极电极E0连接的凸块31是接地用的凸块。
在半导体基板40形成从其下面(第二面)到达热传导膜43的贯通导通孔41。在俯视时,从半导体基板40的下面的与晶体管42重叠的区域到贯通导通孔41的内面连续地配置热传导部件51。作为热传导部件51,例如使用Au等金属膜。作为一个例子,热传导部件51覆盖半导体基板40的下面的整个区域,并覆盖贯通导通孔41的侧面以及底面的整个区域。由于在贯通导通孔41的底面露出热传导膜43,所以热传导部件51与热传导膜43接触。
接下来,参照图3对第一实施例的优异的效果进行说明。
图3是第一实施例的半导体装置的凸块31的附近的剖视图。半导体芯片30的接地用的凸块31与印刷电路基板20的接地用的连接盘21电连接,并且机械固定。连接盘21经由设置在印刷电路基板20的内层的多个布线25以及多个贯通孔导体24,与形成在与安装面相反侧的面的外部连接用的电极23连接。
在晶体管42的动作时,动作电流流过在俯视时与发射极电极E0重叠的半导体区域,从而产生热量。在俯视时,晶体管42的半导体区域中与发射极电极E0重叠的部分成为发热源48。关于半导体基板40的厚度方向,晶体管42的由集电极层、基极层、以及发射极层构成的区域成为发热源48。在发热源48产生,并流向与半导体基板40相反侧的热量经由由发射极电极E0、发射极布线E1、E2以及凸块31构成的热路径T0传导至印刷电路基板20的连接盘21。
并且,在发热源48产生的热量的一部分扩散到半导体基板40的内部。扩散到半导体基板40的内部的热量经由由半导体基板40、热传导部件51、热传导膜43、第二层发射极布线E2、以及凸块31构成的热路径T1传导至印刷电路基板20的连接盘21。
传递到印刷电路基板20的连接盘21的热量经由贯通孔导体24以及布线25,传递到外部连接用的电极23。电极23例如与母板等较大的接地导体连接。因此,传递至电极23的热量朝向具有与半导体芯片30相比足够大的热容量的外部的接地导体排出。
在第一实施例中,在发热源48产生并在半导体基板40向横向(与厚度方向正交的方向)扩散的热量传递至覆盖贯通导通孔41的侧面的热传导部件51,其后,传递至热传导膜43。在发热源48产生,并在半导体基板40向厚度方向扩散的热量传递至覆盖半导体基板40的与安装面相反侧的面的热传导部件51,其后,经由热传导部件51传递至热传导膜43。由于热传导部件51使用与半导体基板40相比热传导率较高的材料,所以与不配置热传导部件51的构成相比能够使热路径T1的热阻降低。
在第一实施例中,不仅热路径T0,以使在半导体基板40内扩散的热量经由热路径T1散热到外部,所以能够抑制晶体管42的温度上升。由于热传导部件51与热传导膜43不经由绝缘材料或者半导体材料而直接接触,所以能够抑制热路径T1的热阻的上升。因此,能够经由热路径T1高效地进行散热。
为了使热路径T1的热阻降低,优选在俯视时,与设置于绝缘膜46的开口以及凸块31至少部分重叠地配置贯通导通孔41以及热传导膜43。并且,优选在俯视时,与接地用的电极23至少部分重叠地配置印刷电路基板20的接地用的连接盘21。这里,“至少部分重叠”是指在俯视时,使一方的部件的一部分与另一方的部件的一部分重叠的状态、使一方的部件的整个区域与另一方的部件的一部分重和的状态、以及使一方的部件的整个区域与另一方的部件的整个区域重叠的状态的任意一种。优选使用与其它的凸块相比具有较大的面积的接地用的凸块作为构成热路径T1的一部分的凸块31。
接下来,对第一实施例的变形例进行说明。
虽然在第一实施例中,例如使用由GaAs构成的基板作为半导体基板40,但也可以使用由其它的半导体构成的基板,也可以使用能够使其在有源元件的半导体区域外延生长的绝缘性基板。另外,虽然在第一实施例中,使用异质结双极晶体管作为晶体管42,但也可以使用其它的有源元件,例如MIS晶体管、MES晶体管、高电子迁移率晶体管(HEMT)等。另外,虽然在第一实施例中,使用Cu柱凸块作为凸块31,但也可以使用其它的结构的凸块。
[第二实施例]
接下来,参照图4对第二实施例的半导体装置进行说明。以下,对与第一实施例的半导体装置(图1A~图2B)相同的构成省略说明。
图4是第二实施例的半导体装置所包含的半导体芯片的剖视图。在第一实施例中,贯通导通孔41(图2B)的侧面和底面被热传导部件51覆盖,贯通导通孔41内的剩余的部分为空洞,或者被密封树脂(图1C)填充。在第二实施例中,在贯通导通孔41内的剩余的部分埋入热传导性膏体49。这里,“埋入”不是指贯通导通孔41内的空间完全被热传导性膏体49填充。例如,即使在热传导性膏体49的表面稍微凹陷的情况下,也能够称为“埋入”。
热传导性膏体49的热传导率比密封树脂28的热传导率高。作为热传导性膏体49,能够使用使金属或者陶瓷的粉末分散到膏体状物质的膏体。膏体状物质例如能够使用环氧树脂等树脂。金属、陶瓷的粉末例如能够使用银、SiC、AlN等。“膏体”一般而言是指具有流动性和较高的粘性的物质,但在本说明书中,膏体通过加热等固化后的物体也称为膏体。
接下来,对第二实施例的优异的效果进行说明。在第二实施例中,贯通导通孔41内的热传导性膏体49作为热路径T1(图3)的一部分发挥作用。因此,热路径T1的剖面积增大,热阻降低。其结果,能够提高经由热路径T1的热传导的效率。
热传导性膏体49即使在固化后,也具有比半导体基板40低的杨氏模量。热传导性膏体49根据半导体基板40的热变形而灵活地变形,所以与在贯通导通孔41内填充金属部件的构成相比,能够得到即使半导体基板40热变形半导体芯片30也不容易受到损伤这样的效果。
[第三实施例]
接下来,参照图5A以及图5B,对第三实施例的半导体装置进行说明。以下,对与第一实施例的半导体装置(图1A~图2B)相同的构成省略说明。
图5A是在第三实施例的半导体装置所包含的半导体芯片30上形成的输出级放大电路13(图1A)俯视图。图5B是图5A的点划线5B-5B上的剖视图。在第三实施例中,在半导体基板40的底面形成凹部60。凹部60不到达半导体基板40的上面。在俯视时,凹部60与晶体管42至少部分重叠,并在凹部60的区域内配置贯通导通孔41。在图5A中,示出在俯视时晶体管42配置在凹部60的内部的例子。贯通导通孔41从凹部60的底面到达热传导膜43。
半导体基板40的下面、凹部60的侧面和底面以及贯通导通孔41的侧面和底面被热传导部件51覆盖。
接下来,对第三实施例的优异的效果进行说明。在第三实施例中,在半导体基板40形成凹部60,所以关于半导体基板40的厚度方向从发热源48到热传导部件51的距离与第一实施例的情况相比变短。由于热路径T1缩短而热阻降低,所以能够提高通过了热路径T1的热传导的效率。虽然若使半导体基板40变薄,则半导体芯片30的机械强度降低,但在第三实施例中,在作为热路径T1发挥作用的区域以外,未使半导体基板40变薄。因此,能够维持半导体芯片30的足够的机械强度。
热传导部件51的热导率与半导体基板40的热导率相比能够视为足够高。此时,为了得到使热路径T1的热阻降低所带来的充分的效果,优选使从发热源48到凹部60的底面的距离L2比从发热源48到贯通导通孔41的横向的距离L1短。从发热源48到贯通导通孔41的距离L1的起点定义为发射极电极E0的端部即可。从发热源48到凹部60的底面的距离L2的起点定义为构成晶体管42的集电极层的下面即可。
[第四实施例]
接下来,参照图6,对第四实施例的半导体装置进行说明。以下,对与第三实施例的半导体装置(图5A、图5B)相同的构成省略说明。
图6是第四实施例的半导体装置所包含的半导体芯片30的剖视图。在第四实施例中,凹部60以及贯通导通孔41的内部埋入热传导性膏体61。作为热传导性膏体61,例如使用与第二实施例的半导体装置所使用的热传导性膏体49(图4)相同的膏体即可。
接下来,对第四实施例的优异的效果进行说明。在第四实施例中,凹部60以及贯通导通孔41的内部埋入热传导性膏体61,所以与第二实施例相同,能够提高热传导的效率。其结果,能够抑制晶体管42的温度上升。
另外,热传导性膏体61即使在固化后,也具有比半导体基板40低的杨氏模量。热传导性膏体61根据半导体基板40的热变形而灵活地变形,所以与在贯通导通孔41和凹部60的内部填充金属部件的构成相比,能够得到即使半导体基板40热变形半导体芯片30也不容易受到损伤这样的效果。
并且,通过埋入到凹部60的热传导性膏体61,能够补偿由于设置凹部60而半导体基板40变薄的部分的机械强度的降低。由此,能够抑制在芯片切割等加工工序施加机械应力所引起的半导体芯片的破损。
[第五实施例]
接下来,参照图7A以及图7B,对第五实施例的半导体装置进行说明。以下,对与第一实施例的半导体装置(图1A~图2B)相同的构成省略说明。
图7A是第五实施例的半导体装置所包含的半导体芯片30的剖视图。在第一实施例中在半导体基板40设置从下面到达上面的热传导膜43(图2B)的贯通导通孔41。在第五实施例中,不设置贯通导通孔,而在半导体基板40的下面设置不到达上面的凹部60。凹部60的侧面以及底面被热传导部件51覆盖。在俯视时,凹部60与晶体管42的发射极电极E0以及热传导膜43至少部分重叠。配置在凹部60的底面的热传导部件51与热传导膜43隔着半导体基板40的一部分对置而并不接触。在凹部60埋入有密封树脂28(图1C)。
图7B是表示第五实施例的半导体装置的各电路的布局的俯视图。在第一实施例中,在配置了输出级放大电路13的区域配置贯通导通孔41(图1B)。在第五实施例中,将凹部60配置为在内部包含输出级放大电路13。
接下来,对第五实施例的优异的效果进行说明。在第五实施例中,与第一实施例的热路径T0(图3)相同,形成从发热源48经由发射极电极E0、以及发射极布线E1、E2到达凸块31的热路径T0。除此之外,形成从发热源48在半导体基板40向横向传递,并经由热传导膜43、第二层发射极布线E2到达凸块31的热路径T2。并且,形成在发热源48产生的热量在半导体基板40向厚度方向扩散,在热传导部件51向横向传导,其后,在半导体基板40向厚度方向传导并到达凸块31的热路径T3。
构成热路径T3的一部分的热传导部件51的热传导率比半导体基板40的热传导率高。另外,若设置凹部60,则热路径T3中由热传导率较低的半导体基板40构成的部分较短。因此,热路径T3的热阻降低,能够提高经由热路径T3的热传导的效率。
若使半导体基板40的整体变薄,则不能够确保足够的机械强度。在第五实施例中,在作为热路径T3发挥作用的区域以外,不使半导体基板40变薄。因此,能够维持半导体芯片30的足够的机械强度。
[第六实施例]
接下来,参照图8对第六实施例的半导体装置进行说明。以下,对与第五实施例的半导体装置(图7A、图7B)相同的构成省略说明。
图8是第六实施例的半导体装置所包含的半导体芯片30的剖视图。在第五实施例中,在俯视时凹部60(图7A)与发热源48以及热传导膜43双方至少部分重叠。在第六实施例中,凹部60并不限定于与发热源48以及热传导膜43双方重叠。在图8中,示出在俯视时凹部60与发热源48重叠,而不与热传导膜43重叠的例子。凹部60配置为在俯视时与被发热源48和热传导膜43夹着的区域部分重叠。
在第六实施例中,热传导部件51也构成使在发热源48产生并向半导体基板40扩散的热量传导至凸块31的热路径的一部分。
接下来,对凹部60、发热源48、以及热传导膜43的优选的相对位置关系进行说明。以L3表示从发热源48到配置在凹部60的底面的热传导部件51为止的最短距离。以L4表示从热传导膜43到热传导部件51为止的最短距离。以L5表示在俯视时,从发热源48的几何学的重心位置到热传导膜43为止的最短距离。热传导部件51的热导率与半导体基板40的热导率相比能够视为足够高。此时,为了得到形成凹部60并配置热传导部件51所带来的充分的效果,优选将凹部60的位置以及深度设定为L3+L4在L5以下。
[第七实施例]
接下来,参照图9对第七实施例的半导体装置进行说明。以下,对与第五实施例的半导体装置(图7A、图7B)相同的构成省略说明。
图9是第七实施例的半导体装置所包含的半导体芯片30的剖视图。在第五实施例中,将半导体芯片30安装于印刷电路基板20(图1C)之后,在凹部60的内部埋入密封树脂28(图1C)。在第七实施例中,凹部60的内部埋入热传导性膏体62。热传导性膏体62例如能够使用与第二实施例的半导体装置所使用的热传导性膏体49(图4)相同的膏体。
接下来,对第七实施例的优异的效果进行说明。在第七实施例中,热传导性膏体62具有使热路径T3中在热传导部件51向横向延伸的部分的剖面积扩大的作用。因此,热路径T3的热阻降低,能够提高经由热路径T3的热传导的效率。其结果,能够抑制晶体管42的温度上升。
另外,通过埋入凹部60的热传导性膏体62,能够补偿由于设置凹部60而半导体基板40变薄的部分的机械强度的降低。由此,能够抑制在芯片切割等加工工序施加机械应力所引起的半导体基板40的破损。
上述的各实施例为例示,当然能够进行不同的实施例所示的构成的部分的置换或者组合。并不对每个实施例依次提及多个实施例的相同的构成所带来的相同的作用效果。并且,本发明并不限定于上述的实施例。例如,本领域技术人员明确能够进行各种变更、改进、组合等。
Claims (9)
1.一种半导体装置,其中,具有:
印刷电路基板,其在安装面设置有连接盘;以及
半导体芯片,其安装于上述印刷电路基板,
上述半导体芯片具有:
有源元件,其形成在基板的与上述印刷电路基板对置的第一面;
热传导膜,其设置在上述基板的上述第一面的与上述有源元件不同的位置,且由热传导率比上述基板高的材料构成;
绝缘膜,其配置在上述基板的上述第一面上并覆盖上述有源元件以及上述热传导膜;
凸块,其配置在上述绝缘膜上并与上述热传导膜电连接;
贯通导通孔,其从上述基板的与上述第一面相反侧的第二面到达上述热传导膜;以及
热传导部件,其从在俯视时与上述有源元件重叠的上述第二面的区域连续地配置至上述贯通导通孔的内面,且由热传导率比上述基板高的材料构成,
上述凸块与上述连接盘连接,上述半导体芯片被密封树脂密封。
2.根据权利要求1所述的半导体装置,其中,
上述凸块和上述热传导膜被配置为在俯视时至少部分重叠。
3.根据权利要求1或者2所述的半导体装置,其中,
上述半导体芯片还具有形成在上述基板的上述第二面的凹部,
上述凹部在俯视时与上述有源元件至少部分重叠,并在上述凹部的区域内配置有上述贯通导通孔,在上述凹部的内面配置有上述热传导部件。
4.根据权利要求1~3中任意一项所述的半导体装置,其中,
上述热传导部件覆盖上述贯通导通孔的内面,
上述半导体装置还具有埋入上述贯通导通孔的内部的热传导性膏体。
5.根据权利要求3所述的半导体装置,其中,
上述热传导部件覆盖上述贯通导通孔以及上述凹部的内面,
上述半导体装置还具有埋入上述贯通导通孔的内部以及上述凹部的内部的热传导性膏体。
6.一种半导体装置,其中,具有:
有源元件,其形成在基板的第一面;
热传导膜,其设置在上述基板的上述第一面的与上述有源元件不同的位置,且由热传导率比上述基板高的材料构成;
绝缘膜,其配置在上述基板的上述第一面上并覆盖上述有源元件以及上述热传导膜;
凸块,其配置在上述绝缘膜上并与上述热传导膜电连接;
凹部,其设置在上述基板的与上述第一面相反侧的第二面,且在俯视时与上述有源元件以及上述热传导膜至少部分重叠;以及
热传导部件,其设置在上述凹部的内面,且由热传导率比上述基板高的材料构成,
配置在上述凹部的底面的上述热传导部件与上述热传导膜隔着上述基板的一部分而对置。
7.根据权利要求6所述的半导体装置,其中,
上述凸块与上述热传导膜被配置为在俯视时至少部分重叠。
8.根据权利要求6或者7所述的半导体装置,其中,
还具有埋入上述凹部的内部的热传导性膏体。
9.根据权利要求6~8中任意一项所述的半导体装置,其中,
从上述有源元件的发热源到上述热传导部件的最短距离与从上述热传导膜到上述热传导部件的最短距离之和在从上述发热源到上述热传导膜的距离以下。
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JP4459883B2 (ja) * | 2005-04-28 | 2010-04-28 | 三菱電機株式会社 | 半導体装置 |
US7538401B2 (en) * | 2005-05-03 | 2009-05-26 | Rosemount Aerospace Inc. | Transducer for use in harsh environments |
JP2009500820A (ja) * | 2005-06-29 | 2009-01-08 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | アセンブリを製造する方法及びアセンブリ |
JP5407667B2 (ja) * | 2008-11-05 | 2014-02-05 | 株式会社村田製作所 | 半導体装置 |
JP2011198866A (ja) | 2010-03-18 | 2011-10-06 | Renesas Electronics Corp | 半導体装置およびその製造方法 |
JP6093556B2 (ja) | 2012-11-13 | 2017-03-08 | 富士通株式会社 | 半導体装置および半導体集積回路装置、電子装置 |
EP2738806A3 (en) * | 2012-11-30 | 2017-01-11 | Enpirion, Inc. | Semiconductor device including a redistribution layer and metallic pillars coupled thereto |
WO2015162815A1 (ja) * | 2014-04-24 | 2015-10-29 | 株式会社村田製作所 | 半導体素子及び高周波増幅器モジュール |
JP2016004877A (ja) * | 2014-06-16 | 2016-01-12 | ルネサスエレクトロニクス株式会社 | 半導体装置および電子装置 |
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US20100123225A1 (en) * | 2008-11-20 | 2010-05-20 | Gruenhagen Michael D | Semiconductor Die Structures for Wafer-Level Chipscale Packaging of Power Devices, Packages and Systems for Using the Same, and Methods of Making the Same |
CN102347243A (zh) * | 2010-07-29 | 2012-02-08 | 三菱电机株式会社 | 半导体装置及其制造方法 |
US20120056337A1 (en) * | 2010-09-03 | 2012-03-08 | Murata Manufacturing Co., Ltd. | Rfic chip mounting structure |
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TW201944557A (zh) | 2019-11-16 |
TWI708338B (zh) | 2020-10-21 |
US20190326191A1 (en) | 2019-10-24 |
US10957617B2 (en) | 2021-03-23 |
JP2019192729A (ja) | 2019-10-31 |
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