JP6697547B2 - 追加的トラックを備えた半導体パワーデバイスおよび半導体パワーデバイスを製造する方法 - Google Patents
追加的トラックを備えた半導体パワーデバイスおよび半導体パワーデバイスを製造する方法 Download PDFInfo
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- JP6697547B2 JP6697547B2 JP2018517303A JP2018517303A JP6697547B2 JP 6697547 B2 JP6697547 B2 JP 6697547B2 JP 2018517303 A JP2018517303 A JP 2018517303A JP 2018517303 A JP2018517303 A JP 2018517303A JP 6697547 B2 JP6697547 B2 JP 6697547B2
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- 239000004065 semiconductor Substances 0.000 title claims description 135
- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 239000000758 substrate Substances 0.000 claims description 103
- 239000003989 dielectric material Substances 0.000 claims description 84
- 239000000463 material Substances 0.000 claims description 46
- 238000000034 method Methods 0.000 claims description 29
- 239000003822 epoxy resin Substances 0.000 claims description 18
- 229920000647 polyepoxide Polymers 0.000 claims description 18
- 229910052709 silver Inorganic materials 0.000 claims description 18
- 239000004332 silver Substances 0.000 claims description 18
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 17
- 229910052802 copper Inorganic materials 0.000 claims description 17
- 239000010949 copper Substances 0.000 claims description 17
- 239000004020 conductor Substances 0.000 claims description 13
- 239000002245 particle Substances 0.000 claims description 13
- 239000000919 ceramic Substances 0.000 claims description 12
- 230000015556 catabolic process Effects 0.000 claims description 11
- 229910000679 solder Inorganic materials 0.000 claims description 10
- 238000005245 sintering Methods 0.000 claims description 9
- 239000007787 solid Substances 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 5
- 229910003460 diamond Inorganic materials 0.000 claims description 4
- 239000010432 diamond Substances 0.000 claims description 4
- 239000002253 acid Substances 0.000 claims 1
- 150000004820 halides Chemical class 0.000 claims 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 17
- 229910052751 metal Inorganic materials 0.000 description 11
- 239000002184 metal Substances 0.000 description 11
- 238000007639 printing Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 239000011230 binding agent Substances 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 239000002270 dispersing agent Substances 0.000 description 3
- 238000007650 screen-printing Methods 0.000 description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- -1 but not limited to Substances 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 230000001419 dependent effect Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- LNEPOXFFQSENCJ-UHFFFAOYSA-N haloperidol Chemical compound C1CC(O)(C=2C=CC(Cl)=CC=2)CCN1CCCC(=O)C1=CC=C(F)C=C1 LNEPOXFFQSENCJ-UHFFFAOYSA-N 0.000 description 2
- 239000002923 metal particle Substances 0.000 description 2
- 150000002894 organic compounds Chemical class 0.000 description 2
- 239000011368 organic material Substances 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 230000021615 conjugation Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
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- H01L23/49838—Geometry or layout
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Description
Claims (17)
- 半導体パワーデバイス(100、300)であって、
− 第1のパターニングされた導電層(112、113、412)を備えた第1の基板(110、400)であって、第1の基板(110、400)が、第1のパターニングされた導電層(112、113、412)がその上に提供されている第1の表面(111)を有する、第1の基板(110、400)と、
− 第2のパターニングされた導電層(122、422)と第1の表面(111)に面した第2の表面(121)とを備えた第2の基板(120、450)であって、第2のパターニングされた導電層(122、422)が第2の表面(121)の上に提供されている、第2の基板(120、450)と、
− 第1のパターニングされた導電層(112、113、412)と第2のパターニングされた導電層(122、422)との間に配置されたスイッチング半導体素子(115)であって、第1のパターニングされた導電層の上に提供されている、スイッチング半導体素子(115)と、
− 導電性トラック(132、432)と誘電材料の層(131、431)との積層(130、430)であって、誘電材料の層(131、431)が、少なくとも部分的に、第1のパターニングされた導電層(112、113、412)または第2のパターニングされた導電層(122、422)の上に提供されており、導電性トラック(132、432)を、積層(130、430)がその上に提供されている前記パターニングされた導電層(112、122、113、412、422)から絶縁する、積層(130、430)と、
− 相互接続構造(140、141、440、440’、441、441’)であって、
− 一方の側におけるスイッチング半導体素子(115)のベースまたはゲートと、他方の側における導電性トラック(132、432)との間に電気的接続を提供する第1の銅製ボール(140、440)と、
− 一方の側における、スイッチング半導体素子(115)のドレイン、ソース、エミッタまたはコレクタのうちの少なくとも1つと、他方の側における第2のパターニングされた導電層(122、422)との間に電気的接続を提供する第2の銅製ボール(141、441)とを備える相互接続構造(140、141、440、440’、441、441’)と、
を備える、半導体パワーデバイス(100、300)。 - 誘電材料の層(131、431)が、導電性トラック(132、432)と、積層がその上に提供されている前記パターニングされた導電層(112、122、113、412、422)との間で、少なくとも20ボルトの絶縁破壊電圧を有する、請求項1に記載の半導体パワーデバイス(100、300)。
- 追加的導電性トラック(333)と誘電材料の追加的層(331)との追加的積層(330)をさらに備えており、誘電材料の追加的層(331)が、第1のパターニングされた導電層(112、113、412)または第2のパターニングされた導電層(122、422)の上に提供されており、追加的導電性トラック(333)を、追加的積層(330)がその上に提供されている前記パターニングされた導電層(112、122、113、412、422)から絶縁する、請求項1または2に記載の半導体パワーデバイス(100、300)。
- 誘電材料が、エポキシ樹脂、酸化物材料、またはソルダレジストを含む、請求項1から3のいずれか一項に記載の半導体パワーデバイス(100、300)。
- 誘電材料の層(131、431)が、エポキシ樹脂の2つの層を備える、請求項4に記載の半導体パワーデバイス(100、300)。
- 導電層トラック(132、432)が、金属、または、導電性であるトラックを取得するためにある量の導電性粒子がその中に提供されているエポキシ樹脂を備えている、請求項1から5のいずれか一項に記載の半導体パワーデバイス(100、300)。
- 導電性トラック(132、432)が固体多孔性銀を含む、請求項1から6のいずれか一項に記載の半導体パワーデバイス(100、300)。
- 第1の基板(110、400)と第2の基板(120、450)との少なくとも一方がセラミック支持層を備える、請求項1から7のいずれか一項に記載の半導体パワーデバイス(100、300)。
- スイッチング半導体素子(115、415、465、465’、465’’)が、ワイドバンドギャップ半導体材料に基づくトランジスタを備える、請求項1から8のいずれか一項に記載の半導体パワーデバイス(100、300)。
- ワイドバンドギャップ半導体材料がSiC、GaNまたはダイヤモンドを含む、請求項9に記載の半導体パワーデバイス(100、300)。
- 導電性トラック(132、432)が、
− 半導体パワーデバイス(100、300)に埋め込まれたセンサ素子と、
− 半導体パワーデバイス(100、300)に埋め込まれた埋込ドライバ素子と、
− 前記パターニングされた導電層(112、122、113、412、422)の電圧が感知されなければならない特定の感知位置(L)における第1のパターニングされた導電層(112、113、412)または第2のパターニングされた導電層(122、422)と、
の少なくとも1つに電気的に結合されている、請求項1から10のいずれか一項に記載の半導体パワーデバイス(100、300)。 - 電力を電気モータに提供するためのモータドライバであって、電気モータに提供された電流をスイッチングするために、請求項1から11のいずれか一項に記載の半導体パワーデバイス(100、300)を備える、モータドライバ。
- 多相電気信号を電気モータに提供するように構成されており、多相電気信号の各位相のために、請求項1から11のいずれか一項に記載の半導体パワーデバイス(100、300)の少なくとも1つを備える、請求項12に記載のモータドライバ。
- 半導体パワーデバイスを製造する方法(500)であって、
− スイッチング半導体素子と第1のパターニングされた導電層とを備えた第1の基板を取得するステップ(502)であって、第1の基板は、第1のパターニングされた導電層がその上に提供されている第1の表面を有している、第1の基板を取得するステップ(502)と、
− 第2のパターニングされた導電層と第2の表面とを備えた第2の基板を取得するステップ(504)であって、第2のパターニングされた導電層は第2の表面の上に提供されており、スイッチング半導体素子が、第1のパターニングされた導電層と第2のパターニングされた導電層との間に配置され、第1のパターニングされた導電層の上に提供されている、第2の基板を取得するステップ(504)と、
− 導電性トラックと誘電材料の層との積層を、少なくとも部分的に、第1のパターニングされた導電層の上にまたは第2のパターニングされた導電層の上に製造するステップ(506)であって、誘電材料の層が、導電性トラックを、積層がその上に製造されパターニングされた導電層から絶縁する、積層を製造するステップ(506)と、
− 導電性材料の相互接続構造を取得するステップ(520)であって、相互接続構造は、第1の銅製ボールと、第2の銅製ボールとを備える、導電性材料の相互接続構造を取得するステップ(520)と、
− 第1のパターニングされた導電性層、スイッチング半導体素子の表面、導電性トラック、または第2のパターニングされた導電層のうちの1つの上に、相互接続構造を提供するステップ(522)と、
− 第1の表面が第2の表面に面し、少なくとも、
− 第1の銅製ボールが、一方の側におけるスイッチング半導体素子のベースまたはゲートと、他方の側における導電性トラックとの間に電気的接続を提供し、
− 第2の銅製ボールが、一方の側における、スイッチング半導体素子のドレイン、ソース、エミッタまたはコレクタのうちの少なくとも1つと、他方の側における第2のパターニングされた導電層との間に電気的接続を提供するように、
第1の基板と対向するように第2の基板を組み立てるステップ(524)と、
を備える、方法。 - 導電性トラックと誘電材料の層との積層を製造するステップ(506)が、
− 第1のパターニングされた導電層または第2のパターニングされた導電層の上に、誘電材料のパターニングされた層を提供するステップ(506)と、
− 誘電材料のパターニングされた層の上に導電性トラックを提供する(514)ステップと、
を備える、請求項14に記載の半導体パワーデバイスを製造する方法(500)。 - 誘電材料のパターニングされた層を提供するステップ(506)が、
− 導電性トラックと誘電材料の層との積層がその上に製造されなければならない前記基板の第1の表面または第2の表面の上に、誘電材料のパターニングされていない層を提供するステップ(510)と、
− 誘電材料のパターニングされていない層の上にパターニングされたエッチング保護層を提供するステップ(511)と、
− パターニングされたエッチング保護層が存在しない場所の誘電材料のパターニングされていない層をエッチングにより除去するステップ(512)と、
− パターニングされたエッチング保護層を取り除くステップ(513)と、
を備える、請求項15に記載の半導体パワーデバイスを製造する方法(500)。 - 誘電材料のパターニングされた層の上に導電性トラックを提供する(514)ステップが、
− 誘電材料のパターニングされた層の上に焼結される材料を提供するステップ(516)と、
− 導電性トラックを取得するために、誘電材料のパターニングされた層が提供されている前記パターニングされた導電層を備える前記基板を焼結するステップ(518)と、
を備える、請求項15または16に記載の半導体パワーデバイスを製造する方法(500)。
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