CN102194755B - 鳍式场效晶体管及其制造方法 - Google Patents

鳍式场效晶体管及其制造方法 Download PDF

Info

Publication number
CN102194755B
CN102194755B CN201010243829.6A CN201010243829A CN102194755B CN 102194755 B CN102194755 B CN 102194755B CN 201010243829 A CN201010243829 A CN 201010243829A CN 102194755 B CN102194755 B CN 102194755B
Authority
CN
China
Prior art keywords
fin
dielectric material
effect transistor
height
isolation area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201010243829.6A
Other languages
English (en)
Other versions
CN102194755A (zh
Inventor
陈弘凯
林宪信
林家彬
詹前泰
彭远清
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN102194755A publication Critical patent/CN102194755A/zh
Application granted granted Critical
Publication of CN102194755B publication Critical patent/CN102194755B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H01L21/845—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Recrystallisation Techniques (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

本发明公开了鳍式场效晶体管及其制造方法，其方法包含形成延伸至一半导体基底的上方的一第一鳍状物和一第二鳍状物、与位于二者之间的一浅沟槽隔离区。一间隔定义于浅沟槽隔离区的上表面上方的第一与第二鳍状物之间。一第一高度定义于该浅沟槽隔离区的上表面与第一、第二鳍状物的上表面之间。一流动性的介电材料经沉积而置入间隔内。介电材料的上表面位于浅沟槽隔离区的上表面的上方，而在介电材料的上表面与第一、第二鳍状物的上表面之间定义出一第二高度。第二高度小于第一高度。在沉积步骤之后，在第一、第二鳍状物上，分别以外延成长形成位于介电材料上方的第一、第二鳍状物延伸结构。本发明减少或避免相邻的鳍状物延伸结构之间的间隙的窄化。

Description

鳍式场效晶体管及其制造方法
技术领域
本发明涉及半导体制造技术，尤其涉及鳍式场效晶体管及其制造方法。
背景技术
在快速发展的半导体制造工业中，互补式金属—氧化物—半导体晶体管(complementary metal oxide semiconductor；CMOS)鳍式场效晶体管装置是受到许多逻辑元件及其他应用的偏好，并且被整合至各种不同类型的半导体装置。鳍式场效晶体管装置通常具有多个半导体鳍状物，其形成是垂直于基底的上表面，并具有高的高宽比，而半导体晶体管装置的沟道区与源极/漏极区是形成于上述半导体鳍状物中。鳍状物是受到隔离的凸起的结构。一栅极是形成于鳍状物的侧面上方、并沿着鳍状物的侧面而形成，其是利用上述沟道区与源极/漏极区的增加的表面积的优点，来制造较快、可靠度优选、较容易控制的半导体晶体管装置。
图1A是一传统的鳍式场效晶体管100的等角视图(isometric view)。鳍状物105、106具有在一半导体基底101(示于图1C、图1D)上方的凸起的氧化物定义(oxide defined；OD)区105、106。鳍状物105、106是通过一浅沟槽隔离(shallow trench isolation；STI)区102而相互隔离，并位于一对的浅沟槽隔离区104之间。鳍状物105、106是在浅沟槽隔离区102的上表面的上方具有一阶差高度(step height)107。多个复晶硅栅极108是形成于鳍状物105、106的上方。多个侧壁间隔件110是形成于每个栅极108的二侧，以用于形成轻掺杂漏极(lightly doped drain；LDD)区(未示出)。
图1B是显示在提高鳍状物106的Si、SiP或SiC层106e的一外延成长步骤之后的鳍状物106中的一个。鳍状物106的上部的Si、SiP或SiC层106e是获得一大体上五边形的形状，并带有多个横向延伸结构106L，横向延伸结构106L是在半导体基底101(示于图1C、图1D)的上表面的方向延伸。
图1C、图1D是显示在形成氧化硅硬掩模112与虚置侧壁间隔件110之后、但在形成外延层之前的图1A的鳍式场效晶体管100的X方向(前)与Y方向(侧)的正面图(elevation view)。
图1E与图1F是显示在执行双外延工艺后的图1A的鳍式场效晶体管100的X方向(前)与Y方向(侧)的正面图。一光致抗蚀剂(未示出)是形成是沉积于P沟道金属—氧化物—半导体(PMOS)装置的上方，而在N沟道金属—氧化物—半导体鳍状物106上执行一第一外延工艺，而在N沟道金属—氧化物—半导体鳍式场效晶体管的鳍状物106的上方，形成一Si、SiP、或SiC层106e。P沟道金属—氧化物—半导体装置是通过一硅凹入工艺(silicon recess process)来形成，其中N沟道金属—氧化物—半导体装置是受到一光致抗蚀剂(未示出)的掩模，而从P沟道金属—氧化物—半导体虚置鳍状物105蚀刻硅，而由在第二外延形成步骤中成长的SiGe来取代被蚀刻的硅。因此，如图1E与图1F所示，P沟道金属—氧化物—半导体的虚置鳍状物105是被一实体的SiGe结构124的鳍状物所取代。
如图1E所示，P沟道金属—氧化物—半导体鳍状物(SiGe结构124)的外延SiGe横向延伸结构124L与N沟道金属—氧化物—半导体鳍状物106的Si、SiP或SiC层106e的横向延伸结构106L是朝向彼此而横向延伸，降低了相邻的鳍状物的侧向延伸结构之间的空间。
发明内容
为了解决上述问题，本发明在某些实施例中，提供一种鳍式场效晶体管的制造方法是包含形成延伸至一半导体基底的上方的一第一鳍状物和一第二鳍状物、与位于上述第一鳍状物与上述第二鳍状物之间的一浅沟槽隔离区。一间隔是定义于上述浅沟槽隔离区的上表面上方的上述第一鳍状物与第二鳍状物之间。一第一高度是定义于上述浅沟槽隔离区的上表面与上述第一、第二鳍状物的上表面之间。一流动性的介电材料是经沉积而置入上述间隔内。上述介电材料的上表面是位于上述浅沟槽隔离区的上表面的上方，而在上述介电材料的上表面与上述第一、第二鳍状物的上表面之间定义出一第二高度，上述第二高度是小于上述第一高度。在上述沉积步骤之后，在上述第一鳍状物与上述第二鳍状物上，分别以外延成长形成位于上述介电材料上方的一第一鳍状物延伸结构与一第二鳍状物延伸结构。
在某些实施例中，一种鳍式场效晶体管的制造方法是包含形成延伸至一半导体基底的上方的一第一鳍状物和一第二鳍状物、与位于上述第一鳍状物与上述第二鳍状物之间的一浅沟槽隔离区。一间隔是定义于上述浅沟槽隔离区的上表面上方的上述第一鳍状物与第二鳍状物之间。一第一高度是定义于上述浅沟槽隔离区的上表面与上述第一、第二鳍状物的上表面之间。上述第一鳍状物与上述第二鳍状物具有一第一长度方向。在上述第一鳍状物的上方形成一第一栅极。上述第一栅极具有与上述第一长度方向垂直的一第二长度方向。一流动性的氧化硅或氮化硅的介电材料是经由沉积而置入上述间隔内。上述介电材料的上表面是位于上述浅沟槽隔离区的上表面的上方，而在上述介电材料的上表面与上述第一、第二鳍状物的上表面之间定义出一第二高度。上述第二高度是小于上述第一高度。在上述沉积步骤之后，在上述第一鳍状物与上述第二鳍状物上，分别以外延成长形成位于上述介电材料上方的一第一鳍状物延伸结构与一第二鳍状物延伸结构。
在某些实施例中，一种鳍式场效晶体管是包含一第一鳍状物和一第二鳍状物，其延伸至一半导体基底的上方，并带有位于上述第一鳍状物与上述第二鳍状物之间的一浅沟槽隔离区。一间隔是定义于上述浅沟槽隔离区的上表面上方的上述第一鳍状物与第二鳍状物之间。上述第一鳍状物与上述第二鳍状物具有一第一长度方向。一第一栅极是位在上述第一鳍状物的上方。上述第一栅极具有与上述第一长度方向垂直的一第二长度方向。一流动性的介电材料是提供于上述浅沟槽隔离区的上表面上，而定义出上述介电材料的上表面与上述第一、第二鳍状物的上表面之间的一阶差高度，上述阶差高度是小于上述浅沟槽隔离区的上表面与上述第一、第二鳍状物的上表面之间的一距离。一第一外延SiGe横向鳍状物延伸结构与一第二外延SiGe横向鳍状物延伸结构是提供于上述介电材料上方，且分别在上述第一鳍状物与上述第二鳍状物上。上述第一外延SiGe横向鳍状物延伸结构与上述第二外延SiGe横向鳍状物延伸结构的横向延伸是避开上述介电材料的上表面下方的上述第一鳍状物与第二鳍状物的侧缘。
本发明通过一低压化学气相沉积(low pressure chemical vapordeposition；LPCVD)工艺，将一流动性的介电材料沉积于浅沟槽隔离(shallowtrench isolation；STI)区的上方，以减少浅沟槽隔离区的上表面与鳍状物的氧化物定义区的上表面之间的阶差高度。通过减少此阶差高度，可将一目标量的SiGe形成于鳍状物上，伴随着横向鳍状物延伸结构的减少。因此，减少或避免了相邻的鳍状物延伸结构之间的间隙的窄化。
附图说明
图1A是一传统的鳍式场效晶体管的等角视图。
图1B是显示外延成长步骤后的图1A的装置的一个鳍状物。
图1C～图1F是显示在鳍状物上形成外延SiGe之前与之后的鳍式场效晶体管。
图2A～图2X是显示本发明一实施例的一鳍式场效晶体管的制造过程中的各个阶段。
上述附图中的附图标记说明如下：
100～鳍式场效晶体管  101～半导体基底
102～浅沟槽隔离区    104～浅沟槽隔离区
105～鳍状物  106～鳍状物
106e～Si、SiP或SiC层  106L～横向延伸结构
107～阶差高度  108～栅极
109～横向延伸结构
110～侧壁间隔件  112～硬掩模
124～SiGe结构(鳍状物)  124L～横向延伸结构
200～装置  201～半导体基底
202～浅沟槽隔离区  205～第一鳍状物
206～第二鳍状物  206e～Si、SiP或SiC层
207～间隔   207a～第一高度
207b～高度  207c～第二高度
208～栅极(栅导体)  209～横向延伸距离
210～侧壁间隔件  211～延伸长度
212～硬掩模  214～介电膜
214e～回蚀膜    214s～平坦表面
216～氧化物层    218～氮化物层
220～光致抗蚀剂    222～氮化物层
223～凹部    224～光致抗蚀剂
226～SiGe结构
具体实施方式
为让本发明的上述和其他目的、特征、和优点能更明显易懂，下文特举出优选实施例，并配合附图，作详细说明如下：
本案诸位发明人已发现对于现有技术(例如22nm或更小)而言，在鳍式场效晶体管的鳍状物上形成外延SiGe，会严重地使邻近的N沟道金属—氧化物—半导体与P沟道金属—氧化物—半导体的鳍状物的横向延伸结构之间的间隙变窄，而可能会发生桥接。即使并未完成桥接，邻近的鳍状物延伸结构之间的间隙的窄化可能会在第一金属间介电(inter metal dielectric；IMD)层内产生孔洞，其中上述第一金属间介电层是在完成主动元件工艺后沉积。这些孔洞会发生于相邻的P沟道金属—氧化物—半导体装置与N沟道金属—氧化物—半导体装置的鳍状物延伸结构的下方与之间。
图2A～图2X是显示用以减少外延形成的SiGe的横向延伸的方法与结构的一例。通过一低压化学气相沉积(low pressure chemical vapor deposition；LPCVD)工艺，将一流动性的介电材料沉积于浅沟槽隔离(shallow trenchisolation；STI)区的上方，以减少浅沟槽隔离区的上表面与鳍状物的氧化物定义区的上表面之间的阶差高度。通过减少此阶差高度，可将一目标量的SiGe形成于鳍状物上，伴随着横向鳍状物延伸结构的减少。因此，减少或避免了相邻的鳍状物延伸结构之间的间隙的窄化。
在每一对的相邻附图(2A与2B、2C与2D、2E与2F、2G与2H、2I与2J、2K与2L、2M与2N、2O与2P、2Q与2R、2S与2T、2U与2V、2W与2X)中，左边的附图是前(X方向)视图，而鳍状物205、206的长度方向是朝纸面延伸。对应的右边附图是侧(Y方向)视图，而鳍状物205、206的长边方向是从图面的平面由左向右延伸。
图2A与图2B是显示在定义鳍状物205、206、复晶硅栅导体208、侧壁间隔件210与硬掩模212以及执行轻掺杂漏极的掺杂之后的具有N沟道金属—氧化物—半导体与P沟道金属—氧化物—半导体结构的装置200。装置200是具有在一半导体基底201的上方并在一第一长度方向延伸的一第一鳍状物205与一第二鳍状物206，并带有位于第一鳍状物205与第二鳍状物206之间的一浅沟槽隔离区202。一间隔207是定义于浅沟槽隔离区202的上表面上方的第一鳍状物205与第二鳍状物206之间。一第一高度207a是定义于浅沟槽隔离区202的上表面与第一、第二鳍状物205、206的上表面之间。多个栅极208是形成于第一、第二鳍状物205、206的上方。栅极208具有与上述第一长度方向垂直的一第二长度方向。一薄闸介电层(未示出)是形成于鳍状物205、206与栅极208之间。
半导体基底201可以是块硅(bulk silicon)、块硅锗(bulk SiGe)、或其他III-V族的化合物基底。半导体基底201是在鳍状物205、206之间具有浅沟槽隔离区202。
浅沟槽隔离的形成通常包含在硅基底上形成凹部，并使用化学气相沉积(chemical vapor deposition；CVD)例如低压化学气相沉积(low pressurechemical vapor deposition；LPCVD)或等离子体增益化学气相沉积(plasmaenhanced chemical vapor deposition；PECVD)来形成一氧化物膜，然后使用化学机械研磨(chemical mechanical polishing；CMP)来移除多余的浅沟槽隔离氧化物膜。可以以四乙基硅氧烷(tetraethoxysilane；TEOS)、SiO、SiN或同类物质来填充浅沟槽隔离区。在一实施例中，浅沟槽隔离电介质是在高于500℃的温度下以低压化学气相沉积工艺来沉积。形成上述浅沟槽隔离的结果，是在浅沟槽隔离区202的上表面与鳍状物205、206的上表面之间，具有一阶差高度(第一高度)207a。
图2C与图2D是显示通过低压化学气相沉积工艺来沉积对表面起伏不敏感的流动性的介电膜214。介电膜214的高度是高于浅沟槽隔离区202的电介质的上表面，并至少部分地填充间隔207。在某些实施例中，是沉积介电膜214而使其先具有高于鳍状物205、206的氧化物定义的上表面之一平坦表面214s。介电膜214可以是例如氧化硅(SiOx)或氮化硅(SiNx)。因为硅与SiNx的晶格尺寸不同，此氮化物物质的使用会导致压应力源区(compressive stressor region)的形成，而可能是在强化载子迁移率与改善P沟道金属—氧化物—半导体结构的漏极饱和电流Idsat的方面所期盼的，而不会对N沟道金属—氧化物—半导体的Idsat造成实质上的劣化。同样地，在其他实施例中，使用SiOx来作为流动性的电介质会导致张应力源区(tensilestressor region)的形成，以改善N沟道金属—氧化物—半导体结构的特性。
上述流动性的化学气相沉积工艺，是可以在约20℃的温度与约100kPa的压力下执行。在沉积之后，在约200℃的温度与约600Torr的压力下执行约10分钟的一臭氧O3固化步骤。另外，在约400℃的温度下执行约20秒的一O2等离子体处理步骤，以使流动性的化学气相沉积膜的膜质致密化。在O2等离子体处理之后，使用100∶1的稀释HF(氟化氢)的蚀刻率可以降低约80％。沉积的介电膜214的平坦表面214s是具有一高度207b，高度207b是比鳍状物205、206的上表面高约10nm。
图2E与图2F是显示在用于将流动性的化学气相沉积介电膜214的上表面回蚀而使其低于鳍状物205、206的上表面的回蚀步骤之后的装置200的结构。此步骤的执行可使用一化学性的湿蚀刻法例如稀释的氟化氢(dilutehudrogen fluoride；DHF)、一等离子体干蚀刻法或一化学性的干蚀刻法，以部分性地移除化学气相沉积介电膜214。所形成的回蚀膜214e是示于图2E与图2F。上述回蚀工艺是移除化学气相沉积介电膜214的之高于鳍状物205、206的上表面的上部，以准备SiGe凹下的源极、漏极工艺所需的鳍状物，并可将回蚀膜214e回蚀至低于鳍状物205、206的上表面的程度。
上述回蚀工艺定义了介电材料的上表面与第一、第二鳍状物205、206的上表面之间的一第二高度207c，而第二高度207c是小于第一高度207a。第二高度207c是以一个足够的数量差小于第一高度207a，以在后续的外延步骤的过程中，避免第一鳍状物延伸结构与第二鳍状物延伸结构的合并。在某些实施例中，第二高度207c比第一高度207a的比值为约67％或小于67％。在某些实施例中，第二高度207c比第一高度207a的比值为约50％。
在一例子中，为了宽度20nm的鳍状物205、206，起始的阶差高度207a为30nm、而第二高度207c为20nm。因此，第二高度207c比第一高度207a的比值为67％。再另一例子中，为了宽度20nm的鳍状物205、206，起始的阶差高度207a为40nm、而第二高度207c为20nm。因此，第二高度207c比第一高度207a的比值为50％。
图2G与图2H是显示虚置侧壁(dummy sidewall；DSW)的沉积，而可以执行后续的选择性外延成长。首先，一在整个装置的上方形成一顺应性的氧化物(SiOx)层216。然后，将一顺应性的氮化物(SiN)层218形成于氧化物层216的上方。另外，也可执行一轻掺杂漏极的退火。
如图2I与图2J所示，在基底上沉积一光致抗蚀剂220，再执行一光刻工艺以选择性地移除N沟道金属—氧化物—半导体结构上方的光致抗蚀剂220，而保留P沟道金属—氧化物—半导体上方的光致抗蚀剂220。
接下来，执行一异向性蚀刻(例如干蚀刻)，以移除用以形成与N沟道金属—氧化物—半导体结构的栅极208相邻的虚置侧壁间隔件以外的氧化物层216与氮化物层218。然后，如图2K与图2L所示，移除光致抗蚀剂220(例如通过灰化的步骤)。
图2M与图2N是显示双外延工艺(dual epitaxial process)的一部分。将外延Si、SiP或SiC层206e成长于N沟道金属—氧化物—半导体结构的鳍状物206的暴露的上表面与侧缘。由于已减少流动性的化学气相沉积回蚀膜214e的上表面与鳍状物206的上表面之间的阶差高度(第二高度)207c(图2E)，鳍状物206的外延成长会使一横向延伸距离209(图2M)小于一横向延伸结构109(图1E)。在某些实施例中，上述外延步骤会将Si、SiP或SiC层206e的上表面推升至比N沟道金属—氧化物—半导体结构的硅鳍状物206的上表面还高约20nm。虽然此Si、SiP或SiC层206e的20nm的高度是与示于图1E的Si、SiP或SiC层106e的高度相同，但是Si、SiP或SiC层206e上的横向延伸结构较小，因为相对于图1E的阶差高度107之阶差高度207c的减少。
在图2O与图2P中，是通过等向性的蚀刻(例如湿蚀刻)，选择性地蚀除氮化物层218。
在图2Q与图2R中，是在整个装置200的上方形成另一个顺应性的氮化物层222。
接下来，沉积一光致抗蚀剂224并执行一光刻工艺，以移除P沟道金属—氧化物—半导体结构上方的光致抗蚀剂224，而留下N沟道金属—氧化物—半导体结构上方的光致抗蚀剂224，如图2S与图2T所示。
接下来，执行异向性蚀刻(例如干蚀刻)而蚀刻P沟道金属—氧化物—半导体结构的鳍状物205的上部，而在P沟道金属—氧化物—半导体结构的鳍状物205的上部形成一凹部223。此蚀刻步骤也将P沟道金属—氧化物—半导体结构的栅极上方的氮化物层222移除。在此蚀刻步骤之后，移除光致抗蚀剂224(例如通过灰化)，如图2U与图2V所示。
接下来，执行一第二外延成长步骤，而在P沟道金属—氧化物—半导体结构的第二鳍状物205的上表面成长SiGe结构226。与前述的N沟道金属—氧化物—半导体结构的情况相似，P沟道金属—氧化物—半导体结构的横向延伸结构的延伸，是通过小于P沟道金属—氧化物—半导体结构的鳍状物延伸结构124L的长度的一延伸长度211，而避开P沟道金属—氧化物—半导体结构的鳍状物205的侧缘。在某些实施例中，外延成长是将SiGe结构226的上表面推升至比P沟道金属—氧化物—半导体结构的硅鳍状物205的上表面还高约20nm，如图2T所示。如图2W与图2X所示，通过一选择性的蚀刻步骤，移除氮化物层(氮化物硬掩模)222。
然后，执行源极/漏极的掺杂而形成晶体管。
表1是比较不同条件下的横向延伸结构。五行均对应至20nm的鳍状物宽度。五行也均对应至最后的SiGe上表面是比外延工艺之前的原始的鳍状物的上表面还高20nm。在外延工艺之前，第一、第二鳍状物205、206之间的额定的间隙是约50nm。
在表1中，行3是对应至适用图1E与图1F的结构的额定条件，其中浅沟槽隔离区的上表面与鳍状物106、124的上表面之间的阶差高度为30nm。在每个鳍状物的二侧，因为SiGe的成长所造成的横向延伸量为24.7nm。行5是对应至最差的条件(阶差高度为40nm)。在每个鳍状物的二侧的横向延伸量为28.2nm。由于在鳍状物延伸结构之间的间隙的减少，此条件会造成邻近的鳍状物的合并、或是在SiGe横向延伸结构的下方出现空孔。行1是对应至图2W、图2X，其中流动性的介电层214e的上表面与第一、第二鳍状物205、206的上表面之间的阶差高度仅有20nm。横向延伸量则减少为21.2nm，而避免了相邻的鳍状物的合并，并在鳍状物之间留下足够的间隙，而使后续会沉积于鳍式场效晶体管上方的蚀刻停止层(未示出)与金属间介电层(未示出)可以进入并填满鳍状物延伸结构之间的间隙，而避免在金属间介电层内产生空孔。
表1
Figure BSA00000215281700101
在图2A至图2X所示实施例中，SiGe凹部工艺是仅在P沟道金属—氧化物—半导体结构(P沟道金属—氧化物—半导体结构的凹下源极、漏极，或称PSSD步骤)执行。上述PSSD步骤是形成一凹部来取代在鳍状物205的上表面，以获得较大的SiGe体积，如图2W与图2X所示，而且PSSD步骤会止于原始的硅表面。
在其他实施例(未示出)中，是在P沟道金属—氧化物—半导体结构的鳍状物206执行一N沟道金属—氧化物—半导体结构的Si、SiP或SiC的凹下源极、漏极(NSSD)步骤，也是形成一凹部来取代N沟道金属—氧化物—半导体结构的鳍状物的上表面。在具有NSSD步骤的实施例中，是在N沟道金属—氧化物—半导体结构形成较大的Si、SiP或SiC的体积。
在其他实施例(未示出)中，是使用单一的外延步骤，其中对P沟道金属—氧化物—半导体结构的鳍状物的处理，是与对N沟道金属—氧化物—半导体结构鳍状物的处理相同，而未使用Si凹部。
虽然本发明已以优选实施例揭示如上，然其并非用以限定本发明，任何本领域普通技术人员，在不脱离本发明的精神和范围内，当可作些许的更动与润饰，因此本发明的保护范围当视所附的权利要求所界定的范围为准。

Claims (9)

1.一种鳍式场效晶体管的制造方法，包含：
形成延伸至一半导体基底的上方的一第一鳍状物和一第二鳍状物、与位于该第一鳍状物与该第二鳍状物之间的一浅沟槽隔离区，其中，一间隔是定义于该浅沟槽隔离区的上表面上方的该第一鳍状物与第二鳍状物之间，一第一高度是定义于该浅沟槽隔离区的上表面与该些第一、第二鳍状物的上表面之间；
一沉积步骤，沉积一流动性的介电材料而将其置入该间隔内，该介电材料的上表面是位于该浅沟槽隔离区的上表面的上方，而在该介电材料的上表面与该些第一、第二鳍状物的上表面之间定义出一第二高度，该第二高度是小于该第一高度；以及
一外延形成步骤，在该沉积步骤之后，在该第一鳍状物与该第二鳍状物上，分别以外延成长形成位于该介电材料上方的一第一鳍状物延伸结构与一第二鳍状物延伸结构，
其中该第二高度是以一个足够的数量差小于第一高度，以在该外延形成步骤的过程中，避免该第一鳍状物延伸结构与该第二鳍状物延伸结构的合并。
2.如权利要求1所述的鳍式场效晶体管的制造方法，其中该介电材料的沉积步骤包含一低压化学气相沉积工艺，该低压化学气相沉积工艺是在20℃的温度与100kPa的压力下执行。
3.如权利要求2所述的鳍式场效晶体管的制造方法，在该沉积步骤之后，还包含在200℃的温度与600Torr的压力下执行10分钟的一臭氧固化步骤，且在400℃的温度下执行20秒的一O2等离子体处理。
4.如权利要求1所述的鳍式场效晶体管的制造方法，其中该第二高度比该第一高度的比值为50％至67％。
5.如权利要求1所述的鳍式场效晶体管的制造方法，其中该沉积步骤包含：
使该介电材料的一平坦层流动而覆盖在该半导体基底的上方，以完全填满该间隔；以及
回蚀该介电材料，而使回蚀后的该介电材料的上表面低于该第一鳍状物与该第二鳍状物的上表面。
6.如权利要求5所述的鳍式场效晶体管的制造方法，其中使该平坦层流动包含提供一足够量的该介电材料，以在回蚀该介电材料之前，使该介电材料的上表面高于该第一鳍状物与该第二鳍状物的上表面。
7.一种鳍式场效晶体管，包含：
一第一鳍状物和一第二鳍状物，其延伸至一半导体基底的上方，并带有位于该第一鳍状物与该第二鳍状物之间的一浅沟槽隔离区，其中，一间隔是定义于该浅沟槽隔离区的上表面上方的该第一鳍状物与第二鳍状物之间，该第一鳍状物与该第二鳍状物具有一第一长度方向；
第一栅极，位在该第一鳍状物的上方，该第一栅极具有与该第一长度方向垂直的一第二长度方向；
一流动性的介电材料，位于该浅沟槽隔离区的上表面上，而定义出该介电材料的上表面与该些第一、第二鳍状物的上表面之间的一阶差高度，该阶差高度是小于该浅沟槽隔离区的上表面与该些第一、第二鳍状物的上表面之间的一距离；以及
一第一外延SiGe横向鳍状物延伸结构与一第二外延SiGe横向鳍状物延伸结构，其位于该介电材料上方，且分别在该第一鳍状物与该第二鳍状物上，该第一外延SiGe横向鳍状物延伸结构与该第二外延SiGe横向鳍状物延伸结构的横向延伸是避开该介电材料的上表面下方的该第一鳍状物与第二鳍状物的侧缘。
8.如权利要求7所述的鳍式场效晶体管，其中该第一鳍状物与该第二鳍状物的至少一个在其上部具有一凹部，外延SiGe则填入该凹部。
9.如权利要求7所述的鳍式场效晶体管，其中该阶差高度比该距离的比值是50％～67％。
CN201010243829.6A 2010-03-01 2010-08-02 鳍式场效晶体管及其制造方法 Active CN102194755B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/714,796 US8937353B2 (en) 2010-03-01 2010-03-01 Dual epitaxial process for a finFET device
US12/714,796 2010-03-01

Publications (2)

Publication Number Publication Date
CN102194755A CN102194755A (zh) 2011-09-21
CN102194755B true CN102194755B (zh) 2014-02-26

Family

ID=44504844

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201010243829.6A Active CN102194755B (zh) 2010-03-01 2010-08-02 鳍式场效晶体管及其制造方法

Country Status (4)

Country Link
US (2) US8937353B2 (zh)
JP (1) JP5291736B2 (zh)
KR (1) KR101153158B1 (zh)
CN (1) CN102194755B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109786327A (zh) * 2017-11-10 2019-05-21 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法

Families Citing this family (83)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8441072B2 (en) * 2011-09-02 2013-05-14 United Microelectronics Corp. Non-planar semiconductor structure and fabrication method thereof
US9847225B2 (en) * 2011-11-15 2017-12-19 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacturing the same
US8637931B2 (en) 2011-12-27 2014-01-28 International Business Machines Corporation finFET with merged fins and vertical silicide
US8609499B2 (en) * 2012-01-09 2013-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs and the methods for forming the same
US8779517B2 (en) * 2012-03-08 2014-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET-based ESD devices and methods for forming the same
CN103367160B (zh) * 2012-03-31 2015-09-02 中芯国际集成电路制造(上海)有限公司 鳍式场效应管的形成方法
CN102646599B (zh) 2012-04-09 2014-11-26 北京大学 一种大规模集成电路中FinFET的制备方法
US8835243B2 (en) * 2012-05-04 2014-09-16 United Microelectronics Corp. Semiconductor process
US8586455B1 (en) * 2012-05-15 2013-11-19 International Business Machines Corporation Preventing shorting of adjacent devices
US8569152B1 (en) 2012-06-04 2013-10-29 International Business Machines Corporation Cut-very-last dual-epi flow
US8697515B2 (en) * 2012-06-06 2014-04-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method of making a FinFET device
US8729634B2 (en) * 2012-06-15 2014-05-20 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET with high mobility and strain channel
KR101909204B1 (ko) 2012-06-25 2018-10-17 삼성전자 주식회사 내장된 스트레인-유도 패턴을 갖는 반도체 소자 및 그 형성 방법
US9142400B1 (en) 2012-07-17 2015-09-22 Stc.Unm Method of making a heteroepitaxial layer on a seed area
US9059323B2 (en) 2012-08-03 2015-06-16 International Business Machines Corporation Method of forming fin-field effect transistor (finFET) structure
US8703556B2 (en) * 2012-08-30 2014-04-22 Taiwan Semiconductor Manufacturing Company, Ltd. Method of making a FinFET device
CN103681272A (zh) * 2012-09-04 2014-03-26 中芯国际集成电路制造(上海)有限公司 一种鳍片场效应晶体管的制备方法
US8765563B2 (en) * 2012-09-28 2014-07-01 Intel Corporation Trench confined epitaxially grown device layer(s)
KR102049774B1 (ko) 2013-01-24 2019-11-28 삼성전자 주식회사 반도체 장치 및 그 제조 방법
US8921191B2 (en) * 2013-02-05 2014-12-30 GlobalFoundries, Inc. Integrated circuits including FINFET devices with lower contact resistance and reduced parasitic capacitance and methods for fabricating the same
US8823060B1 (en) 2013-02-20 2014-09-02 Taiwan Semiconductor Manufacturing Co., Ltd. Method for inducing strain in FinFET channels
US9034715B2 (en) 2013-03-12 2015-05-19 International Business Machines Corporation Method and structure for dielectric isolation in a fin field effect transistor
US9214555B2 (en) 2013-03-12 2015-12-15 Taiwan Semiconductor Manufacturing Co., Ltd. Barrier layer for FinFET channels
US9443961B2 (en) 2013-03-12 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor strips with undercuts and methods for forming the same
US9824881B2 (en) * 2013-03-14 2017-11-21 Asm Ip Holding B.V. Si precursors for deposition of SiN at low temperatures
US9564309B2 (en) 2013-03-14 2017-02-07 Asm Ip Holding B.V. Si precursors for deposition of SiN at low temperatures
US9087724B2 (en) * 2013-03-21 2015-07-21 International Business Machines Corporation Method and structure for finFET CMOS
US8916932B2 (en) 2013-05-08 2014-12-23 International Business Machines Corporation Semiconductor device including FINFET structures with varied epitaxial regions, related method and design structure
US8981487B2 (en) 2013-07-31 2015-03-17 United Microelectronics Corp. Fin-shaped field-effect transistor (FinFET)
US9105582B2 (en) * 2013-08-15 2015-08-11 United Microelectronics Corporation Spatial semiconductor structure and method of fabricating the same
CN104425372B (zh) * 2013-08-20 2017-07-14 中芯国际集成电路制造(上海)有限公司 反相器的形成方法及反相器
US9112030B2 (en) * 2013-11-04 2015-08-18 United Microelectronics Corp. Epitaxial structure and process thereof for non-planar transistor
US20150145067A1 (en) * 2013-11-28 2015-05-28 United Microelectronics Corp. Fin structure
US9343320B2 (en) 2013-12-06 2016-05-17 Globalfoundries Inc. Pattern factor dependency alleviation for eDRAM and logic devices with disposable fill to ease deep trench integration with fins
CN104733311A (zh) * 2013-12-18 2015-06-24 中芯国际集成电路制造(上海)有限公司 鳍式场效应晶体管的形成方法
CN104752351B (zh) * 2013-12-30 2019-03-29 中芯国际集成电路制造(上海)有限公司 半导体器件的形成方法
KR102157839B1 (ko) 2014-01-21 2020-09-18 삼성전자주식회사 핀-전계효과 트랜지스터의 소오스/드레인 영역들을 선택적으로 성장시키는 방법
KR102193493B1 (ko) 2014-02-03 2020-12-21 삼성전자주식회사 반도체 장치 및 그 제조 방법
US9299780B2 (en) 2014-03-26 2016-03-29 International Business Machines Corporation Constrained epitaxial source/drain regions on semiconductor-on-insulator finFET device
KR102017611B1 (ko) 2014-04-04 2019-09-04 삼성전자주식회사 반도체 장치 및 그 제조방법
US9443963B2 (en) 2014-04-07 2016-09-13 International Business Machines Corporation SiGe FinFET with improved junction doping control
US9887196B2 (en) 2014-04-07 2018-02-06 International Business Machines Corporation FinFET including tunable fin height and tunable fin width ratio
US9985030B2 (en) 2014-04-07 2018-05-29 International Business Machines Corporation FinFET semiconductor device having integrated SiGe fin
US9312360B2 (en) * 2014-05-01 2016-04-12 International Business Machines Corporation FinFET with epitaxial source and drain regions and dielectric isolated channel region
US9312364B2 (en) 2014-05-27 2016-04-12 International Business Machines Corporation finFET with dielectric isolation after gate module for improved source and drain region epitaxial growth
KR102200345B1 (ko) 2014-06-26 2021-01-11 삼성전자주식회사 반도체 소자 및 그 제조방법
CN105304490B (zh) 2014-07-23 2020-09-15 联华电子股份有限公司 半导体结构的制作方法
KR102227128B1 (ko) 2014-09-03 2021-03-12 삼성전자주식회사 반도체 장치 및 이의 제조 방법
US9209279B1 (en) * 2014-09-12 2015-12-08 Applied Materials, Inc. Self aligned replacement fin formation
US9576792B2 (en) 2014-09-17 2017-02-21 Asm Ip Holding B.V. Deposition of SiN
KR102245133B1 (ko) 2014-10-13 2021-04-28 삼성전자 주식회사 이종 게이트 구조의 finFET를 구비한 반도체 소자 및 그 제조방법
US9385191B2 (en) 2014-11-20 2016-07-05 United Microelectronics Corporation FINFET structure
WO2016105412A1 (en) * 2014-12-24 2016-06-30 Intel Corporation Apparatus and methods of forming fin structures with asymmetric profile
CN105826188B (zh) * 2015-01-06 2019-11-01 中芯国际集成电路制造(上海)有限公司 N型鳍式场效应晶体管及其形成方法
CN105826194A (zh) * 2015-01-07 2016-08-03 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法
US9276013B1 (en) 2015-01-21 2016-03-01 International Business Machines Corporation Integrated formation of Si and SiGe fins
US9761699B2 (en) 2015-01-28 2017-09-12 International Business Machines Corporation Integration of strained silicon germanium PFET device and silicon NFET device for finFET structures
US9362407B1 (en) 2015-03-27 2016-06-07 International Business Machines Corporation Symmetrical extension junction formation with low-K spacer and dual epitaxial process in FinFET device
KR102379267B1 (ko) 2015-04-01 2022-03-28 삼성전자주식회사 아이솔레이션 영역 상의 스페이서를 갖는 반도체 소자
US9754941B2 (en) 2015-06-03 2017-09-05 Globalfoundries Inc. Method and structure to form tensile strained SiGe fins and compressive strained SiGe fins on a same substrate
US9935178B2 (en) 2015-06-11 2018-04-03 International Business Machines Corporation Self-aligned channel-only semiconductor-on-insulator field effect transistor
US9627278B2 (en) 2015-06-16 2017-04-18 International Business Machines Corporation Method of source/drain height control in dual epi finFET formation
US9330984B1 (en) * 2015-07-08 2016-05-03 International Business Machines Corporation CMOS fin integration on SOI substrate
US10410857B2 (en) 2015-08-24 2019-09-10 Asm Ip Holding B.V. Formation of SiN thin films
US9450094B1 (en) 2015-09-08 2016-09-20 United Microelectronics Corp. Semiconductor process and fin-shaped field effect transistor
US10529717B2 (en) * 2015-09-25 2020-01-07 International Business Machines Corporation Orientation engineering in complementary metal oxide semiconductor fin field effect transistor integration for increased mobility and sharper junction
KR102323943B1 (ko) 2015-10-21 2021-11-08 삼성전자주식회사 반도체 장치 제조 방법
KR102427326B1 (ko) 2015-10-26 2022-08-01 삼성전자주식회사 반도체 소자 및 이의 제조 방법
US10026662B2 (en) * 2015-11-06 2018-07-17 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure and fabricating method thereof
US9536989B1 (en) 2016-02-15 2017-01-03 Globalfoundries Inc. Field-effect transistors with source/drain regions of reduced topography
KR102521379B1 (ko) 2016-04-11 2023-04-14 삼성전자주식회사 반도체 소자 및 이의 제조 방법
US9917154B2 (en) 2016-06-29 2018-03-13 International Business Machines Corporation Strained and unstrained semiconductor device features formed on the same substrate
US9882051B1 (en) * 2016-09-15 2018-01-30 Qualcomm Incorporated Fin field effect transistors (FETs) (FinFETs) employing dielectric material layers to apply stress to channel regions
US9917210B1 (en) 2016-10-20 2018-03-13 International Business Machines Corporation FinFET transistor gate and epitaxy formation
KR102330087B1 (ko) * 2017-04-03 2021-11-22 삼성전자주식회사 반도체 장치 및 이의 제조 방법
US10847360B2 (en) * 2017-05-25 2020-11-24 Applied Materials, Inc. High pressure treatment of silicon nitride film
CN109273440B (zh) 2017-07-18 2021-06-22 联华电子股份有限公司 具伸张应力鳍状结构的制作方法与互补式鳍状晶体管结构
US10340384B2 (en) * 2017-11-30 2019-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing fin field-effect transistor device
US10727352B2 (en) * 2018-01-26 2020-07-28 International Business Machines Corporation Long-channel fin field effect transistors
TWI705529B (zh) 2018-02-15 2020-09-21 美商應用材料股份有限公司 空氣間隙形成處理
US10529831B1 (en) * 2018-08-03 2020-01-07 Globalfoundries Inc. Methods, apparatus, and system for forming epitaxial formations with reduced risk of merging
US11031489B2 (en) * 2018-09-26 2021-06-08 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device
CN114765171A (zh) 2021-01-14 2022-07-19 联华电子股份有限公司 半导体结构及其制作方法

Family Cites Families (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05218416A (ja) 1992-01-31 1993-08-27 Kawasaki Steel Corp 半導体装置の製造方法
US6413802B1 (en) 2000-10-23 2002-07-02 The Regents Of The University Of California Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture
US6657252B2 (en) 2002-03-19 2003-12-02 International Business Machines Corporation FinFET CMOS with NVRAM capability
US7358121B2 (en) 2002-08-23 2008-04-15 Intel Corporation Tri-gate devices and methods of fabrication
US6706571B1 (en) 2002-10-22 2004-03-16 Advanced Micro Devices, Inc. Method for forming multiple structures in a semiconductor device
US7214991B2 (en) 2002-12-06 2007-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. CMOS inverters configured using multiple-gate transistors
US6815738B2 (en) * 2003-02-28 2004-11-09 International Business Machines Corporation Multiple gate MOSFET structure with strained Si Fin body
TWI231994B (en) * 2003-04-04 2005-05-01 Univ Nat Taiwan Strained Si FinFET
US7045401B2 (en) * 2003-06-23 2006-05-16 Sharp Laboratories Of America, Inc. Strained silicon finFET device
KR100521382B1 (ko) * 2003-06-30 2005-10-12 삼성전자주식회사 핀 전계효과 트랜지스터 제조 방법
KR100513405B1 (ko) 2003-12-16 2005-09-09 삼성전자주식회사 핀 트랜지스터의 형성 방법
US7122412B2 (en) * 2004-04-30 2006-10-17 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating a necked FINFET device
US7355233B2 (en) * 2004-05-12 2008-04-08 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for multiple-gate semiconductor device with angled sidewalls
US6969659B1 (en) * 2004-08-12 2005-11-29 International Business Machines Corporation FinFETs (Fin Field Effect Transistors)
US7244640B2 (en) * 2004-10-19 2007-07-17 Taiwan Semiconductor Manufacturing Company, Ltd. Method for fabricating a body contact in a Finfet structure and a device including the same
US7790633B1 (en) * 2004-10-26 2010-09-07 Novellus Systems, Inc. Sequential deposition/anneal film densification method
US7250657B2 (en) * 2005-03-11 2007-07-31 Taiwan Semiconductor Manufacturing Co., Ltd. Layout structure for memory arrays with SOI devices
US7247887B2 (en) 2005-07-01 2007-07-24 Synopsys, Inc. Segmented channel MOS transistor
US7508031B2 (en) 2005-07-01 2009-03-24 Synopsys, Inc. Enhanced segmented channel MOS transistor with narrowed base regions
US7265008B2 (en) 2005-07-01 2007-09-04 Synopsys, Inc. Method of IC production using corrugated substrate
US7807523B2 (en) 2005-07-01 2010-10-05 Synopsys, Inc. Sequential selective epitaxial growth
US7190050B2 (en) 2005-07-01 2007-03-13 Synopsys, Inc. Integrated circuit on corrugated substrate
US7605449B2 (en) 2005-07-01 2009-10-20 Synopsys, Inc. Enhanced segmented channel MOS transistor with high-permittivity dielectric isolation material
US8466490B2 (en) 2005-07-01 2013-06-18 Synopsys, Inc. Enhanced segmented channel MOS transistor with multi layer regions
US7589387B2 (en) * 2005-10-05 2009-09-15 Taiwan Semiconductor Manufacturing Company, Ltd. SONOS type two-bit FinFET flash memory cell
US7425740B2 (en) * 2005-10-07 2008-09-16 Taiwan Semiconductor Manufacturing Company, Ltd. Method and structure for a 1T-RAM bit cell and macro
US7564081B2 (en) * 2005-11-30 2009-07-21 International Business Machines Corporation finFET structure with multiply stressed gate electrode
JP2007165780A (ja) * 2005-12-16 2007-06-28 Toshiba Corp 半導体装置
US7425500B2 (en) * 2006-03-31 2008-09-16 Intel Corporation Uniform silicide metal on epitaxially grown source and drain regions of three-dimensional transistors
US8946811B2 (en) * 2006-07-10 2015-02-03 Taiwan Semiconductor Manufacturing Company, Ltd. Body-tied, strained-channel multi-gate device and methods of manufacturing same
US8558278B2 (en) * 2007-01-16 2013-10-15 Taiwan Semiconductor Manufacturing Company, Ltd. Strained transistor with optimized drive current and method of forming
US7939862B2 (en) 2007-05-30 2011-05-10 Synopsys, Inc. Stress-enhanced performance of a FinFet using surface/channel orientations and strained capping layers
US8174073B2 (en) * 2007-05-30 2012-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit structures with multiple FinFETs
JP2009032955A (ja) * 2007-07-27 2009-02-12 Toshiba Corp 半導体装置、およびその製造方法
JP2009054705A (ja) * 2007-08-24 2009-03-12 Toshiba Corp 半導体基板、半導体装置およびその製造方法
US7833889B2 (en) * 2008-03-14 2010-11-16 Intel Corporation Apparatus and methods for improving multi-gate device performance
JP5159413B2 (ja) * 2008-04-24 2013-03-06 株式会社東芝 半導体装置及びその製造方法
US8169024B2 (en) * 2009-08-18 2012-05-01 International Business Machines Corporation Method of forming extremely thin semiconductor on insulator (ETSOI) device without ion implantation
US8362568B2 (en) * 2009-08-28 2013-01-29 International Business Machines Corporation Recessed contact for multi-gate FET optimizing series resistance
US8716797B2 (en) * 2009-11-03 2014-05-06 International Business Machines Corporation FinFET spacer formation by oriented implantation

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109786327A (zh) * 2017-11-10 2019-05-21 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法
CN109786327B (zh) * 2017-11-10 2021-07-13 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法

Also Published As

Publication number Publication date
KR20110099156A (ko) 2011-09-07
US8937353B2 (en) 2015-01-20
US20150115322A1 (en) 2015-04-30
KR101153158B1 (ko) 2012-07-03
CN102194755A (zh) 2011-09-21
US20110210393A1 (en) 2011-09-01
US9224737B2 (en) 2015-12-29
JP2011181931A (ja) 2011-09-15
JP5291736B2 (ja) 2013-09-18

Similar Documents

Publication Publication Date Title
CN102194755B (zh) 鳍式场效晶体管及其制造方法
US10515856B2 (en) Method of making a FinFET, and FinFET formed by the method
US9343551B2 (en) Methods for manufacturing a fin structure of semiconductor device
CN103474397B (zh) 制造finfet器件的方法
US8395195B2 (en) Bottom-notched SiGe FinFET formation using condensation
CN103066123B (zh) FinFET器件及其制造方法
CN102074461B (zh) 半导体装置及其制造方法
US9954104B2 (en) Multiwidth finFET with channel cladding
US8062938B2 (en) Semiconductor device and method of fabricating the same
US20120217583A1 (en) Semiconductor device and method for forming the same
TW201334184A (zh) 半導體元件與其形成方法及ｐ型金氧半電晶體
US20160204198A1 (en) High mobility transistors
KR101576529B1 (ko) 습식 식각을 이용한 실리콘 파셋트를 갖는 반도체 장치 및 제조방법
CN104051266A (zh) 用于鳍式场效应晶体管的鳍形状及其形成方法
JPWO2005106949A1 (ja) 半導体の製造方法及び半導体装置
CN106409679A (zh) 具有掺杂的隔离绝缘层的鳍式场效应晶体管
TW201318032A (zh) 半導體裝置及製作磊晶層的方法
US8362530B2 (en) Semiconductor device including MISFET and its manufacture method
US8273620B2 (en) Semiconductor integrated circuit device and related fabrication method

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant