CN101728483B - 介电层夹置的柱状存储装置 - Google Patents

介电层夹置的柱状存储装置 Download PDF

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CN101728483B
CN101728483B CN2009101763803A CN200910176380A CN101728483B CN 101728483 B CN101728483 B CN 101728483B CN 2009101763803 A CN2009101763803 A CN 2009101763803A CN 200910176380 A CN200910176380 A CN 200910176380A CN 101728483 B CN101728483 B CN 101728483B
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李明修
陈介方
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Macronix International Co Ltd
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Abstract

一种存储装置实施例包含一底电极结构及一顶电极结构，及一存储单元在两者之间。该存储单元包含一底存储元件及一顶存储元件，及一介电元件在两者之间。一较低电阻导电路经形成在介电元件。该介电元件具有一外缘和一中心部位，而该外缘较厚于该中心部位。为了制造该存储装置，施加一电性脉冲通过该存储单元以形成一导电路径并通过该介电元件。借着氧化该存储单元的该外表面可以形成一钝化元件，这样亦可以加大该存储元件的该外缘。

Description

介电层夹置的柱状存储装置
技术领域
本发明是有关于以相变化基础存储材料为主的高密度存储装置，包含硫属化物基础材料与其它可程序化电阻材料，以及制造此等装置的方法。
背景技术
以相变化材料为基础的存储器材料，如硫属化物材料及其类似材料，亦可以由施加合适于集成电路操作的电流而改变状态。此通常为非晶状态具有较通常为结晶状态为高的电阻特性，其可以被快速感应资料之用。此等性质有利于作为非挥发性存储器电路的可程序电阻材料，其可以用随机方式进行资料的读取与写入。
非晶状态改变为结晶状态的相变化通常是一较低电流的操作。而自结晶状态改变为结非晶状态的相变化，在此称为重置，一般是为一高电流操作，其包含一短暂的高电流密度脉冲以熔化或破坏结晶结构，其后此相变化材料会快速冷却，抑制相变化的过程，使得至少部份相变化结构得以维持在非晶态。在理想状态下，致使相变化材料从结晶态转变至非晶态的重置电流强度应越低越好。
重置所需的电流强度，可由减低在存储器中的相变化材料元件的尺寸，及/或减少电极与此相变化材料的接触面积，从而对此相变化材料元件施加较小的绝对电流值，便可达成较高的电流密度。
一种用以在相变化细胞中控制主动区域尺寸的方式，是设计非常小的电极以将电流传送至一相变化材料体中。此微小电极结构会在相变化材料中类似蕈状的小区域，即接点部位，诱发相变化。请参照2002/8/22发证给Wicker的美国专利6,429,064号“Reduced Contact Areas of SidewallConductor”、2002/10/8发证给Gilgen的美国专利6,462,353“Method forFabricating a Small Area of Contact Between Electrodes”、2002/12/31发证给Lowrey的美国专利6,501,111号“Three-Dimensional(3D)Programmable Device”、以及2003/7/1发证给Harshfield的美国专利6,563,156号“Memory Elements and Methods for Making same”。
在以非常小的尺度制造这些元件、以及欲满足大规模生产存储元件时所需求的严格工艺变量时，则会遭遇到问题。
要降低所需要的电流量的另外一传统方式是缩小该存储单元的尺寸。然而，这样的方式具有一些问题，因为要制造每一存储单元具有相同尺寸有困难度，然而对于这些存储单元一致性的操作上这却是必要的。另外一种方式是限制由该相变化材料的热散失。若要成功的使用这种方式，但某种程度上也证明了其困难性，因为一般用来做为金属电极不仅仅是好的电性导体更是好的热导体。
因此，需要提供一种具有低电流操作的存储装置并加速工艺，以及制造此种装置的制造方法。
发明内容
一种存储装置实施例包含一底电极结构及一顶电极结构，及一存储单元在两者之间。该存储单元包含一底存储元件包含一底存储材料，借着施加能量在电性特性状态间转换，一顶存储元件包含一顶存储材料，借着施加能量在电性特性状态间转换以及一介电元件，在该底存储元件和该顶存储元件之间。该介电元件包含一导电路径形成该顶存储元件和该底存储元件间的连接。该介电元件的该部位围绕着该导电路径，且该介电元件的该部位具有一电阻大于该导电路径的该电阻。在一些实施例中，该底存储元件和该顶存储元件包含不同的存储材料。在一些实施例中，每一该底存储元件和该顶存储元件包含GST以及该介电元件包含GexOy或SiOx。在一些实施例中，该存储单元在该底电极结构和顶电极结构之间延伸出一外表面，而该外表面具有一钝化元件。在一些实施例中，该介电元件具有一外缘和一中心部位，而该外缘较厚于该中心部位。
一种用来制造一存储装置的方法的一实施例包含形成一底电极结构及一顶电极结构，并在其中间形成一存储单元，该存储单元包含一底存储元件及一顶存储元件，以及在其中间形成一介电元件。执行一电性崩溃步骤于该介电元件，借着施加一电性脉冲于该存储单元，形成通过该介电元件的一导电路径。在一些实施例中，对于该底存储元件和该顶存储元件使用不同的存储材料。一些实施例中，包含形成一钝化元件围绕于该存储单元的外表面。在一些实施例中，该钝化元件可由氧化该外表面来产生。在一些实施例中氧化该外表面加大了该介电元件的该外缘，使得该外缘较厚于该中心部位。
本发明一集成电路的一实施例包含一存储阵列及控制电路。该存储阵列包含多个存储装置。至少一些该存储装置包含一存储单元。该存储单元包含一底存储元件、一顶存储元件，以及一介电元件介于该底存储元件和该顶存储元件之间。在一电性崩溃步骤中适合通过该存储单元施加一电性脉冲的控制电路，以形成通过该介电元件的一导电路径，该介电元件连接该至少某些该存储单元装置的该顶存储元件和该底存储元件，该介电元件围绕在该导电路径的部位具有一电阻大于该导电路径的电阻。在一些实施例中，至少一些该存储装置还包含一钝化元件围绕于该存储单元。在一些实施例中，该导电路径是一电性-脉冲-形成的导电路径。在一些实施例中，该介电元件具有一外缘和一中心部位，而该外缘较厚于该中心部位。
附图说明
凡是本发明的目的及优点等将可通过下列说明的附图、实施方式及权利要求范围获得充分了解，其中：
图1是依据本发明制造的一存储装置的一简单的剖面图。
图2是图1的该装置的一部位的放大图，绘示在该底存储元件和该顶存储元件通过该介电元件及该转变区域的一导电路径。
图3至图5用来制造图1的该存储装置的步骤的示范结构。
图3绘示形成一第一介电层包含底电极、其上的一第一存储元件层、一介电层、一第二存储元件层、及一覆盖层。
图4绘示由图3结构形成具有被一介电层围绕的存储材料柱，且顶电极在其上方。
图5绘示图4的一结构在执行一电性崩溃步骤后产生通过该介电层的导电路径。
图6至图7是依据本发明另一实施例中，具有一钝化元件围绕该存储材料柱以帮忙保护该存储单元的该外表面。
图8是图7的该存储单元的一放大图，较佳地绘示出该介电层的该放大的外缘。
图9是依据本发明一实施例包含一存储装置的一集成电路装置的一方块图，而该存储装置包含具有介电元件的存储单元，且在该底电极元件和该顶电极元件之间通过该介电元件具有一导电路径。
具体实施方式
以下将参照至特定结构实施例与方法而详述本发明。可以理解的是，本发明内容说明章节目的并非在于定义本发明。本发明是由权利要求范围所定义。凡是本发明的实施例、特征、目的及优点等将可通过下列说明申请专利的范围及附图获得充分了解。本发明所述的较佳实施例并不局限其范围，而由权利要求范围中定义。熟习此项技术的人士亦可了解本发明实施方式中的各种等同变化。在本发明中相似元件，将以相似的标号标示的。
图1绘示依据本发明制造一存储装置10的一实施例。该存储装置10包含一底电极结构12、一顶电极结构14、以及在其之间的一存储单元16。该存储单元16包含一底存储元件18、一顶存储元件20以及在其之间的一介电元件22。该底存储元件18及该顶存储元件20分别包含底存储材料和顶存储材料。该存储材料是可在施加能量的状况下在电性特性间转换。最佳地绘示在图2，该介电元件22在该底存储元件18和该顶存储元件20之间形成具有一低电阻的导电路径24连接。该导电路径24较佳地具有一电阻小于该介电元件22的该剩余部位25的该电阻。该介电元件22可为氧化硅或氧化锗。其它介电材料像是氮化硅或许也可以用做为介电元件22，只要它们具有合适的电性崩溃特性。以下将讨论该导电路径24的形成。
该介电元件22较佳地具有一厚度约介于1nm至30nm之间，且通常是约5nm。比起在没有导电路径24的该介电元件22的状况下，由于该导电路径24的该较小直径或薄度，使得要在转变区域28转变该存储材料所需的电流大大地降低。
在一实施例中，该底电极结构12是一栓塞型底电极。在图1的实施例中，该顶电极结构14包含一顶电极30及一选用的保护覆盖层。一般来说，该覆盖层32是由氮化钛制造。在本实施例中，该底存储元件18和该顶存储元件20的该存储材料是由相同或不同的存储材料来制造。举例来说，底存储元件18和该顶存储元件20两者可为相变化型的电阻存储材料，像是GST(Ge、Sb、Te合金)，特别是Ge2Sb2Te5，以及该介电元件22可为GexOv。在一些情况下对于该底存储元件18和该顶存储元件20可能需要使用GST，且在该底存储元件18和该顶存储元件20一种或两种掺杂，使得他们具有不同相变化转换特性。在一些或是所有的情况下，当仅需要在该底存储元件18或该顶存储元件20的一产生一转变区域28时，这种安排是必须的。
该底电极结构12及一顶电极30可包含，例如钨、氮化钛或氮化钽。对于底电极结构12，其中包含有GST(如下讨论)的底存储元件18的实施例中，氮化钛是较佳，因为其与GST具有良好接触，其是一般常用于半导体制造的普通材料，及其提供一良好的扩散阻障层在较高的温度下，一般来说是在600-700℃。或者，该底电极结构12可为氮化铝钛或氮化铝钽，或还包含例如一个以上选自下列群组的元素：钛、钨、钼、铝、钽、铜、铂、铱、镧、镍、氮、氧和钌及其组合。
图3至图5绘示用来制造图1存储装置10的工艺。在一实施例中，形成一底电极结构在一第一介电层36内，接着使用像是一薄膜沉积技术来沉积一第一存储元件层38，使用像是GST及氧气共溅镀技术或使用GeO溅镀或使用SiO2溅镀来形成一介电层40，接着使用一薄膜沉积技术来形成一第二存储元件层42，以及一选用的覆盖层44。将图3的结构转变为图4的结构，像是借着使用一掩膜来移除该存储元件层38、该介电层40、该第二存储元件层42、该覆盖层44的部位而保留材料柱45。而该柱将做为图1的该存储单元16及该覆盖层32元件的基底。接着。借着沉积一第二介电层46以围绕材料柱45并平坦化该所得的结构以产生图4的该平坦化的表面48。接着，在表面48上形成一顶电极30以产生次集合50。然后，借着施加电性脉冲通过该材料柱45以形成该存储装置10的导电路径24，而执行一电性崩溃步骤。在一示范的步骤中，施加具有一5伏特峰值和50ns时间的一电性脉冲至该顶电极30如图5所示以形成导电路径24。该导电路径的形成是由在一已知介电层的电性崩溃路径所产生。可参见，像是美国专利第6,704,235号专利和第7,130,350号专利先前技术部分。
通过使用本发明具有许多额外的优点。因为介电元件22是被包夹于相对较差热传导的底存储元件18和顶存储元件20之间。可降低由转变区域28的热散失，来减少在设置和重置操作时的所需电流。本发明提供好的临界尺寸(CD)控制；借着控制该电性崩溃步骤，像是一电流脉冲的波形和大小，而可以控制该导电路径的一致性和可靠性。该存储单元16的宽度和该底电极12的大小并非固定，而是可以相对地较大，因为对于这样的存储单元结构该操作电流是由导电路径24而决定，而该导电路径24的大小是由该电性崩溃步骤定义。因为在该电性崩溃步骤中施加该电性脉冲来形成该电性路径，而该电性路径24是自动对准，因此可简化工艺。对于设置和重置操作上较低的操作电流，是因为该薄的导电路径24和加热效率，而其是由于在具有低热传导材料的该底存储元件18和该顶存储元件20之间所产生的该导电路径。
图6至图8绘示在本发明中另一实施例的建构步骤。在此实施例中是在材料柱45形成之后，使用一钝化工艺使得一钝化元件52围绕于该材料柱45。要达到此工艺的一种方法是使用氧等离子体去氧化该材料柱45的外表面，这样亦会强化、加大该介电元件22的该外缘54。加大的外缘54可以较佳地参见图8。在图7之后，剩下的步骤是实质地与图3至图5中所讨论的步骤相同。该平坦化步骤移除覆盖于该覆盖层上的该钝化元件52的该部位。之后，执行一电性崩溃步骤来产生该导电路径24。在本实施例中，钝化元件52可以帮助保护该存储单元16的该外表面，且可有助于确认该导电路径24与该介电元件22的外缘54有所分隔，因为在该氧化步骤之后，该外缘54是较厚于该介电元件22的该中央部位；因此该电性崩溃步骤将不会在该加大的外缘54发生，而是朝向于该介电元件22的该中央部位。这是很关键重要的，因为在制造该材料柱的该蚀刻步骤上，该相变化元件的该组合在该材料柱45的外表面是可变换。该介电元件22的该较厚的外缘54将维持该导电路径24隔离该材料柱45的该外表面，因此改善该装置的特性。
图9是为一实施例中的集成电路110的简化方块图，该集成电路110包含一存储阵列112实施于存储装置10。具有读取、设置与重置模式的一字符线译码器114是耦接且电性连接至多条字符线116，并且在存储阵列112中沿着各列排列。一位线(行)译码器118是电性连接至多条位线120，位线120是沿着各列而在存储阵列112中排列，以读取、设置并重置在存储阵列112中的存储单元16。地址是经由总线122而供应至字符线译码器及驱动器114与位线译码器118。在方块124中的感测放大器与资料输入结构，包含用于读取、设置与重置模式中的电压及/或电流源，是经由资料总线126而耦接至位线译码器118。资料是从集成电路110的输入/输出端口、或在集成电路110内部或外部的其它资料源，经由资料输入线128而传送至方块124的资料输入结构。其它电路130是包含于集成电路110之上，例如泛用目的处理器或特殊目的应用电路，或可以提供系统单芯片功能(由阵列112的支持)的模块组合。资料是从方块124中的感测放大器，经由资料输出线132而输出至集成电路110的输入/输出端口，或者传输至集成电路110内部或外部的其它资料目的。
在本实施例中所使用的控制器134使用了偏压安排状态机器，控制了偏压调整供应电压及电流源136的施加，例如读取、设置、重置、以及确认电压及/或字符线与位线的电流，且利用存取控工艺序而控制字符线/源极线操作电压。此控制器134可以利用此领域中所已知的特殊目的逻辑电路而实施。在替代实施例中，控制器包含了一通用目的处理器，其可以实施于同一集成电路上，此集成电路执行了计算机程序以控制此装置的操作。在又一实施例中，特殊目的逻辑电路与泛用目的处理器的组合，可以用来实施此控制器134。
存储单元的实施例包含以相变化为主的存储材料，相变化存储材料包含含硫属化物材料与其它材料。硫属化物包含下列四元素的任一之：氧(O)、硫(S)、硒(Se)、以及碲(Te)，形成元素周期表上第VI族的部分。硫属化物包含将一硫属元素与一更为正电性的元素或自由基结合而得。硫属化合物合金包含将硫属化合物与其它物质如过渡金属等结合。一硫属化合物合金通常包含一个以上选自元素周期表第六栏的元素，例如锗(Ge)以及锡(Sn)。通常，硫属化合物合金包含下列元素中一个以上的复合物：锑(Sb)、镓(Ga)、铟(In)、以及银(Ag)。许多以相变化为基础的存储材料已经被描述于技术文件中，包含下列合金：镓/锑、铟/锑、铟/硒、锑/碲、锗/碲、锗/锑/碲、铟/锑/碲、镓/硒/碲、锡/锑/碲、铟/锑/锗、银/铟/锑/碲、锗/锡/锑/碲、锗/锑/硒/碲、以及碲/锗/锑/硫。在锗/锑/碲合金家族中，可以尝试大范围的合金成分。此成分可以下列特征式表示：TeaGebSb100-(a+b)。一位研究员描述了最有用的合金是为，在沉积材料中所包含的平均碲浓度是远低于70％，典型地是低于60％，并在一般型态合金中的碲含量范围从最低23％至最高58％，且最佳是介于48％至58％的碲含量。锗的浓度是高于约5％，且其在材料中的平均范围是从最低8％至最高30％，一般是低于50％。最佳地，锗的浓度范围是介于8％至40％。在此成分中所剩下的主要成分则为锑。(Ovshinky‘112专利，栏10-11)由另一研究者所评估的特殊合金包含Ge2Sb2Te5、GeSb2Te4、以及GeSb4Te7。(NoboruYamada，”Potential of Ge-Sb-Te Phase-change Optical Disks forHigh-Data-Rate Recording”、SPIE v.3109、pp.28-37(1997))更一般地，过渡金属如铬(Cr)、铁(Fe)、镍(Ni)、铌(Nb)、钯(Pd)、铂(Pt)、以及上述的混合物或合金，可与锗/锑/碲结合以形成一相变化合金其包含有可程序化的电阻性质。可使用的存储材料的特殊范例，是如Ovshinsky ‘112专利中栏11-13所述，其范例在此是列入参考。
在一些实施例中硫属化物及其它相变化材料掺是杂着杂质来修改导电性、变化温度、熔点及使用该掺杂的硫属化物存储元件的其它特性。用来掺杂硫属化物的代表杂质包含：氮、硅、氧、二氧化硅、氮化硅、铜、银、金、铝、氧化铝、钽、氧化钽、氮化钽、钛及氧化钛。可参见美国专利第6800504号专利及美国专利公开号第2005/0029502号专利。
相变化合金能在此细胞主动信道区域内依其位置顺序于材料为一般非晶状态的第一结构状态与为一般结晶固体状态的第二结构状态之间切换。这些合金至少为双稳定态。此词汇“非晶”是用以指称一相对较无次序的结构，其较的一单晶更无次序性，而带有可侦测的特征如较的结晶态更高的电阻值。此词汇“结晶态”是用以指称一相对较有次序的结构，其较的非晶态更有次序，因此包含有可侦测的特征例如比非晶态更低的电阻值。典型地，相变化材料可电切换至完全结晶态与完全非晶态之间所有可侦测的不同状态。其它受到非晶态与结晶态的改变而影响的材料中包含，原子次序、自由电子密度、以及活化能。此材料可切换成为不同的固态、或可切换成为由两种以上固态所形成的混合物，提供从非晶态至结晶态之间的灰阶部分。此材料中的电性质亦可能随的改变。
相变化合金可由施加一电脉冲而从一种相态切换至另一相态。先前观察指出，一较短、较大幅度的脉冲倾向于将相变化材料的相态改变成大体为非晶态。一较长、较低幅度的脉冲倾向于将相变化材料的相态改变成大体为结晶态。在较短、较大幅度脉冲中的能量够大，因此足以破坏结晶结构的键结，同时够短因此可以防止原子再次排列成结晶态。在没有不适当实验的情形下，可以利用实验方法决定特别适用于一特定相变化合金的适当脉冲量变曲线。在本发明的下述部分中，相变化材料是指GST(锗锑碲)，并且可以理解的是，亦可使用其它类型的相变化材料。本发明中所描述适用于PCRAM中的材料是为Ge2Sb2Te5。
可用于本发明其它实施例中的其它可程序化的存储材料包括，掺杂N2的GST、GexSby、或其它以不同结晶态转换来决定电阻的物质；PrxCayMnO3、PrxSryMnO3、ZrOx或其它利用电脉冲以改变电阻状态的材料；或其它使用一电脉冲以改变电阻状态的物质；TCNQ(7，7，8，8-tetracyanoquinodimethane)、PCBM(methanofullerene6，6-phenyl C61-butyric acid methyl ester)、TCNQ-PCBM、Cu-TCNQ、Ag-TCNQ、C60-TCNQ、以其它物质掺杂的TCNQ、或任何其它聚合物材料其包括有以一电脉冲而控制的双稳定或多稳定电阻态。
一种用来形成硫属化物材料的示范方法是利用PVD溅镀或磁控(Magnetron)溅镀方式，其反应气体为氩气、氮气、及/或氦气、压力为1mTorr至100mTorr。此沉积步骤一般是于室温下进行。一长宽比为1-5的准直器(collimater)可用以改良其填入表现。为了改善其填入表现，亦可使用数十至数百伏特的直流偏压。另一方面，同时合并使用直流偏压以及准直器亦是可行的。
有时需要在真空中或氮气环境中进行一沉积后退火处理，以改良硫属化物材料的结晶态。此退火处理的温度典型地是介于100℃至400℃，而退火时间则少于30分钟。
硫属化物材料的厚度是随着细胞结构的设计而定。一般而言，硫属化物的厚度大于3纳米者可以具有相变化特性，使得此材料展现至少双稳定的电阻态。
在上述的实施例中，可使用像是上、下、顶、底、之上、之下等词汇。而这些词汇是用在描述中，其在于帮助了解本发明并非用作于限制之用。
虽然本发明是已参照较佳实施例来加以描述，将为我们所了解的是，本发明创作并未受限于其详细描述内容。替换方式及修改样式是已于先前描述中所建议，并且其它替换方式及修改样式将为熟习此项技术的人士所思及。因此，所有此等替换方式及修改样式是意欲落在本发明于权利要求范围及其均等物所界定的范畴之中。
任何在前文中提及的专利申请案以及印刷文本，均是列为本案的参考。

Claims (13)

1.一种相变化存储装置，包含：
一底电极结构；
一存储单元在该底电极结构之上，包含：
一底存储元件包含一底存储材料，借着施加能量在电性特性状态间转换，该底存储材料为相变化型的电阻存储材料；
一顶存储元件包含一顶存储材料，借着施加能量在电性特性状态间转换，该顶存储材料为相变化型的电阻存储材料；
一介电元件，在该底存储元件和该顶存储元件之间，其包含一形成该顶存储元件和该底存储元件间的连接导电路径；以及
该介电元件围绕着该导电路径的部位具有一电阻大于该导电路径的电阻；以及
一顶电极结构在该存储单元的该顶存储元件之上。
2.如权利要求1所述的存储装置，其中该介电元件具有一厚度介于1nm至30nm之间。
3.如权利要求1所述的存储装置，该顶电极结构包含一顶电极和一覆盖层，该覆盖层介于该顶电极及该顶存储元件之间。
4.如权利要求1所述的存储装置，其中还包含一钝化元件围绕于该存储单元。
5.如权利要求1所述的存储装置，其中该介电元件具有一外缘和一中心部位，而该外缘厚于该中心部位。
6.一种用来制造一相变化存储装置的方法，包含：
形成一底电极结构及一顶电极结构，并在其中间形成一存储单元，该存储单元包含一底存储元件及一顶存储元件，以及在其中间形成一介电元件，其中该底存储元件和顶存储元件包括相变化型的电阻存储材料；以及
执行一电性崩溃步骤于该介电元件，借着施加一电性脉冲于该存储单元，形成通过该介电元件的一导电路径。
7.如权利要求6所述的用来制造一存储装置的方法，其中该介电元件具有一厚度介于1nm至30nm之间。
8.如权利要求6所述的用来制造一存储装置的方法，其中还包含一钝化元件围绕于该存储单元，该钝化元件形成步骤包含氧化该存储单元的一外缘。
9.如权利要求8所述的用来制造一存储装置的方法，其中该介电元件具有一外缘及一中心部位，及该氧化步骤包含放大该外缘，使得该外缘较厚于该中心部位。
10.一集成电路，包含：
一存储阵列包含多个相变化存储装置，至少某些相变化存储装置包含：
一存储单元包含：
一底存储元件，其中该底存储元件包括相变化型的电阻存储材料；
一顶存储元件，其中该顶存储元件包括相变化型的电阻存储材料；以及
一介电元件介于该底存储元件和该顶存储元件之间；以及
一控制电路用于一电性崩溃步骤中施加一电性脉冲于该存储单元，以形成通过该介电元件的一导电路径，该介电元件连接该至少某些存储单元装置的该顶存储元件和该底存储元件，该介电元件围绕该导电路径的部位具有一电阻大于该导电路径的电阻。
11.如权利要求10所述的集成电路，其中至少一些该存储装置还包含一钝化元件围绕于该存储单元。
12.如权利要求10所述的集成电路，其中该导电路径是一电性-脉冲-形成的导电路径。
13.如权利要求10所述的集成电路，其中该介电元件具有一外缘和一中心部位，而该外缘较厚于该中心部位。
CN2009101763803A 2008-10-10 2009-09-28 介电层夹置的柱状存储装置 Active CN101728483B (zh)

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