CN100555653C - 可编程电阻随机存取存储器及其制造方法 - Google Patents
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Abstract
本发明公开一种可编程电阻随机存取存储器单元,其具有与此可编程电阻元件尺寸相关的电阻。本发明还公开此具有均匀电阻值的可编程电阻元件的制造方法及集成电路,此元件具有比层间接触截面小的截面积。
Description
相关申请的交叉引用
本申请要求申请人的美国临时专利申请No.60/757,366“Processof Self-Align Formation of Bi-stable Resistance Random AccessMemory”的优先权日,其申请日为2006年1月9日。
技术领域
本发明涉及非易失性存储集成电路,特别涉及于可编程电阻非易失性存储器,如相变化存储器。
背景技术
非易失性存储器可以在不必持续供应电源的情况下储存数据。可编程电阻非易失性存储器,如相变化存储器即为非易失性存储器的一个范例。高电流重置脉冲将此可编程电阻非易失性存储器融化并快速冷却至非晶结构,而提高此可编程电阻非易失性存储器的电阻。另一方面,低电流设置脉冲将此可编程电阻非易失性存储器的电阻结晶化并降低。
因为电流脉冲类型会决定储存于可编程电阻非易失性存储器的数据,同时可编程电阻非易失性存储器的尺寸大小会帮助决定电流脉冲的特性,因此制造适当尺寸的可编程电阻非易失性存储器是很重要的。
通常而言,一个较小的可编程电阻非易失性存储器单元会与较低振幅的电流脉冲相关。因此,较小的可编程电阻非易失性存储器单元与较低的能量消耗相关。传统的制造较小的可编程电阻非易失性存储器单元的方法依赖于可定义较小单元的照相平板印刷(photolithographic)掩模。然而,使用这样的掩模又会衍生出其他的问题,如,与平面集成电路上已经制造完成的层次之间的正确对准问题。
因此,需要一种能够在不依赖可定义较小单元的照相平板印刷掩模的严格工艺参数的情况下,制造较小尺寸的可编程电阻非易失性存储器单元的方法。
发明内容
本发明的某些实施例公开一种具有非易失性存储单元的集成电路,包括:多个导体行,对该非易失性存储单元按行进行存取;该导体行之上的一个或多个介质层;层间接触点,其具有穿过该一个或多个介质层的均匀的截面,以电连接可编程电阻元件与该导体行;该非易失性存储单元的该可编程电阻元件,具有小于该层间接触点的该截面的截面,该可编程电阻元件包括:邻近于该层间接触点的第一端;第二端;以及多个导体列,对该非易失性存储单元按列进行存取,该导体列邻近于该可编程电阻元件的该第二端。
本发明的另一些实施例公开一种制造具有非易失性存储单元的集成电路的方法,包括:形成多个导体行,对该非易失性存储单元按行进行存取;形成一个或多个介质层于该导体行之上;形成层间接触点,其具有穿过该一个或多个介质层的均匀的截面,以电连接可编程电阻元件与该导体行;形成该非易失性存储单元的该可编程电阻元件,其具有小于该层间接触点的该截面的截面,该可编程电阻元件具有第一端和第二端,其中该第一端邻近于该层间接触点;以及形成多个导体列,对该非易失性存储单元按列进行存取,该导体列邻近于该可编程电阻元件的该第二端。
本发明的某些实施例通孔另一种制造具有非易失性存储单元的集成电路的方法,包括:形成多个导体行,对该非易失性存储单元按行进行存取;形成一个或多个介质层于该导体行之上;形成层间接触点,其具有穿过该一个或多个介质层的均匀的截面,以电连接可编程电阻元件与该导体行,包括:形成具有均匀截面的层间接触点;以及除去该层间接触点的上方部份以形成具有均匀截面的开口,该开口至少部分由形成该可编程电阻元件填充;形成该非易失性存储单元的该可编程电阻元件于由除去该层间接触点的上方部份所形成的开口中;以及形成多个导体列,以对该非易失性存储单元以列进行存取,该导体列邻近于该可编程电阻元件。
在某些实施例中,包括除去介质层直到裸露另一介质层的至少一部分的步骤。此两层介质层具有蚀刻选择差异。
在某些实施例中,包括形成侧壁结构邻近于该层间接触点的该上方部份的至少一部分的步骤,其包括以下步骤:
形成覆盖且邻近该层间接触点的上方部份的介质层的步骤。蚀刻选择差异存在于此介质层与被除去以露出层间接触点的上方部份的另一介质层之间。
除去多余的此介质层,以保留该侧壁结构。
除去该层间接触点的上方部份以形成具有大致均匀截面的开口的步骤,该开口由该可编程电阻元件填充。在某些实施例中,该层间接触点的上方部份被除去,该上方部份邻近于该两个介质层具有蚀刻选择差异之间的至少一界面,由此该两层的下层作为该两层的上层的蚀刻停止层。在另一些实施例中,被除去的该上方部份邻近于介质层,使得该层间接触点与该第一介质层具有蚀刻选择差异,如此该介质层会在除去该层间接触点的上方部份时防止被去除。
形成该可编程电阻元件步骤之前,在由除去该层间接触点的上方部份所形成的开口中形成介质垫层,且也可选择性地覆盖此介质层。也可以选择性地包括下列步骤。
在该开口中形成该介质垫层。其中该层间接触点与该介质垫层具有蚀刻选择差异,同时该介质垫层与其上的介质层之间也具有蚀刻选择差异,如此该介质层会在该除去该介质垫层时防止被去除。
除去该开口中的该介质垫层至少一部分,以裸露至少一部分的该层间接触点的步骤。也可选择性地露出该介质垫层下的该介质层。
形成该非易失性存储单元的该可编程电阻元件于由除去该层间接触点的上方部份所形成的开口中的步骤。这些可编程电阻元件的例子包括:硫属化物、PrxCayMnO3、PxrSryMnO3、ZrOx、双元素存储化合物、TCNQ、以及PCBM。此可编程电阻元件具有比层间接触截面小的截面积,还具有邻近于该层间接触点的第一端和邻近于导体列的第二端。还可以选择性地包括以下步骤:
沉积此可编程电阻材料以部份填充因为该介质垫层而变窄的该开口的步骤。
除去介质层直到至少该可编程电阻元件与环绕的介质材料大致同高为止的步骤。在某些实施例中,这可以通过除去介质层直到一部分的具有研磨选择差异的另一介质层裸露出来为止来实现。
形成多个导体列,以对该非易失性存储单元按列进行存取的步骤,该导体列邻近于该可编程电阻元件。
在某些实施例中,此方法,或一个或多个的步骤,为一自动对准工艺,例如除去该层间接触点的上方部份,以及/或形成该可编程电阻元件的步骤。此自动对准特征可以通过减少照相平板印刷掩模工艺步骤数目,以及增加工艺成品率以减少生产成本。
附图说明
图1示出根据本发明实施例的存储单元的基本结构剖面图,图中显示出晶体管、多重介质层以及层间接触点的形成。
图2的剖面图示出介质层的上层的移除,并停止于次一介质层;
图3为一剖面图,其示出侧壁结构形成于邻近上层的层间接触点处;
图4示出一剖面图,其示出移除部分新介质层的步骤,包括位于接触点上且具有实质上三角形截面的介质结构;
图5示出一剖面图,其示出将层间接触点的顶部部分移除的工艺结果;
图6示出一截面图,其示出将裸露于衬底表面的介质垫层除去后的结果;
图7示出一剖面图,其示出可编程电阻材料50形成于移除接触点上方部分的步骤中所形成的开口内部;
图8示出一剖面图,其示出将集成电路上方部份层次移除后的结果;
图9示出一剖面图,其示出形成金属位线及其上方介质层后的结果;
图10示出一集成电路的方块图,其包括有非易失性可编程电阻存储单元阵列以及其他电路。
主要元件符号说明
8 衬底
10、12 栅极
14、16、18 源/漏极
20、22、24、26、28 介质层
32、34 层间接触点
36、38 侧壁结构
40、42 接触点
44 介质层
46、48 开口
50、52、54 可编程电阻材料
56、58 开口
60、62 可编程电阻元件
64 金属位线
66 金属层间介质层
1000 存储阵列
1001 列解码器
1003 行解码器
1002,1004 位/字线总线
1005,1007 总线
1009 偏压安排状态机
1011 数据输入线
1015 数据输出线
1050 集成电路
具体实施方式
本发明的各实施例涉及存储器的制造方法,例如使用了可编程电阻随机存取存储器的非易失性内置存储器。可编程元件RAM的范例,包括电阻存储器(RRAM)、高分子存储器、以及相变化存储器(PCRAM)。可编程电阻RAM的层间接触点的顶部截面被缩减。
图1示出本发明实施例的存储单元10的基本结构剖面图。图中显示出晶体管、多重介质层以及层间接触的形成。
衬底8(可以是n或p阱)上具有源极和漏极区域14、16和18。栅极10,12为导电行,其用来选择存取可编程电阻RAM单元,并在衬底8中、位于栅极10与12之下、介于区域14与16、区域16与18之间的对应区域中诱发产生沟道。介质层20、22、24、26和28覆盖了衬底8以及栅极10,12。层间接触点32和34物理地且电气地穿过介质层20、22、24、26和28而连接至区域14,18。介质层20,24和28的示例性材料为如SiOx等的氧化物与低介电系数材料,以及其他与晶体管制造相关的介质材料。介质层20的示例性厚度为600纳米。而介质层24和28的示例性厚度范围介于100至200纳米之间。介质层22和26的示例性材料之一为氮化硅,且介质层22和26的示例性厚度为30纳米。层间接触点32,34的示例性材料为钨、未经掺杂的多晶硅、或以p或n掺杂的多晶硅(例如n+掺杂的多晶硅)。
图2为一剖面图,其示出介质层的上层的移除,并停止于次一介质层。
介质层28被移除,露出介质层26以及层间接触点32,34的顶部。为了移除介质层28,可使用湿蚀刻、干蚀刻、或湿蚀刻与干蚀刻的组合。一个示例使用稀释的氢氟酸(DHF)或缓冲氢氟酸(BHF)的湿蚀刻,以蚀刻二氧化硅。在介质层26与介质层28之间的蚀刻选择性的差异足够高,因而使得材料的移除会在介质层26停止。
图3为一剖面图,其示出侧壁结构形成于邻近上层的层间接触点处。
高密度等离子体(HDP)氧化物层被沉积形成,然后被蚀刻以形成侧壁结构36和38。在氧化物与介质层26之间的蚀刻选择性,以及在氧化物与层间接触点32,34之间的蚀刻选择性,必须大到足够除去多余的氧化物,但是又不会伤害到介质层26或是层间接触点32,34。
此蚀刻方法可以使用湿蚀刻、干蚀刻、或湿蚀刻与干蚀刻的组合。一个示例使用稀释的氢氟酸(DHF)或缓冲氢氟酸(BHF)的湿蚀刻,以蚀刻氧化层而保留侧壁结构36和38。
图4为一剖面图,其示出将层间接触点的顶部部分移除的工艺结果。
在此步骤中,可使用湿蚀刻、干蚀刻、或湿蚀刻与干蚀刻的组合。在一实施例中,使用含有六氟化硫(SF6)的反应性离子蚀刻,以针对接触点32,34进行干蚀刻。在接触点32和34与结构36和38之间的蚀刻选择性的差异足够高,因而可避免结构36和38的大幅度蚀刻。同样地,在接触点32和34与介质层20、22、24和26之间的蚀刻选择性的差异足够高,因而可避免介质层20、22、24和26的大幅度蚀刻。将蚀刻时间控制于在接触点32和34之中形成适当深度,如100到500纳米,或是例如在介质层22之下50纳米。即接触点32和34被蚀刻为具有较短高度的40和42。
图5为一剖面图,其示出在接触点周围的开口中形成介质垫层的结果,这些开口在先前移除接触点上方部分的步骤中所形成。
介质垫层44沿着集成电路裸露的表面共形形成。一个介质垫层44材料的例子为利用化学气相沉积(CVD)而得到的氧化硅,其具有低导热性。
图6为一剖面图,其示出将裸露于衬底表面的介质垫层除去后的结果。
此介质垫层44利用各向异性蚀刻。通过先前移除接触点上方部分的步骤中所形成的开口内部的剩余介质垫层为46和48,而各向异性蚀刻停止于层间接触点40和42。通过先前移除接触点上方部分的步骤中所形成的开口外部的各向异性蚀刻停止于介质层26。
图7为一剖面图,其示出可编程电阻材料50形成于移除接触点上方部分的步骤中所形成的开口内部。
可编程电阻元件50,52实际上接触到层间接触点部分40和42,并与之形成电气连接。
存储材料的实施例包括了相变化为基础的存储材料,包括以硫属化物为基础与的材料与其他材料做为电阻元件。硫属化物包括下列四元素中的任一种:氧(O)、硫(S)、硒(Se)、以及碲(Te),形成元素周期表上第VI族的部分。硫属化物包括将一硫属元素与一更为正电性的元素或自由基结合而得。硫属化合物合金包括将硫属化合物与其他物质如过渡金属等结合。硫属化合物合金通常包括一个以上选自元素周期表第六栏的元素,例如锗(Ge)以及锡(Sn)。通常,硫属化合物合金包括下列元素中一个以上的复合物:锑(Sb)、镓(Ga)、铟(In)、以及银(Ag)。许多以相变化为基础的存储材料已在技术文件中进行了描述,包括下列合金:镓/锑、铟/锑、铟/硒、锑/碲、锗/碲、锗/锑/碲、铟/锑/碲、镓/硒/碲、锡/锑/碲、铟/锑/锗、银/铟/锑/碲、锗/锡/锑/碲、锗/锑/硒/碲、以及碲/锗/锑/硫。在锗/锑/碲合金家族中,可以尝试大范围的合金成分。此成分可以下列特征式表示:TeaGebSb100-(a+b)。一位研究员描述了最有用的合金为,在沉积材料中所包括的平均碲浓度远低于70%,典型地低于60%,并在一般类型的合金中的碲含量范围从最低23%至最高58%,且最佳为介于48%至58%得到碲含量。锗的浓度高于约5%,且其在材料中的平均范围从最低8%至最高30%,一般低于50%。最佳地,锗的浓度范围介于8%至40%。在此成分中所剩下的主要成分则为锑。上述百分比为原子百分比,其为所有组成元素总和为100%。(Ovshinky‘112专利,栏10~11)由另一研究者所评估的特殊合金包括Ge2Sb2Te5、GeSb2Te4、以及GeSb4Te7。(Noboru Yamada,”Potential of Ge-Sb-Te Phase-changeOptical Disks for High-Data-Rate Recording”,SPIE v.3109,pp.28-37(1997))更一般地,过渡金属如铬(Cr)、铁(Fe)、镍(Ni)、铌(Nb)、钯(Pd)、铂(Pt)、以及上述的混合物或合金,可与锗/锑/碲结合以形成相变化合金,其包括有可编程的电阻性质。可使用的存储材料的特殊范例,如Ovshinsky‘112专利中栏11-13所述,其范例在此列入参考。
相变化合金能在此单元活性通道区域内依其位置顺序在材料为一般非晶态的第一结构状态与为一般结晶固体状态的第二结构状态之间切换。这些材料至少为双稳定态的。“非晶”一词指相对较无次序的结构,其比单晶更无次序性,而带有可检测的特征,如比结晶态更高的电阻值。“结晶态”指相对较有次序的结构,其比非晶态更有次序,因此包括有可检测的特征,例如比非晶态更低的电阻值。典型地,相变化材料可电切换至完全结晶态与完全非晶态之间所有可检测的不同状态。其他受到非晶态与结晶态的改变而影响的材料特中包括,原子次序、自由电子密度、以及活化能。此材料可切换成为不同的固态、或可切换成为由两种以上固态所形成的混合物,提供从非晶态至结晶态之间的灰阶部分。此材料中的电性质也可能随之改变。
相变化合金可通过施加电脉冲而从一种相态切换至另一相态。先前观察指出,较短、较大幅度的脉冲倾向于将相变化材料的相态改变成大体为非晶态。较长、较低幅度的脉冲倾向于将相变化材料的相态改变成大体为结晶态。在较短、较大幅度脉冲中的能量够大,因此足以破坏结晶结构的键结,同时够短因此可以防止原子再次排列成结晶态。在没有不适当实验的情形下,可决定特别适用于特定相变化合金的适当脉冲量变曲线。在本文的后续部分,此相变化材料以GST代称,同时应该了解,也可使用其他类型的相变化材料。在本文中所描述的一种适用于PCRAM中的材料,为Ge2Sb2Te5。
另一种电阻随机存取存储材料为双元素化合物,例如NixOy、TixOy、AlxOy、WxOy、ZnxOy、ZrxOy、CuxOy等,其中x∶y=0.5∶0.5,或其他成分为x:0~1;y:0~1。同时,使用了如铜、碳六十、银等掺杂物的聚合物,包括四氰代二甲基苯醌(TCNQ,7,7,8,8-tetracyanoquinodimethane)、甲烷富勒烯6苯基C61丁酸甲酯PCBM(methanofullerene 6,6-phenyl C61-butyric acid methyl ester,PCBM)、TCNQ-PCBM、Cu-TCNQ、Ag-TCNQ、C60-TCNQ、以其他物质掺杂的TCNQ、或任何其他聚合物材料,其包括有以电脉冲而控制的双稳定或多稳定电阻态。
接着简单描述四种电阻存储材料。第一种为硫属化物材料,例如GexSbyTez,其中x∶y∶z=2∶2∶5,或其他成分为x:0~5;y:0~5;z:0~10。以氮、硅、钛或其他元素掺杂的GeSbTe也可被使用。
一种用以形成硫属化物材料的示例方法,利用PVD溅镀或磁电管(Magnetron)溅镀方式,其反应气体为氩气、氮气、及/或氦气、压力为1mTorr至100mTorr。此沉积步骤一般在室温下进行。长宽比为1~5的准直器(collimater)可用以改良其填充性能。为了改善其填充性能,也可使用数十至数百伏特的直流偏压。另一方面,同时合并使用直流偏压以及准直器也是可行的。
可以选择性地在真空中或氮气环境中进行沉积后退火处理,以改良硫属化物材料的结晶态。此退火处理的温度典型地介于100℃至400℃,而退火时间则少于30分钟。
硫属化物材料的厚度随着单元结构的设计而定。一般而言,硫属化物的厚度大于8nm的可以具有相变化特性,使得此材料表现出至少双稳定的电阻态。
第二种适合用于本发明实施例中的存储材料为超巨磁阻(CMR)材料,例如PrxCayMnO3,其中x∶y=0.5∶0.5,或其他成分为x:0~1;y:0~1。包括有锰氧化物的超巨磁阻材料也可被使用。
用以形成超巨磁阻材料的示例方法,利用PVD溅镀或磁电管溅镀方式,其反应气体为氩气、氮气、氧气及/或氦气、压力为1mTorr至100mTorr。此沉积步骤的温度可介于室温至600℃,视后处理条件而定。长宽比为1~5的准直器可用以改良其填充性能。为了改善其填充性能,也可使用数十至数百伏特的直流偏压。另一方面,同时合并使用直流偏压以及准直器也是可行的。可施加数十高斯至1特司拉(10,000高斯)之间的磁场,以改良其磁结晶态。
可以选择性地在真空中或氮气环境中或氧气/氮气混合环境中进行沉积后退火处理,以改良超巨磁阻材料的结晶态。此退火处理的温度典型地介于400℃至600℃,而退火时间则少于2小时。
超巨磁阻材料的厚度随着存储单元结构的设计而定。厚度介于10nm至200nm的超巨磁阻材料,可被用作为核心材料。YBCO(YBACuO3,一种高温超导体材料)缓冲层通常被用以改良超巨磁阻材料的结晶态。此YBCO的沉积在沉积超巨磁阻材料之前进行。YBCO的厚度介于30nm至200nm。
第三种存储材料为双元素化合物,例如NixOy、TixOy、AlxOy、WxOy、ZnxOy、ZrxOy、CuxOy等,其中x∶y=0.5∶0.5,或其他成分为x:0~1;y:0~1。用以形成此存储材料的示例方法,利用PVD溅镀或磁电管溅镀方式,其反应气体为氩气、氮气、氧气、及/或氦气、压力为1mTorr至100mTorr,其目标金属氧化物为如NixOy、TixOy、AlxOy、WxOy、ZnxOy、ZrxOy、CuxOy等。此沉积步骤一般在室温下进行。长宽比为1~5的准直器可用以改良其填充性能。为了改善其填充,也可使用数十至数百伏特的直流偏压。若有需要时,同时合并使用直流偏压以及准直器也是可行的。
可以选择性地在真空中或氮气环境或氧气/氮气混合环境中进行沉积后退火处理,以改良金属氧化物内的氧原子分布。此退火处理的温度典型地介于400℃至600℃,而退火时间则少于2小时。
一种替代性的形成方法利用PVD溅镀或磁电管溅镀方式,其反应气体为氩气/氧气、氩气/氮气/氧气、纯氧、氦气/氧气、氦气/氮气/氧气等,压力为1mTorr至100mTorr,其目标金属氧化物为如Ni、Ti、Al、W、Zn、Zr、Cu等。此沉积步骤一般在室温下进行。长宽比为1~5的准直器可用以改良其填充性能。为了改善其填充,也可使用数十至数百伏特的直流偏压。若有需要时,同时合并使用直流偏压以及准直器也是可行的。
可以选择性地在真空中或氮气环境或氧气/氮气混合环境中进行沉积后退火处理,以改良金属氧化物内的氧原子分布。此退火处理的温度典型地介于400℃至600℃,而退火时间则少于2小时。
另一种形成方法,使用高温氧化系统(例如高温炉管或快速热处理(RTP))进行氧化。此温度介于200℃至700℃、以纯氧或氮气/氧气混合气体,在压力为数mTorr至一大气压下进行。进行时间可从数分钟至数小时。另一氧化方法为等离子体氧化。无线射频或直流电压源等离子体与纯氧或氩气/氧气混合气体、或氩气/氮气/氧气混合气体,在压力为1mTorr至100mTorr下进行金属表面的氧化,例如Ni、Ti、Al、W、Zn、Zr、Cu等。此氧化时间从数秒钟至数分钟。氧化温度从室温至约300℃,视等离子体氧化的程度而定。
第四种存储材料为聚合物材料,例如掺杂有铜、碳六十、银等的TCNQ,或PCBM、TCNQ混合聚合物。一种形成方法利用热蒸发、电子束蒸发、或原子束磊晶系统(MBE)进行蒸发。固态TCNQ以及掺杂物丸在单独室内进行共蒸发。此固态TCNQ以及掺杂物丸置于钨船或钽船或陶瓷船中。接着施加大电流或电子束,以熔化反应物,使得这些材料混合并沉积于晶圆之上。此处并未使用反应性化学物质或气体。此沉积作用在压力为10-4Torr至10-10Torr下进行。晶圆温度介于室温至200℃。
可以选择性地在真空中或氮气环境中进行沉积后退火处理,以改良聚合物材料的成分分布。此退火处理的温度典型地介于室温至300℃,而退火时间则少于1小时。
另一种用以形成一层以聚合物为基础的存储材料的技术使用旋转涂布机与经掺杂的TCNQ溶液,转速低于1000rpm。在旋转涂布之后,此晶圆静置(典型地在室温下,或低于200℃的温度)足够的时间以利固态的形成。此静置时间可介于数分钟至数天,视温度以及形成条件而定。
图8为一剖面图,示出将集成电路上方部份层次移除后的结果。
化学机械研磨(CMP)平坦化上表面直到介质层22,将介质层24和26除去。超过介质层22高度的一部分介质垫层46和48也被除去,而留下介质垫层56和58。同时,超过介质层22高度的一部分可编程电阻材料52和54也被除去,而留下可编程电阻材料60和62。此化学机械研磨(CMP)会因为高选择性的研磨液如氧化铯(CeO2)而停止于介质层22。此化学机械研磨(CMP)的结果是所有的可编程电阻元件如60和62具有相同的高度,其会具有在不同的非易失性存储单元之间仅有很小的电阻差异的优点,不管是其所储存的逻辑状态是什么。
图9为一剖面图,示出形成金属位线及其上方介质层后的结果。
金属位线64沿着各列而存取可编程的电阻RAM单元。金属位线64材料的一些范例为氮化钛/铝铜/钛/氮化钛,氮化钽/铜或是氮化钛/钨。另一可实施的方法为全铜工艺。金属层间介质层66先沉积,其材料可为二氧化硅、高密度等离子体氧化物、等离子体增强氧化物等。
图10为一集成电路的方块图,其包括有非易失性可编程电阻存储单元阵列以及其他电路。
集成电路1050包括了存储阵列1000,存储阵列利用在半导体衬底上使用具有电阻元件的存储单元而实施。此存储阵列1000具有如上所述的较窄截面,且利用除去层间接触点上半部的一部份而形成。位址提供总线1005而传送到列解码器1003以及行解码器1001,列解码器1003以及行解码器1001通过位/字线总线1002及1004而与存储阵列1000连接。在方块1006中的感测放大器以及数据输入结构,通过数据总线1007而连接到列解码器1003。数据通过数据输入线1011而从集成电路1050中的输入/输出端口、或从集成电路1050的其他内部或外部来源,传送到方块1006中的数据输入结构。数据通过数据输出线1015而从方块1006传送到集成电路1050的输入/输出端口、或传送到其他位于集成电路1050内部或外部的目的地。集成电路1050也可包括具有电阻元件的非易失性储存(图中未示出)以外的功能电路。偏压安排状态机1009控制此应用的供应电压的偏压安排。
上述的叙述可能使用如上、下、顶、底、覆盖等词汇。这些词汇仅用以协助了解本发明,而非用以限制本发明。
虽然本发明已参照较佳实施例加以描述,应该所了解的是,本发明并不受限于其详细描述的内容。替换方式及修改方式已在先前描述中建议,并且其他替换方式及修改方式将为本领域的技术人员可想到的。特别是,根据本发明的结构与方法,所有具有实质上相同于本发明的构件结合而实现与本发明实质上相同结果的,皆不脱离本发明的精神范畴。因此,所有这些替换方式及修改方式意欲落在本发明所附的权利要求书及其等价物所界定的范畴中。
Claims (22)
1.一种具有非易失性存储单元的集成电路,包括:
多个导体行,对该非易失性存储单元按行进行存取;
该导体行之上的一个或多个介质层;
层间接触点,其具有穿过该一个或多个介质层的均匀的截面,以电连接可编程电阻元件与该导体行;
该非易失性存储单元的该可编程电阻元件,具有小于该层间接触点的该截面的截面,该可编程电阻元件包括:
邻近于该层间接触点的第一端;
第二端;以及
多个导体列,对该非易失性存储单元按列进行存取,该导体列邻近于该可编程电阻元件的该第二端。
2.一种制造具有非易失性存储单元的集成电路的方法,包括:
形成多个导体行,对该非易失性存储单元按行进行存取;
形成一个或多个介质层于该导体行之上;
形成层间接触点,其具有穿过该一个或多个介质层的均匀的截面,以电连接可编程电阻元件与该导体行;
形成该非易失性存储单元的该可编程电阻元件,其具有小于该层间接触点的该截面的截面,该可编程电阻元件具有第一端和第二端,其中该第一端邻近于该层间接触点;以及
形成多个导体列,对该非易失性存储单元按列进行存取,该导体列邻近于该可编程电阻元件的该第二端。
3.如权利要求2所述的方法,其中该形成层间接触点的步骤包括:
除去该层间接触点的上方部份以形成具有均匀截面的开口。
4.如权利要求2所述的方法,其中该形成层间接触点的步骤包括:
除去该层间接触点的上方部份以形成具有均匀截面的开口,该开口至少部分由该可编程电阻元件填充。
5.一种制造具有非易失性存储单元的集成电路的方法,包括:
形成多个导体行,对该非易失性存储单元按行进行存取;
形成一个或多个介质层于该导体行之上;
形成层间接触点,其具有穿过该一个或多个介质层的均匀的截面,以电连接可编程电阻元件与该导体行,包括:
形成具有均匀截面的层间接触点;以及
除去该层间接触点的上方部份以形成具有均匀截面的开口,该开口至少部分由该可编程电阻元件填充;
形成该非易失性存储单元的该可编程电阻元件于由除去该层间接触点的上方部份所形成的开口中;以及
形成多个导体列,以对该非易失性存储单元以列进行存取,该导体列邻近于该可编程电阻元件。
6.如权利要求5所述的方法,其中该形成可编程电阻元件的步骤为自动对准工艺。
7.如权利要求5所述的方法,其中该形成的可编程电阻元件具有小于该层间接触点的该截面的截面,邻近于该层间接触点的第一端,和邻近于该导体列的第二端。
8.如权利要求5所述的方法,还包括:
形成该可编程电阻元件前,形成介质垫层于由除去该层间接触点的上方部份所形成的开口中。
9.如权利要求5所述的方法,其中该形成一个或多个介质层的步骤包括:
形成第一介质层于该导体行之上;
形成第二介质层于该第一介质层至少一部分之上,其中该第一及第二介质层具有蚀刻选择差异;
其中该形成层间接触点,还包括:
除去该第二介质层直到一部分的该第一介质层裸露出来,因此裸露该层间接触点的上方至少一部份。
10.如权利要求5所述的方法,其中除去该层间接触点的上方部份的步骤为自动对准工艺。
11.如权利要求5所述的方法,其中该除去该层间接触点的上方部份的步骤包括:
除去该层间接触点的上方部份,该上方部份邻近于该一个或多个介质层的两层具有蚀刻选择差异之间的至少一界面,如此该两层的下层作为该两层的上层的蚀刻停止层。
12.如权利要求5所述的方法,其中该除去该层间接触点的上方部份的步骤包括:
除去该层间接触点的上方部份,该上方部份邻近于该一个或多个介质层的至少一个第一介质层,且该层间接触点与该第一介质层具有蚀刻选择差异,由此该第一介质层会在该除去时抵抗去除。
13.如权利要求5所述的方法,其中该形成该层间接触点的步骤还包括:
除去该一个或多个介质层的至少一部分以裸露该层间接触点的该上方部份的至少一部分,以裸露该一个或多个介质层的第一介质层;
形成侧壁结构邻近于该层间接触点的该上方部份的至少一部分,包括:
形成第二介质层覆盖和位于邻近该层间接触点的该上方部份,该第一及第二介质层具有蚀刻选择差异;以及
除去多余的该第二介质层,以保留该侧壁结构。
14.如权利要求5所述的方法,其中该形成该层间接触点的步骤还包括:
除去该一个或多个介质层的至少一部分以裸露该层间接触点的该上方部份的至少一部分;
形成侧壁结构邻近于该层间接触点的该上方部份的至少一部分,以及
该方法还包括:
形成该可编程电阻元件前,形成介质垫层于由除去该层间接触点的上方部份所形成的开口中。
15.如权利要求5所述的方法,还包括:
形成该可编程电阻元件前,形成介质垫层于由除去该层间接触点的上方部份所形成的开口中,包括:
形成该介质垫层于该开口中;以及
除去该开口中的该介质垫层至少一部分,以裸露至少一部分的该层间接触点。
16.如权利要求5所述的方法,还包括:
形成该可编程电阻元件前,形成介质垫层于由除去该层间接触点的上方部份所形成的开口中,包括:
形成该介质垫层于该开口中,其中该层间接触点与该介质垫层具有蚀刻选择差异;以及
除去该开口中的该介质垫层至少一部分,以裸露至少一部分的该层间接触点。
17.如权利要求5所述的方法,还包括:
形成一第一介质层;以及
该方法还包括:
形成该可编程电阻元件前,形成介质垫层于该第一介质层之上以及由除去该层间接触点的上方部份所形成的开口中,包括:
形成该介质垫层于该第一介质层之上以及该开口中,其中该层间接触点与该介质垫层之间,和该第一介质层与该介质垫层之间具有蚀刻选择差异,如此该层间接触点与该第一介质层会在该除去该介质垫层时抵抗去除;以及
除去该第一介质层之上以及该开口中的该介质垫层至少一部分,以裸露至少一部分的该层间接触点。
18.如权利要求5所述的方法,还包括:
形成该可编程电阻元件前,形成介质垫层于由除去该层间接触点的上方部份所形成的开口中;以及
其中形成该可编程电阻元件包括:
沉积该可编程电阻元件以部份填充因为该介质垫层而变窄的该开口。
19.如权利要求5所述的方法,其中形成可编程电阻元件包括:
形成的可编程电阻元件包括下列组中的至少一个:硫属化物、PrxCayMnO3、PrSrMnO3、双元素存储化合物、TCNQ、以及PCBM。
20.如权利要求5所述的方法,还包括:
除去该一个或多个介质层直到至少该可编程电阻元件与环绕的介质材料同高为止。
21.如权利要求5所述的方法,其中该形成一个或多个介质层的步骤包括:
形成第一介质层于该导体行之上;
形成第二介质层于该第一介质层的至少一部分之上,其中该第一及第二介质层具有研磨选择差异;以及
该方法还包括:
除去该第二介质层直到一部分的该第一介质层裸露出来,因此除去该一个或多个介质层直到至少该可编程电阻元件与环绕的介质材料同高为止。
22.如权利要求5所述的方法,其中形成可编程电阻元件包括:形成的可编程电阻元件包括ZrOx。
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2006
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- 2006-12-08 TW TW095146128A patent/TWI321357B/zh active
- 2006-12-28 CN CNB2006101727131A patent/CN100555653C/zh active Active
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US7595218B2 (en) | 2009-09-29 |
US20070158690A1 (en) | 2007-07-12 |
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