CN101593740A - 用于半导体器件封装的导电夹片 - Google Patents

用于半导体器件封装的导电夹片 Download PDF

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Publication number
CN101593740A
CN101593740A CNA2008101850811A CN200810185081A CN101593740A CN 101593740 A CN101593740 A CN 101593740A CN A2008101850811 A CNA2008101850811 A CN A2008101850811A CN 200810185081 A CN200810185081 A CN 200810185081A CN 101593740 A CN101593740 A CN 101593740A
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pin
finger
intermediate plate
semiconductor
lead frame
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CN101593740B (zh
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石磊
刘凯
孙明
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Chongqing Wanguo Semiconductor Technology Co., Ltd.
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Alpha and Omega Semiconductor Inc
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Abstract

一种用于半导体器件封装的夹片，包含2个或2个以上分隔开的、且相互间通过一个或多个导电桥电性连接的导电指状引脚。至少一个指状引脚的第一端是适合与引线框架电性接触的。所述导电桥是适用于为其和半导体器件的顶部半导体区域提供电性连接的，并且在指状引脚的顶部表面外露的情况下，也提供热耗散路径。该半导体器件封装包含夹片以及半导体器件和引线框架。该半导体器件在其顶部表面和底部表面分别具有一第一半导体区域。所述的夹片通过导电桥和顶部半导体区域电性连接，且通过至少一个指状引脚的第一端和引线框架电性连接。

Description

用于半导体器件封装的导电夹片
技术领域
本发明一般涉及半导体芯片封装，更具体的，涉及一种适用于芯片封装的源极夹片以提供一种电性连接的方法来降低扩展电阻，并且增强热耗散。
背景技术
在半导体器件的封装中，通常使用一个金属夹片来提供安装在导线框架上的半导体芯片和该导线框架之间的电性连接。例如，美国专利第6,624,522号公开了一种金属氧化物半导体(MOS)栅极器件晶片，其具有一被钝化层覆盖的栅极侧，该钝化层最好是感光的液体环氧树脂层，或者是氮化硅层，或者由其他相似的物质构成。所述的晶片上涂布了纺织物、屏蔽物，或者在晶片表面上沉积液态的环氧树脂。材料干燥后，使用标准光刻技术来暴露被涂布的晶片，从而图案化晶片，并且在钝化层中形成的开口用于在源极金属下方形成许多的间隔分开的暴露表面区域，并且形成一相似的开口用于将晶片上每个芯片的栅极电极下方暴露出来。所述的钝化层除了作为钝化层外，进一步可作为抗电镀剂(如果需要)以及作为焊锡掩模，标示并形成该焊锡区域。
随后，晶圆被锯开或通过其他方法形成单个芯片。所述的单个芯片随后呈U形或杯形状被设置在源极侧的下方，通过使用导电的环氧树脂或焊锡或者类似方法，将电镀漏极夹片的一部分和芯片上可软焊的漏极侧连接，从而将漏极夹片键合到芯片底部漏极电极。漏极夹片的引脚的底部和芯片源极侧的表面(即为突出部分的接触顶面)是位于同一平面的。随后，芯片的外表面使用盘式模型封装。封装后，对该器件进行测试，激光掩模并锯开成各个器件。但是，该器件和标准的导线框架的输出引脚并不兼容。
美国专利6,777,800号公开了一种包含垂直功率MOSFET(金属氧化物半导体场效应晶体管)的半导体芯片封装，该垂直功率MOSFET具有设置在其底部表面上的栅极区域和源极区域，以及设置在其顶部表面上的漏极区域。一栅极引脚电耦合至所述的栅极区域，一源极引脚电耦合至所述的源极区域。一漏极夹片电耦合至所述的漏极区域。使用一不导电的模塑料封装该半导体芯片，其中漏极夹片的表面是外露于该不导电的模塑料的。但是，所述的半导体芯片封装需要进行倒装过程。
美国专利申请公布文件20080087992公开了一种半导体封装，其具有一桥式互连板。该封装利用了一桥式源极互连板，其包含一桥形部分，设置于桥形部分两侧的低凹部分，若干个设置于低凹部分与桥形部分两侧的平面部分，与一个依靠于其中一个平面部分的连接部分。所述的桥形部分所设置的平面是高于低凹部分所处平面的，而所述若干平面部分所设置的平面是介于桥形部分所处的平面与低凹部分所处的平面之间的。在封装过程中，焊锡材料流入桥形部分下方，且为桥式源极互连板提供了机械强度。
需要开发一种能提供高效热耗散，并且以低电阻接入半导体器件的半导体器件封装。进一步，也需要开发一种与标准半导体引脚分布相兼容的封装。更进一步，制造一种具有坚固的应力消除结构，且可灵活用于不同尺寸半导体器件上的半导体器件封装也是需要的。
在这样的背景下提出了本发明的各个实施例。
发明内容
本发明的目的在于提供一种半导体器件封装，用于该半导体器件封装的夹片，以及制成该半导体器件封装的方法，该半导体器件封装具有高效热耗散，以低电阻接入半导体器件；其与标准的半导体封装的引脚分布相兼容，具有坚固的应力消除结构，可灵活用于不同尺寸的半导体器件上。
为达上述目的，本发明提供一种用于半导体器件封装的夹片，其包含2个或2个以上的分隔开的、且相互间通过一个或多个导电桥电性连接的导电指状引脚；其中，至少一个指状引脚的第一端是适合与引线框架电性接触的；所述的导电桥是适用于提供其与半导体器件的顶部半导体区域之间的电性连接的。
该用于半导体器件封装的夹片是由具有导热和导电性质的材料制成的。
在所述的指状引脚的第一侧面和相邻指状引脚的第二侧面之间，包含2个或2个以上所述的导电桥，所述的2个相邻导电指状引脚是通过该2个或2个以上的导电桥连接的。
所述的2个或2个以上的分隔开的导电指状引脚包含第一、第二和第三指状引脚；所述的导电桥包含位于第一指状引脚和第二指状引脚间的第一组导电桥，和位于第二指状引脚和第三指状引脚间的第二组导电桥。
所述的每个导电桥都是“V”形的，该每个“V”形导电桥的底部是适于和第一半导体区域建立电性连接的。
所述的指状引脚和导电桥被配置来提供多个电的平行路径，该多个电的平行路径的相互间通过相邻指状引脚和相邻导电桥之间的间隙分隔开。
所述的其中一个指状引脚的长度没有完全延伸到和芯片一样的长度，以此容纳半导体封装中的其他特征。
本发明还提供一种半导体器件封装，包含：一引线框架，包含一主体部分和若干引脚；一半导体器件，至少包含一位于顶部表面的第一半导体区域和一位于底部表面的第二半导体区域；一夹片，包含2个或2个以上的分隔开的、且相互间通过导电桥电性连接的导电指状引脚；其中，至少一个指状引脚的第一端是与引线框架的引脚电性接触的；所述的夹片通过导电桥和半导体器件的第一半导体区域电性连接；所述的第二半导体区域位于引线框架的主体部分上，并且和该主体部分电性连接。
所述的第一半导体区域是源极区域。
所述的每个导电桥都是“V”形的，该每个“V”形导电桥的底部是适于和第一半导体区域建立电性连接的。
至少一个所述的指状引脚在夹片的顶部平面外呈现弯曲，使得其能够在触点处和引线框架实现连接。
所述的半导体封装用模塑料封装，且各个指状引脚的顶部表面没有被模塑料覆盖。
进一步，所述的半导体器件是MOS器件；则第一半导体区域是源极，第二半导体区域是漏极；该金属氧化物半导体器件进一步包含位于其顶部表面的栅极区域。
所述的栅极通过一键合线和引线框架电性连接；该键合线是被模塑料覆盖的。
所述的栅极通过一栅极夹片和引线框架电性连接；该栅极夹片的顶部表面可以和指状引脚的顶部表面处于同一平面，用模塑料封装后，所述的栅极夹片的顶部表面是外露的；该栅极夹片的顶部表面也可以低于指状引脚的顶部表面，且该栅极夹片的顶部表面被模塑料覆盖。
由所述的引线框架的主体部分引出的所述的一个或多个引脚是和引线框架的主体部分以及第二半导体区域电性连接的；所述的引脚是弯曲的，使得其顶部表面外露于模塑料。
所述的引线框架可以是非熔接引线框架；也可以是熔接的引线框架。
所述的一个或多个指状引脚在位于导电桥和引线框架的接触点之间的夹片顶部平面区域内呈现弯曲，使得指状引脚与引线框架的引脚对准从而和引线框架的引脚连接。
所述的夹片是由具有导热和导电性质的材料制成的，可配置使用于各种尺寸的半导体器件，提供贯穿半导体器件的第一半导体区域的多个平行的导电导热路径。
本发明还提供一种制成半导体器件封装的方法，包含以下步骤：
(a)将一半导体器件安装到引线框架上，该半导体器件包含一位于其顶面的第一半导体区域和一位于其底面的第二半导体区域；由此该第二半导体区域依靠并电性连接该引线框架的主体部分；
(b)将一夹片安装到半导体器件和引线框架上，所述的夹片包含2个或2个以上分隔开的、且相互间通过一个或多个导电桥电性连接的导电指状引脚；其中，至少一个指状引脚的第一端是适合与引线框架的引脚电性接触的；
所述的导电桥是适用于为其和半导体器件的第一半导体区域提供电性连接的；
所述的一个或多个导电桥是安装在半导体器件的第一半导体区域上的，且和该第一半导体区域电性连接；所述的夹片的至少一个指状引脚和引线框架的引脚连接；以及
(c)用模塑料封装半导体器件、部分引线框架和夹片，使得夹片的指状引脚的顶部表面外露于模塑料。
上述步骤中，所述的半导体器件是一垂直MOSFET，其中第一半导体区域是源极区域，第二半导体区域是漏极区域，该MOSFET进一步包含一位于其顶面的栅极区域；
在步骤(a)与步骤(c)之间，进一步包含步骤(d)：将MOSFET的栅极区域连接到引线框架的栅极引脚上。
本发明可提供一种能提供高效热耗散，并且以低电阻接入半导体器件的半导体器件封装，其与标准半导体引脚分布相兼容，可灵活用于不同尺寸的半导体器件上。
附图说明
在参考附图阅读下文的详细描述后，本发明的目的和优点将显而易见，附图中：
图1A为根据本发明的实施例所示的一种半导体器件封装的透视图，该半导体器件封装包含一个没有外露栅极金属线的V形夹片；
图1B为图1A所示的器件封装的侧视图；
图1C为图1A所示的器件封装被封装进模塑料后的透视图；
图2A为根据本发明的另一实施例所示的一种半导体器件封装的透视图，该半导体器件封装包含一个源极夹片和一个外露的栅极夹片；
图2B为图2A所示的器件封装的侧视图；
图2C为图2A所示的器件封装的俯视图；
图2D为图2A所示的器件封装被封装进模塑料后的透视图；
图3A为根据本发明的另一实施例所示的一种半导体器件封装的透视图，该半导体器件封装包含一个源极夹片和一个非外露的栅极夹片；
图3B为图3A所示的器件封装的侧视图；
图3C为图3A所示的器件封装被封装进模塑料后的透视图；
图4A为根据本发明的另一实施例所示的一种半导体器件封装的透视图，该半导体器件封装包含一个源极夹片，该源极夹片具有若干与一个非熔接的引线框架相配的指状引脚；
图4B为图4A所示的器件封装的侧视图；
图4C为图4A所示的器件封装的俯视图；
图4D为根据本发明的另一实施例所示的一种半导体器件封装的透视图，该半导体器件封装包含一个源极夹片，该源极夹片具有若干与一个非熔接的引线框架相配的指状引脚；
图4E为根据本发明的另一实施例所示的一种半导体器件封装的透视图，该半导体器件封装包含一个源极夹片，该源极夹片具有若干与一个非熔接的引线框架相配的指状引脚；
图4F为图4A、4D和4E所示的各器件封装被封装进模塑料后的透视图；
图5A为根据本发明的另一实施例所示的一种半导体器件封装的透视图，该半导体器件封装包含一个源极夹片，该源极夹片具有若干漏极引脚和暴露在同一侧面上的源极和栅极衬垫；
图5B为图5A所示的器件封装的侧视图；
图5C为图5A所示的器件封装被封装进模塑料后的透视图；
图6为根据本发明的实施例所示的形成一个半导体器件封装的流程图。
在上述附图中，相同的技术特征引用相同的附图标号。
具体实施方式
虽然为了说明的目的下文的详尽描述包含了许多特定的细节，但是任何本领域的普通熟练技术人员都将意识到，对于下文细节的许多变化和替代都将属于本发明的范围。因此，下文描述的本发明的示例性实施例将不背离本发明要求保护的基本原理，也不对本发明施加任何限制。
根据本发明的一个实施例，如图1A-1B所示的一个半导体器件封装100，其包含一个V形夹片，该V形夹片利用非外露的栅极金属线键合到引线框架。如图1A所示，所述的器件封装100包含一个熔接的引线框架102和一个半导体器件114，例如，一个具有顶部源极S，顶部栅极G和底部漏极D的MOS器件，其通过底部漏极D和引线框架102的主体部分连接从而位于该引线框架102的顶部。例如，但不限定，所述的引线框架102可以是熔接的或者是非熔接的。在此所说的熔接的引线框架是指该引线框架中的若干源极引脚被熔接在一起。相反的，非熔接引线框架是指该引线框架中的若干源极引脚是相互独立的，没有熔片的(参见图4A-4E所示)。如图1B中清晰所示，无论是上述哪种情况，所述的源极引脚和引线框架的主体部分之间是不存在电性接触的。
根据本发明的一个实施例，所述的半导体器件封装100包含一个夹片112，该夹片112包含若干分隔开的相互平行的导电指状引脚104，该些指状引脚104通过导电桥106相互间电性且机械连接，并且通过导电桥106和半导体器件114的顶部源极之间建立电性连接。这种结构提供了多个电性平行路径，该多个电性平行路径是通过位于相邻的指状引脚104之间以及相邻导电桥106之间的间隙107而相互间分隔开的。例如，但不限定，每个导电桥106具有近似于“V”的形状，且通过“V”形的底部和半导体器件114顶部的源极衬垫实现电性连接。电流可从指状引脚流向顶部源极，或者反过来也是一样的，电流由顶部源极流向“V”形的底部，并通过“V”形两侧和“V”形顶部，流向指状引脚104。所述的导电桥106可以具有其他的形状，例如，“U”形也可以实现所述的源极和相邻指状引脚104之间的电性连接。本文中，“V”形用于描述一种通常的倒拱形状，包括但不仅限于“U”形和其他等同的形状。更好的，导电桥106的形状要考虑到指状引脚104和半导体器件114表面之间的距离，相邻指状引脚104间的缝隙大小，以及半导体器件114表面上的接触区域。在一个优选实施例中，夹片112是由单独的整块材料制成的，例如，由单独的一整块金属冲压制成。
例如，但不限定，半导体器件114可以是金属氧化物半导体(MOS)器件，其具有一顶部源极、一顶部栅极和一底部漏极。在这个例子中，夹片112有时被称为“源极夹片”。夹片112仅仅通过导电桥106与半导体器件114的顶部源极电性连接。每个“V”形的底部被弄平以促进导电桥106和半导体器件114的顶部源极之间的电性连接。半导体器件114的顶部栅极可以通过键合线108与栅极引脚110实现电性连接。导电指状引脚104弯曲在夹片112的平面外发生弯曲，从而使得其能够垂直的连接到熔接的源极引脚118，由此可节省半导体器件封装100的封装空间。
如图1C所示，半导体器件封装100被封装进模塑料116中，且仅仅外露出各个指状引脚104的顶部。但是在这个例子中，键合线108完全被模塑料116覆盖住了。例如，但不限定，所述的模塑料116可以是环氧树脂。
由于热膨胀导致的硅和金属之间的不匹配会引起压力甚至分裂。如果在所述的硅和金属之间具有一个大的单独的接触区域，那么这个问题会更恶化。可以通过在半导体器件100内将所述的接触区域分裂成若干较小的区域块来解决上述问题。所述的夹片112通过由导电桥106提供的多个接触点，在夹片112和MOS器件114之间提供一个压力缓解结构，当夹片112被封装进模塑料116中时，这个压力缓解结构对制作指状引脚104的顶部表面提供较大的帮助。该导电桥106也可以增加封装的机械强度，因为其为模塑料116提供了多个位于不同角度的固定性能。
在夹片112中，通过导电桥106和指状引脚14实现电性接触的方法降低了扩展电阻。所述的扩展电阻是指由于电流由接触点横向流向导体时，导体中的电流发生扩散而产生的电阻。可以通过分布多个平行的传导路径来引导电流穿过位于半导体器件114顶部的触点衬垫的方式来减少扩展电阻。相比于在美国专利申请公布文件20080087992中所描述的触点被密集设置，或者触点的数目较少的源极夹片结构，如图1A-1D中所示的夹片类型具有一个较低的电阻。在图1A-1D所示的例子中，夹片112包含3个长的指状引脚104和一个较短的指状引脚104。在这个特殊的例子中，当外露区域的面积增加以使得通过导电桥的接触点更多时，该较短的指状引脚104可以调节平衡栅极区域。
本发明的另一个优点是和标准的半导体封装的引脚相兼容匹配。由此，本发明可以通过现存的设备实现，而不需要改变电路板或者其他周边元件的设计。
图2A-2D是根据本发明的一个较佳实施例所示的半导体器件封装200。该半导体器件封装200基本包含以上图1A-1C中所描述的半导体器件封装100的所有元件，除了用栅极夹片208替换之前的栅极键合线108。所述的器件封装200包含一熔接的引线框架102，一包含顶部源极、顶部栅极和底部漏极的MOS器件114，该MOS器件114位于引线框架102的顶部，一包含若干分隔开的相互平行的导电指状引脚104的夹片112，其中所述的若干导电指状引脚104通过导电桥106相互间电性连接。所述的夹片112仅仅通过导电桥106和MOS器件114的顶部源极电性接合。如图1A-1C所示，该指状引脚104在夹片112的平面外发生弯曲，使得其能够垂直的连接到熔接的源极引脚118。在本实施例中，顶部栅极通过栅极夹片208电连接到引线框架102的栅极引脚110。在图2B所示的侧视图中可以看到，本实施例中，栅极夹片208的顶部表面和夹片112的顶部表面是在同一平面上的。图2D是半导体器件封装200在被模塑料116覆盖封装后的透视图。如图2D所示，夹片112和栅极夹片208的顶部表面是外露的。
图3A根据本发明的另一个实施例所示的半导体器件封装300的透视图。本实施例是如图2A-2D所示的实施例的一种变化。半导体器件封装300基本包含了如图2A-2D所示的半导体器件封装200的所有元件。本实施例中，顶部栅极通过一栅极夹片308和引线框架102的栅极引脚110实现电性连接。但是，如图3B所示，栅极夹片308的顶部表面要低于夹片112的指状引脚104的顶部表面。如图3C所示，当半导体器件封装300被装进模塑料116后，由于夹片112和栅极夹片308的高度不同，当栅极夹片308被模塑料116覆盖住时，而指状引脚104的顶部表面是外露的。
图4A-4D是根据本发明的一个实施例描述了一半导体器件封装400。例如，但不限定，所述的半导体器件封装400包含一非熔接的引线框架402，一包含顶部源极、顶部栅极和底部漏极的MOS器件414，该MOS器件414位于该非熔接的引线框架402的顶部，还包含一源极V形夹片412，其和MOS器件414的顶部源极电性连接。该非熔接的引线框架402包含若干非熔接的源极引脚413。所述的源极夹片412包含若干分隔开的相互平行的导电指状引脚404，该导电指状引脚404相互间通过导电桥406电性连接。该源极夹片412仅仅通过导电桥406和MOS器件414的顶部源极电耦合连接。相邻的指状引脚404和相邻的导电桥406之间被间隙407分隔开。所述的在导电桥和引线框架402的非熔接的源极引脚413之间的那部分指状引脚404在夹片412的平面内发生弯曲，使得指状引脚404和非熔接的源极引脚413对准。进一步，所述的指状引脚404在夹片412的平面外发生弯曲，使得其与非熔接的源极引脚413接触连接。MOS器件的顶部栅极和引线框架402的栅极引脚410通过栅极夹片408实现电性连接。如图4B所示，栅极夹片408的顶部表面低于夹片412的指状引脚404的顶部表面。可替换的(未显示)，栅极夹片的顶部表面可以和夹片412的指状引脚404的顶部表面位于同一片面，并且在封装进模塑料418后均外露顶部。
如图4D-4E所示，所述的V形夹片412可以用于不同设计的MOS器件。详细的，半导体器件封装401和403可以各自包含不同大小尺寸的半导体器件415和416。所述导电桥分散的分布形式保证了MOS器件的充分接触，即使有些导电桥并未使用到。由于相同的夹片能被用于不同尺寸大小的器件，这会同时增加设计的灵活性以及因经营规模扩大而得到的经济节约。当然，对于熔接引线框架的夹片而言，例如图1A中所示的夹片112，其也可用于不同尺寸大小的器件。如图4F所示，为图4A-4D以及图4E所描述的不同类型的半导体器件封装被模塑料418封装覆盖后的示意图。图4F中，夹片412的顶部表面是外露的，而栅极夹片408是被模塑料418覆盖住的。
图5A为根据本发明的另一实施例所示的半导体器件封装500的透视图。该半导体器件封装500是上述图2A-2D所描述的半导体器件封装200的变化。该半导体器件封装500包含一熔接的引线框架102，一包含顶部源极、顶部栅极和底部漏极的半导体器件114，该半导体器件114位于引线框架所述引线框架102的顶部，一包含若干分隔开的指状引脚104的夹片112，其中所述的若干指状引脚104通过导电桥106相互间电性连接。所述的夹片112仅仅通过导电桥106和半导体器件114的顶部源极电性接合。指状引脚104在夹片112的平面外发生弯曲，使得其能够垂直的连接到熔接的源极引脚118。半导体器件114的顶部栅极通过栅极夹片208和引线框架102的栅极引脚110电性连接。导线框架102的漏极引脚和半导体器件114的底部漏极电性连接，该漏极引脚包含漏极引脚延伸区504，其被建立并弯曲以提供一个外露的顶部连接区，该顶部连接区的表面和源极夹片112以及栅极夹片208的表面在同一平面上。如图5B所示，即漏极引脚延伸区504、栅极夹片208以及源极夹片112的顶部表面是位于同一平面的。半导体器件封装500的部分被模塑料516覆盖。如图5C所示，漏极引脚延伸区504、栅极夹片208以及源极夹片112的顶部表面都是外露的。由于漏极、栅极和源极的电性接触区域均设置在顶部，该半导体器件封装500可以倒装安装在电路板上。在倒装结构中，引线框架102的底部表面(也就是现在朝上的正表面)可以被设置为外露的，以用于热耗散。可替代的，也可在引线框架102的底部表面(仍旧为现在朝上的正表面)上安装一散热片。
有很多不同的方法可以用来在半导体器件封装中使用上述的各种类型的夹片以制成该半导体器件封装。图6中显示的流程图仅举例描述了制成半导体器件封装的一种方法600。该方法可以参考上述根据图1A-1C所示的半导体器件封装的例子来了解。如在步骤610中所指出的，半导体器件114包含一位于其顶部的第一半导体区域，以及一位于其底部的、且连接到引线框架102上的第二半导体区域，由此，该第二半导体区域依靠并电性连接该引线框架的主体部分。例如，可以通过以下步骤来完成：首先，在引线框架102的主体部分上分配设置焊锡膏，随后将半导体器件114放置到焊锡膏上。
如在步骤620中所指出的，将具有导电指状引脚104和导电桥106的夹片112粘附安装到半导体器件114上，使得导电桥106的基底和半导体器件114的第一半导体区域相接触连接，并且使得一个或多个指状引脚104和引线框架102的引脚118相接触连接。上述过程可以通过以下步骤来完成：首先，在第一半导体区域和引脚118的接触区域上分配设置焊锡，随后将夹片112粘附上去。此时，进行焊锡回流的操作，用以分别在引线框架102和半导体器件114、半导体器件114和夹片112以及夹片112和引脚118之间形成焊锡接合点。随后，如在步骤630中所指出的，模塑料116被封装在半导体器件114、夹片112和引线框架102的部分的周围。然而，夹片112的指状引脚104的顶部表面是穿过模塑料116暴露在外的。然后，进行一些标准的步骤，包括硬化模具，在封装上激光打标，去除垃圾，去除毛刺，电镀和/或修整引线框架/封装元件。可选择的，还可在指状引脚104的外露顶部表面上附加安装一散热片。
尽管本说明书中所提到的实施例是顶部源极半导体器件，但本发明的范围并不仅限于这种器件。例如，本发明的实施例也同样适用于底部源极的半导体器件。本发明的核心夹片112和412也都适用于除了MOS器件以外的各种半导体器件，例如但不限定：功率双极结型晶体管(BJT)，绝缘栅双极型晶体管(IGBT)，晶体闸流管，二极管，电容器或电阻器。当然，夹片112和412在设计上可以有非常多的变化。指状引脚的数量，长度，宽度和形状，指状引脚间的间距，以及导电桥之间的间距仅仅只是变化的一小部分，而且是可以调整的。并且，尽管本说明书中仅仅举例说明了适用于一种特殊类型的半导体封装(例如DFN5x6)的夹片，但是，本发明的各实施例可以适用于其他类型的半导体封装，例如，TO220，TSOP和SOT等。因此，本发明的实施例没有限制适用于任何一种特殊类型的半导体封装。
虽然上文对本发明的优选实施例进行了完整的描述，但是还可以使用各种替代，修改和等效形式。因此，本发明的范围不应参考上文的描述确定，而是应该参考附后的权利要求及其等效内容的全部范围确定。任何技术特征不论是否优选都可以和任何其它不论是否优选的技术特征组合。在附后的权利要求中，原文中的不定冠词″A″或″An″指该冠词之后的项目的数量为一个或多个，除非另有明确的指定。附后的权利要求不应解释为包括方法加功能的限制，除非这样的限制在所给出的权利要求中用词语“其意义为”明确地指出。

Claims (27)

1.一种用于半导体器件封装的夹片，其特征在于，包含：
2个或2个以上的分隔开的、且相互间通过一个或多个导电桥电性连接的导电指状引脚；其中，至少一个指状引脚的第一端是适合与引线框架电性接触的；
所述的导电桥是适用于提供其与半导体器件的顶部半导体区域之间的电性连接的。
2.如权利要求1所述的夹片，其特征在于，在指状引脚的第一侧面和相邻指状引脚的第二侧面之间，包含2个或2个以上所述的导电桥，所述的2个相邻导电指状引脚是通过该2个或2个以上的导电桥连接的。
3.如权利要求1所述的夹片，其特征在于，所述的2个或2个以上的分隔开的导电指状引脚包含第一、第二和第三指状引脚；所述的导电桥包含位于第一指状引脚和第二指状引脚间的第一组导电桥，和位于第二指状引脚和第三指状引脚间的第二组导电桥。
4.如权利要求1所述的夹片，其特征在于，所述的每个导电桥都是“V”形的，该每个“V”形导电桥的底部是适于和第一半导体区域建立电性连接的。
5.如权利要求1所述的夹片，其特征在于，所述的夹片是由具有导热和导电性质的材料制成的。
6.如权利要求1所述的夹片，其特征在于，所述的指状引脚和导电桥被配置来提供多个电的平行路径，该多个电的平行路径的相互间通过相邻指状引脚和相邻导电桥之间的间隙分隔开。
7.如权利要求1所述的夹片，其特征在于，所述的其中一个指状引脚的长度没有完全延伸到和芯片一样的长度，以此容纳半导体封装中的其他特征。
8.一种半导体器件封装，其特征在于，包含：
一引线框架，其包含一主体部分和若干引脚；
一半导体器件，其至少包含一位于顶部表面的第一半导体区域和一位于底部表面的第二半导体区域；
一夹片，其包含2个或2个以上的分隔开的、且相互间通过导电桥电性连接的导电指状引脚；其中，至少一个指状引脚的第一端是与引线框架的引脚电性接触的；
所述的夹片通过导电桥和半导体器件的第一半导体区域电性连接；
所述的第二半导体区域位于引线框架的主体部分上，并且和该主体部分电性连接。
9.如权利要求8所述的半导体器件封装，其特征在于，所述的第一半导体区域是源极区域。
10.如权利要求8所述的半导体器件封装，其特征在于，所述的每个导电桥都是“V”形的，该每个“V”形导电桥的底部是适于和第一半导体区域建立电性连接的。
11.如权利要求8所述的半导体器件封装，其特征在于，至少一个指状引脚在夹片的顶部平面外呈现弯曲，使得其能够在触点处和引线框架实现连接。
12.如权利要求8所述的半导体器件封装，其特征在于，所述的半导体封装用模塑料封装，且各个指状引脚的顶部表面没有被模塑料覆盖。
13.如权利要求12所述的半导体器件封装，其特征在于，所述的半导体器件是金属氧化物半导体器件；
所述的第一半导体区域是源极，第二半导体区域是漏极；以及
所述的金属氧化物半导体器件进一步包含位于其顶部表面的栅极区域。
14.如权利要求13所述的半导体器件封装，其特征在于，所述的栅极通过一键合线和引线框架电性连接。
15.如权利要求14所述的半导体器件封装，其特征在于，所述的键合线是被模塑料覆盖的。
16.如权利要求13所述的半导体器件封装，其特征在于，所述的栅极通过一栅极夹片和引线框架电性连接。
17.如权利要求16所述的半导体器件封装，其特征在于，所述的栅极夹片的顶部表面和指状引脚的顶部表面处于同一平面，用模塑料封装后，所述的栅极夹片的顶部表面是外露的。
18.如权利要求16所述的半导体器件封装，其特征在于，所述的栅极夹片的顶部表面低于指状引脚的顶部表面，且该栅极夹片的顶部表面被模塑料覆盖。
19.如权利要求12所述的半导体器件封装，其特征在于，由引线框架的主体部分引出的所述的一个或多个引脚是和引线框架的主体部分以及第二半导体区域电性连接的；所述的引脚是弯曲的，使得其顶部表面外露于模塑料。
20.如权利要求8所述的半导体器件封装，其特征在于，所述的引线框架是非熔接引线框架。
21.如权利要求8所述的半导体器件封装，其特征在于，所述的引线框架是熔接的引线框架。
22.如权利要求8所述的半导体器件封装，其特征在于，所述的一个或多个指状引脚在位于导电桥和引线框架的接触点之间的夹片顶部平面区域内呈现弯曲，使得指状引脚与引线框架的引脚对准从而和引线框架的引脚连接。
23.如权利要求8所述的半导体器件封装，其特征在于，所述的夹片是由具有导热和导电性质的材料制成的。
24.如权利要求8所述的半导体器件封装，其特征在于，所述的夹片配置使用于各种尺寸的半导体器件。
25.如权利要求8所述的半导体器件封装，其特征在于，所述的夹片提供贯穿半导体器件的第一半导体区域的多个平行的导电导热路径。
26.一种制成半导体器件封装的方法，其特征在于，包含步骤：
(a)将一半导体器件安装到引线框架上，该半导体器件包含一位于其顶面的第一半导体区域和一位于其底面的第二半导体区域；由此该第二半导体区域依靠并电性连接该引线框架的主体部分；
(b)将一夹片安装到半导体器件和引线框架上，所述的夹片包含2个或2个以上分隔开的、且相互间通过一个或多个导电桥电性连接的导电指状引脚；其中，至少一个指状引脚的第一端是适合与引线框架的引脚电性接触的；
所述的导电桥是适用于为其和半导体器件的第一半导体区域提供电性连接的；
所述的一个或多个导电桥是安装在半导体器件的第一半导体区域上的，且和该第一半导体区域电性连接；所述的夹片的至少一个指状引脚和引线框架的引脚连接；以及
(c)用模塑料封装半导体器件、部分引线框架和夹片，使得夹片的指状引脚的顶部表面外露于模塑料。
27.如权利要求26所述的方法，其特征在于，所述的半导体器件是一垂直金属氧化物半导体场效应晶体管，所述的第一半导体区域是源极区域，第二半导体区域是漏极区域，所述的金属氧化物半导体场效应晶体管进一步包含一位于其顶面的栅极区域；并且所述方法在步骤(a)与步骤(c)之间，进一步包含：
(d)将金属氧化物半导体场效应晶体管的栅极区域连接到引线框架的栅极引脚上。
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CN109065516B (zh) * 2018-07-23 2020-07-21 苏州锝耀电子有限公司 大功率芯片封装生产方法
CN109003947A (zh) * 2018-07-23 2018-12-14 苏州锝耀电子有限公司 大功率层叠式芯片结构
CN110400786A (zh) * 2019-07-17 2019-11-01 杰群电子科技（东莞）有限公司 一种无引脚封装半导体产品及其加工方法
CN110400786B (zh) * 2019-07-17 2021-04-20 杰群电子科技（东莞）有限公司 一种无引脚封装半导体产品及其加工方法

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