CN106252287B - 包括夹件的半导体装置 - Google Patents
包括夹件的半导体装置 Download PDFInfo
- Publication number
- CN106252287B CN106252287B CN201610391189.0A CN201610391189A CN106252287B CN 106252287 B CN106252287 B CN 106252287B CN 201610391189 A CN201610391189 A CN 201610391189A CN 106252287 B CN106252287 B CN 106252287B
- Authority
- CN
- China
- Prior art keywords
- folder
- lead
- engagement disk
- disk
- chamber
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 93
- 229910000679 solder Inorganic materials 0.000 claims abstract description 68
- 239000000843 powder Substances 0.000 claims abstract description 35
- 238000005476 soldering Methods 0.000 claims abstract description 30
- 238000003466 welding Methods 0.000 claims abstract description 22
- 238000000034 method Methods 0.000 claims description 9
- 238000010992 reflux Methods 0.000 claims description 9
- 239000006071 cream Substances 0.000 claims description 6
- 230000004907 flux Effects 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 235000006508 Nelumbo nucifera Nutrition 0.000 claims 1
- 240000002853 Nelumbo nucifera Species 0.000 claims 1
- 230000005611 electricity Effects 0.000 claims 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 5
- 239000012778 molding material Substances 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000012777 electrically insulating material Substances 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/564—Details not otherwise provided for, e.g. protection against moisture
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/49524—Additional leads the additional leads being a tape carrier or flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/038—Post-treatment of the bonding area
- H01L2224/03848—Thermal treatments, e.g. annealing, controlled cooling
- H01L2224/03849—Reflowing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0501—Shape
- H01L2224/05012—Shape in top view
- H01L2224/05014—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05647—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/37001—Core members of the connector
- H01L2224/37099—Material
- H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/37001—Core members of the connector
- H01L2224/37099—Material
- H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/37138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/37147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/4005—Shape
- H01L2224/4007—Shape of bonding interfaces, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40105—Connecting bonding areas at different heights
- H01L2224/40108—Connecting bonding areas at different heights the connector not being orthogonal to a side surface of the semiconductor or solid-state body, e.g. fanned-out connectors, radial layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40105—Connecting bonding areas at different heights
- H01L2224/40111—Connecting bonding areas at different heights the strap connector extending above another semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/71—Means for bonding not being attached to, or not being formed on, the surface to be connected
- H01L2224/72—Detachable connecting means consisting of mechanical auxiliary parts connecting the device, e.g. pressure contacts using springs or clips
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73221—Strap and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/808—Bonding techniques
- H01L2224/80801—Soldering or alloying
- H01L2224/80815—Reflow soldering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
- H01L2224/84009—Pre-treatment of the connector and/or the bonding area
- H01L2224/8401—Cleaning, e.g. oxide removal step, desmearing
- H01L2224/84011—Chemical cleaning, e.g. etching, flux
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
- H01L2224/848—Bonding techniques
- H01L2224/84801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
- H01L2224/848—Bonding techniques
- H01L2224/84801—Soldering or alloying
- H01L2224/84815—Reflow soldering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/71—Means for bonding not being attached to, or not being formed on, the surface to be connected
- H01L24/72—Detachable connecting means consisting of mechanical auxiliary parts connecting the device, e.g. pressure contacts using springs or clips
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Die Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
一种半导体装置包括:包括管芯焊盘与引线的引线框架、半导体芯片以及夹件。所述半导体芯片具有第一侧以及与所述第一侧相反的第二侧。所述第一侧附接至所述管芯焊盘并且所述第二侧包括第一接合盘与第二接合盘。所述夹件将所述第一接合盘电耦接至所述引线。所述夹件在所述第一接合盘的与所述第二接合盘相邻的第一边缘部分处接触所述第一接合盘并且在所述第一接合盘的中央部分与所述夹件之间限定第一腔。焊料位于所述第一腔内以将所述夹件电耦接至所述第一接合盘。所述半导体装置包括通向所述第一腔的第一开口以在回流焊接期间引导助焊剂远离所述第二接合盘。
Description
背景技术
功率半导体装置可以包括半导体芯片与引线框架。半导体芯片的接合盘可以通过夹件(clip)电耦接至引线框架的引线。通常,将夹件的一侧焊接至半导体芯片的接合盘,并且将夹件的另一侧焊接至引线。在用于附接夹件的回流焊接工艺期间,助焊剂(solderflux)可能会散布在半导体芯片上并且污染半导体芯片的其他接合盘。这种污染可能导致在后续的引线接合期间接合线无法粘至接合盘。
由于这些原因和其他原因,本发明是有必要的。
发明内容
一个实施例包括半导体装置。所述半导体装置包括:包括管芯焊盘(die paddle)和引线的引线框架、半导体芯片以及夹件。半导体芯片具有第一侧以及与第一侧相反的第二侧。所述第一侧附接至管芯焊盘,并且所述第二侧包括第一接合盘与第二接合盘。夹件将第一接合盘电耦接至引线。夹件在第一接合盘的与第二接合盘相邻的第一边缘部分处接触第一接合盘,并且在第一接合盘的中央部分与夹件之间限定第一腔。焊料位于第一腔内以将夹件电耦接至第一接合盘。半导体装置包括通向第一腔的第一开口以在回流焊接期间将助焊剂引导远离第二接合盘。
附图说明
图1示出半导体装置的一个实施例。
图2A-2D示出半导体装置的一个实施例的各种视图。
图3A和3B分别示出半导体装置的另一个实施例的俯视图和剖视图。
图4A和4B分别示出半导体装置的另一个实施例的俯视图和剖视图。
图5是示出用于制造半导体装置的方法的一个实施例的流程图。
具体实施方式
在下文的详细描述中,参考了一些附图,这些附图形成描述的一部分并且在这些附图中通过图示方式示出了可以实践本发明的具体示例。应该理解的是,在不背离本发明的范围的情况下,可以使用其他示例以及可以做出结构上的改变。因此,下文的详细描述不应理解为限制性的,并且本发明的范围由所附权利要求限定。应该理解的是,除非另有特别说明,否则本文中所描述的各种示例的特征可以部分地或全部地互相组合。
图1示出半导体装置100的一个实施例。半导体装置100包括引线框架102、半导体芯片110、接合线128、夹件130、焊料132和134以及模制材料140。引线框架102由铜或另外的合适的金属制成,并且包括管芯焊盘104和引线106。在其他示例中,引线框架102可以包括多个引线(未示出)。诸如塑料材料或另外的合适的电绝缘材料的模制材料140封装半导体芯片110、接合线128、夹件130、焊料132和134,以及引线框架102的一些部分,使得引线框架102的其他部分保持暴露以提供至半导体芯片110的电接触。
在一个示例中,半导体芯片110包括功率半导体装置,诸如功率二极管或功率晶体管。半导体芯片110的第一侧(即底部)通过焊料、粘接材料或其他合适的材料(未示出)附接至管芯焊盘104。在一个示例中,半导体芯片110通过半导体芯片110的第一侧电耦接至管芯焊盘104。半导体芯片110的与第一侧相反的第二侧(即顶部)包括第一接合盘112和第二接合盘114。在其他示例中,半导体芯片110可以包括额外的接合盘(未示出)。第一接合盘112和第二接合盘114由铜或另外的合适的金属制成。第一接合盘112通过焊料132、夹件130和焊料134电耦接至引线106。第二接合盘114通过接合线128电耦接至引线106或电耦接至另外的引线(未示出)。接合线128可以由铜、金或另外的合适的金属制成。
夹件130被配置成在回流焊接期间防止助焊剂污染接合盘114。夹件130可以由铜或另外的合适的金属制成。在一个示例中,夹件130通过冲压成型以提供夹件与第一接合盘112的中央部分118之间的第一腔129以及提供夹件与引线106的中央部分124之间的第二腔133。夹件130在与第二接合盘114相邻的第一边缘部分116处以及在与第一边缘部分116相反的第二边缘部分120处接触第一接合盘112。夹件130也在第一边缘部分122处以及在与第一边缘部分122相反的第二边缘部分126处接触引线106。第一腔129容纳焊料132,所述焊料将夹件130电耦接至第一接合盘112的中央部分118。第二腔133容纳焊料134,所述焊料将夹件130电耦接至引线106的中央部分124。在夹件130接触第一接合盘112的第一边缘部分116的情况下,防止了助焊剂在回流焊接期间散布在第二接合盘114上。更确切地说,由于夹件130的配置,助焊剂在回流焊接期间被引导远离第二接合盘114,如将参照图2A-4B更详细地描述的。
图2A-2D示出半导体装置200的一个实施例的各种视图。图2A示出俯视图,图2B示出剖视图,图2C示出第一侧视图,以及图2D示出与第一侧视图垂直的第二侧视图。半导体装置200包括引线框架102、半导体芯片110、夹件202以及焊料132和134。简洁起见,图2A-2D没有示出接合线与模制材料。引线框架102包括管芯焊盘104和引线106。半导体芯片110的第一侧(即底部)附接至管芯焊盘104。半导体芯片110的与第一侧相反的第二侧(即顶部)包括第一接合盘112和与第一接合盘112相邻的多个第二接合盘114。第一接合盘112通过焊料132、夹件202以及焊料134电耦接至引线106。
夹件202被配置成在回流焊接期间防止助焊剂污染接合盘114。如在图2B中示出的,夹件202在与第二接合盘114相邻的第一边缘部分116处以及在与第一边缘部分116相反的第二边缘部分120处接触第一接合盘112。夹件202也在第一边缘部分122处以及在与第一边缘部分122相反的第二边缘部分126处接触引线106。在这个示例中,夹件202在与半导体芯片110垂直的方向上具有在第一厚度与第二厚度之间的变化的厚度,以在夹件与第一接合盘112的中央部分118之间限定第一腔204(例如半边陷孔(halfedge sink hole)),所述第一厚度例如在接合盘112的第一边缘部分116处在208处表示,所述第二厚度例如在接合盘112的中央部分118处在210处表示。第一腔204在第一接合盘112的第一边缘部分116与第一接合盘112的第二边缘部分120之间延伸。类似地,夹件202的厚度变化以在夹件的第一部分203a与引线106的中央部分124之间以及在夹件的第二部分203b与引线106的中央部分124之间限定两个第二腔206。每一个第二腔206在引线106的第一边缘部分122与引线106的第二边缘部分126之间延伸。
第一腔204容纳焊料132,该焊料将夹件202电耦接至第一接合盘112的中央部分118。第二腔206容纳焊料134,该焊料将夹件202的第一部分203a和第二部分203b电耦接至引线106的中央部分124。如在图2C的侧视图中示出的,夹件202的第一部分203a和第二部分203b的与引线106的第一边缘部分122垂直的侧面限定开口以在回流焊接期间将多余的焊料和/或助焊剂在与引线106的第一边缘部分122平行的方向上引导出相应的第二腔206。还如在图2C中示出的,夹件202的与接合盘112的第一边缘部分116垂直的侧面接触第一接合盘112以封闭腔204。如在图2D中示出的,夹件202限定开口214以在回流焊接期间将多余的焊料和/或助焊剂在由箭头212表示的方向上(即在与第一边缘部分116垂直的方向上)引导出腔204。开口214从第一接合盘112的中央部分118延伸至第一接合盘112的第二边缘部分120。在夹件202接触第一接合盘112的第一边缘部分116的情况下,防止了助焊剂在回流焊接期间散布在第二接合盘114上。更确切地说,如由箭头212所表示的,在回流焊接期间,多余的焊料和/或助焊剂被引导通过开口214远离第二接合盘114,以防止对第二接合盘114的污染。
图3A和3B分别示出半导体装置300的另一个实施例的俯视图与剖视图。半导体装置300包括引线框架102、半导体芯片110、夹件302以及焊料132与134。简洁起见,图3A和图3B没有示出接合线与模制材料。引线框架102包括管芯焊盘104与引线106。半导体芯片110的第一侧(即底部)附接至管芯焊盘104。半导体芯片110的与第一侧相反的第二侧(即顶部)包括第一接合盘112以及与第一接合盘112相邻的多个第二接合盘114。第一接合盘112通过焊料132、夹件302以及焊料134电耦接至引线106。
夹件302被配置成在回流焊接期间防止助焊剂污染接合盘114。如在图3B中示出的,夹件302在与第二接合盘114相邻的第一边缘部分116处以及在与第一边缘部分116相反的第二边缘部分120处接触第一接合盘112。夹件302还在第一边缘部分122处以及在与第一边缘部分122相反的第二边缘部分126处接触引线106。在这个示例中,夹件302具有单一的厚度并且被成型成在夹件与第一接合盘112的中央部分118之间限定第一腔304。第一腔304在第一接合盘112的第一边缘部分116与第一接合盘112的第二边缘部分120之间延伸。类似地,夹件302被成型成在夹件的第一部分303a与引线106的中央部分124之间以及在夹件的第二部分303b与引线106的中央部分124之间限定两个第二腔306。每一个第二腔306在引线106的第一边缘部分122与引线106的第二边缘部分126之间延伸。
第一腔304容纳焊料132以将夹件302电耦接至第一接合盘112的中央部分118。第二腔306容纳焊料134以将夹件302的第一部分303a和第二部分303b电耦接至引线106的中央部分124。如在图3B中示出的,夹件302的第一部分303a和第二部分303b与引线106的第一边缘部分122垂直的侧面限定开口以在回流焊接期间将多余的焊料和/或助焊剂在与引线106的第一边缘部分122平行的方向上引导出相应的第二腔306。还如在图3B中示出的,夹件302的与接合盘112的第一边缘部分116垂直的侧面限定开口以在回流焊接期间如由箭头312所示将多余的焊料和/或助焊剂在与第一边缘部分116平行的方向上引导出腔304。在夹件302接触第一接合盘112的第一边缘部分116的情况下,防止了助焊剂在回流焊接期间散布在第二接合盘114上。更确切地说,如由箭头312所表示的,在回流焊接期间多余的焊料和/或助焊剂被引导通过腔304的每一个端部上的开口远离第二接合盘114,以防止对第二接合盘114的污染。
图4A与4B分别示出半导体装置400的另一个实施例的俯视图和剖视图。半导体装置400包括引线框架102、半导体芯片110、夹件402以及焊料132和134。简洁起见,图4A和图4B没有示出接合线和模制材料。引线框架102包括管芯焊盘104和引线106。半导体芯片110的第一侧(即底部)附接至管芯焊盘104。半导体芯片110的与第一侧相反的第二侧(即顶部)包括第一接合盘112以及与第一接合盘112相邻的多个第二接合盘114。第一接合盘112通过焊料132、夹件402以及焊料134电耦接至引线106。
夹件402被配置成在回流焊接期间防止助焊剂污染接合盘114。如在图4B中示出的,夹件402在与第二接合盘114相邻的第一边缘部分116处以及在与第一边缘部分116相反的第二边缘部分120处接触第一接合盘112。夹件402还在第一边缘部分122处以及在与第一边缘部分122相反的第二边缘部分126处接触引线106。在这个示例中,夹件402具有单一的厚度并且被成型成在夹件与第一接合盘112的中央部分118之间限定第一腔404。第一腔404在第一接合盘112的第一边缘部分116与第一接合盘112的第二边缘部分120之间延伸。类似地,夹件402被成型成在夹件的第一部分403a与引线106的中央部分124之间以及在夹件的第二部分403b与引线106的中央部分124之间限定两个第二腔406。每一个第二腔406在引线106的第一边缘部分122与引线106的第二边缘部分126之间延伸。
第一腔404容纳焊料132以将夹件402电耦接至第一接合盘112的中央部分118。第二腔406容纳焊料134以将夹件402的第一部分403a和第二部分403b电耦接至引线106的中央部分124。如在图4B中所示出的,夹件402的第一部分403a和第二部分403b的与引线106的第一边缘部分122垂直的侧面限定开口以在回流焊接期间将多余的焊料和/或助焊剂在与引线106的第一边缘部分122平行的方向上引导出相应的第二腔406。还如在图4B中所示出的,夹件402的与接合盘112的第一边缘部分116垂直的侧面限定开口以在回流焊接期间如由箭头412所示将多余的焊料和/或助焊剂在与第一边缘部分116平行的方向上引导出腔404。
夹件402还包括在与半导体芯片110和引线框架102垂直的方向上延伸穿过夹件的第一开口414和第二开口416a与416b,以在回流焊接期间分别将多余的焊料和/或助焊剂如由箭头413所示在垂直方向上引导出腔404与腔406。在夹件402接触第一接合盘112的第一边缘部分116的情况下,防止了助焊剂在回流焊接期间散布在第二接合盘114上。更确切地说,如由箭头412与箭头413所表示的,在回流焊接期间多余的焊料和/或助焊剂被引导通过腔404的每一个端部上的开口以及通过开口414远离第二接合盘114,以防止对第二接合盘114的污染。
图5是示出用于制造诸如之前所述的并且参照图2A-4B示出的半导体装置200、300或400的半导体装置的方法500的一个实施例的流程图。在502,将半导体芯片的第一侧附接至引线框架的管芯焊盘,其中半导体芯片的与第一侧相反的第二侧包括第一接合盘与第二接合盘。在504,将焊料膏施加于第一接合盘的中央部分以及施加于引线框架的引线的中央部分。在506,将夹件放置在第一接合盘和引线上,使得夹件接触第一接合盘的与第二接合盘相邻的第一边缘部分并且在第一接合盘的中央部分与夹件之间在施加焊料膏的地方限定第一腔。在508,回流焊料以将第一接合盘电耦合至引线,从而引导助焊剂远离第二接合盘。
在一个示例中,放置夹件包括:放置夹件使得夹件接触引线的第一边缘部分并且在引线的中央部分与夹件之间在施加焊料膏的地方限定第二腔。在另一个示例中,回流焊料包括:回流焊料使得助焊剂被引导通过从第一接合盘的中央部分延伸至第一接合盘的与第一接合盘的第一边缘部分相反的第二边缘部分的开口。在另一个示例中,回流焊料包括:回流焊料使得助焊剂被引导通过与第一接合盘的第一边缘部分垂直地延伸的开口。在另一个实施例中,回流焊料包括:回流焊料使得助焊剂被引导通过在第一接合盘的中央部分处并且与半导体芯片垂直地延伸穿过夹件的开口。
尽管本文已经示出并且描述了特定的示例,但在不背离本发明的范围的情况下,各种替代的和/或等同的实施方式可以替代所示出的和所描述的特定的示例。本申请旨在覆盖本文所讨论的特定示例的任意调整方案或变型方案。因此,本发明旨在仅由权利要求及其等同方案限定。
Claims (22)
1.一种半导体装置,所述半导体装置包括:
引线框架,所述引线框架包括管芯焊盘和引线;
半导体芯片,所述半导体芯片具有第一侧以及与所述第一侧相反的第二侧,所述第一侧附接至所述管芯焊盘并且所述第二侧包括第一接合盘以及第二接合盘;
夹件,所述夹件将所述第一接合盘电耦接至所述引线,所述夹件在所述第一接合盘的与所述第二接合盘相邻的第一边缘部分处接触所述第一接合盘并且在所述第一接合盘的中央部分与所述夹件之间限定第一腔;
位于所述第一腔内的焊料,所述焊料将所述夹件电耦接至所述第一接合盘;以及
通向所述第一腔的由夹件限定的第一开口,所述第一开口从所述第一接合盘的除第一边缘部分以外的边缘部分延伸,并且所述第一开口用以在回流焊接期间引导助焊剂远离所述第二接合盘。
2.根据权利要求1所述的半导体装置,其中,所述第一开口从所述第一接合盘的中央部分延伸至所述第一接合盘的与所述第一接合盘的第一边缘部分相反的第二边缘部分。
3.根据权利要求1所述的半导体装置,其中,所述第一开口由所述夹件限定以在回流焊接期间与所述第一接合盘的第一边缘部分平行地引导助焊剂。
4.根据权利要求1所述的半导体装置,其中,所述第一开口在所述第一接合盘的中央部分处并且与所述半导体芯片垂直地延伸穿过所述夹件。
5.根据权利要求1所述的半导体装置,其中,所述夹件在与所述半导体芯片垂直的方向上的厚度从所述第一接合盘的第一边缘部分至所述第一接合盘的中央部分变化以限定所述第一腔。
6.根据权利要求1所述的半导体装置,其中,所述夹件具有单一的厚度并且被成型成限定所述第一腔。
7.根据权利要求1所述的半导体装置,其中,所述夹件在所述引线的第一边缘部分处接触所述引线并且在所述引线的中央部分与所述夹件之间限定第二腔,所述半导体装置还包括:
通向所述第二腔的第二开口,以在回流焊接期间将助焊剂引导出所述第二腔。
8.根据权利要求7所述的半导体装置,其中,所述第二开口由所述夹件限定以在回流焊接期间与所述引线的第一边缘部分平行地引导助焊剂。
9.根据权利要求7所述的半导体装置,其中,所述第二开口在所述引线的中央部分处并且与所述引线框架垂直地延伸穿过所述夹件。
10.根据权利要求7所述的半导体装置,其中,所述夹件在与所述引线垂直的方向上的厚度从所述引线的第一边缘部分到所述引线的中央部分变化以限定所述第二腔。
11.根据权利要求7所述的半导体装置,其中,所述夹件具有单一的厚度并且被成型成限定所述第二腔。
12.一种半导体装置,所述半导体装置包括:
引线框架,所述引线框架包括管芯焊盘与引线;
半导体芯片,所述半导体芯片具有第一侧以及与所述第一侧相反的第二侧,所述第一侧附接至所述管芯焊盘并且所述第二侧包括第一接合盘以及第二接合盘;
夹件,所述夹件将所述第一接合盘电耦接至所述引线,所述夹件在所述第一接合盘的与所述第二接合盘相邻的第一边缘部分处接触所述第一接合盘并且在所述第一接合盘的中央部分与所述夹件之间限定第一腔,所述夹件在所述引线的第一边缘部分处接触所述引线并且在所述引线的中央部分与所述夹件之间限定第二腔;
位于所述第一腔中的第一焊料,所述第一焊料将所述夹件电耦接至所述第一接合盘;
位于所述第二腔中的第二焊料,所述第二焊料将所述夹件电耦接至所述引线;
通向所述第一腔的第一开口,以在回流焊接期间引导助焊剂远离所述第二接合盘;以及
通向所述第二腔的第二开口,以在回流焊接期间将助焊剂引导出所述第二腔。
13.根据权利要求12所述的半导体装置,其中,所述夹件接触所述第一接合盘的与所述第一接合盘的第一边缘部分相反的第二边缘部分,并且所述第一腔在所述第一接合盘的第一边缘部分与所述第一接合盘的第二边缘部分之间延伸,以及
其中,所述夹件接触所述引线的与所述引线的第一边缘部分相反的第二边缘部分,并且所述第二腔在所述引线的第一边缘部分与所述引线的第二边缘部分之间延伸。
14.根据权利要求12所述的半导体装置,其中,所述第一腔与所述第二腔通过改变所述夹件在与所述引线框架垂直的方向上的厚度来限定。
15.根据权利要求12所述的半导体装置,其中,所述夹件具有单一的厚度并且被成型成限定所述第一腔和所述第二腔。
16.一种用于制造半导体装置的方法,所述方法包括:
将半导体芯片的第一侧附接至引线框架的管芯焊盘,所述半导体芯片的与所述第一侧相反的第二侧包括第一接合盘和第二接合盘;
将焊料膏施加于所述第一接合盘的中央部分并且施加于所述引线框架的引线的中央部分;
将夹件放置在所述第一接合盘和所述引线上,使得所述夹件接触所述第一接合盘的与所述第二接合盘相邻的第一边缘部分并且在所述第一接合盘的所述中央部分与所述夹件之间在施加所述焊料膏的地方限定第一腔;以及
回流所述焊料,以将所述第一接合盘电耦接至所述引线,从而引导助焊剂远离所述第二接合盘。
17.根据权利要求16所述的方法,其中,放置所述夹件包括:放置所述夹件使得所述夹件接触所述引线的第一边缘部分并且在所述引线的中央部分与所述夹件之间在施加所述焊料膏的地方限定第二腔。
18.根据权利要求16所述的方法,其中,回流所述焊料包括:回流所述焊料使得引导助焊剂通过从所述第一接合盘的中央部分延伸至所述第一接合盘的与所述第一接合盘的第一边缘部分相反的第二边缘部分的开口。
19.根据权利要求16所述的方法,其中,回流所述焊料包括:回流所述焊料使得引导助焊剂通过与所述第一接合盘的第一边缘部分垂直地延伸的开口。
20.根据权利要求16所述的方法,其中,回流所述焊料包括:回流所述焊料使得引导助焊剂通过在所述第一接合盘的中央部分处并且与所述半导体芯片垂直地延伸穿过所述夹件的开口。
21.一种半导体装置,所述半导体装置包括:
引线框架,所述引线框架包括管芯焊盘和引线;
半导体芯片,所述半导体芯片具有第一侧以及与所述第一侧相反的第二侧,所述第一侧附接至所述管芯焊盘并且所述第二侧包括第一接合盘以及第二接合盘;
夹件,所述夹件将所述第一接合盘电耦接至所述引线,所述夹件具有上表面和沿着所述第一接合盘的与所述第二接合盘相邻的第一边缘部分接触所述第一接合盘的相反的下表面,并且所述夹件在所述下表面与所述第一接合盘的中央部分之间限定第一腔;
位于所述第一腔内的焊料,所述焊料将所述夹件电耦接至所述第一接合盘;以及
从所述上表面穿过所述夹件延伸到第一腔的上开口,所述上开口用以在回流焊接期间引导助焊剂远离所述第二接合盘。
22.一种半导体装置,所述半导体装置包括:
引线框架,所述引线框架包括管芯焊盘和引线;
半导体芯片,所述半导体芯片具有第一侧以及与所述第一侧相反的第二侧,所述第一侧附接至所述管芯焊盘并且所述第二侧包括第一接合盘以及第二接合盘;
夹件,所述夹件将所述第一接合盘电耦接至所述引线,所述夹件具有上表面和相反的下表面;所述下表面在夹件的第一端部处沿着所述第一接合盘的与所述第二接合盘相邻的第一边缘部分接触所述第一接合盘,并且所述夹件在所述下表面与第一接合盘的中央部分之间限定第一腔,且所述下表面在夹件的与第一端部相反的第二端部处沿着引线的第一边缘部分接触所述引线,所述夹件在所述下表面与所述引线的中央部分之间限定第二腔;
位于所述第一腔内的将所述夹件电耦接至所述第一接合盘的以及位于第二腔内的将所述夹件电藕接至所述引线的焊料;
从所述上表面垂直于半导体芯片穿过所述夹件延伸到第一腔的第一上开口;以及
从所述上表面穿过所述夹件延伸到第二腔的第二上开口;所述第一和第二上开口提供用以在回流焊接期间引导助焊剂远离所述第二接合盘的引导路径。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/729,672 | 2015-06-03 | ||
US14/729,672 US9640465B2 (en) | 2015-06-03 | 2015-06-03 | Semiconductor device including a clip |
Publications (2)
Publication Number | Publication Date |
---|---|
CN106252287A CN106252287A (zh) | 2016-12-21 |
CN106252287B true CN106252287B (zh) | 2019-04-09 |
Family
ID=57352377
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201610391189.0A Active CN106252287B (zh) | 2015-06-03 | 2016-06-03 | 包括夹件的半导体装置 |
Country Status (3)
Country | Link |
---|---|
US (2) | US9640465B2 (zh) |
CN (1) | CN106252287B (zh) |
DE (1) | DE102016110235B4 (zh) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9640465B2 (en) * | 2015-06-03 | 2017-05-02 | Infineon Technologies Ag | Semiconductor device including a clip |
US9911684B1 (en) * | 2016-08-18 | 2018-03-06 | Semiconductor Components Industries, Llc | Holes and dimples to control solder flow |
US10825757B2 (en) * | 2016-12-19 | 2020-11-03 | Nexperia B.V. | Semiconductor device and method with clip arrangement in IC package |
US9935041B1 (en) * | 2017-04-06 | 2018-04-03 | Texas Instruments Incorporated | Multi-chip module clips with connector bar |
CN110914981B (zh) * | 2018-05-29 | 2023-06-16 | 新电元工业株式会社 | 半导体模块 |
WO2019229829A1 (ja) * | 2018-05-29 | 2019-12-05 | 新電元工業株式会社 | 半導体モジュール |
EP3761358A1 (en) * | 2019-07-02 | 2021-01-06 | Nexperia B.V. | A lead frame assembly for a semiconductor device |
US20210074667A1 (en) * | 2019-09-05 | 2021-03-11 | Infineon Technologies Ag | Interconnect Clip with Angled Contact Surface and Raised Bridge Technical Field |
US11183451B2 (en) * | 2019-09-05 | 2021-11-23 | Infineon Technologies Ag | Interconnect clip with angled contact surface and raised bridge |
US11901309B2 (en) * | 2019-11-12 | 2024-02-13 | Semiconductor Components Industries, Llc | Semiconductor device package assemblies with direct leadframe attachment |
CN114628347B (zh) * | 2022-05-16 | 2022-07-22 | 山东中清智能科技股份有限公司 | 一种半导体封装结构及其制备方法 |
CN116705770B (zh) * | 2023-08-03 | 2023-12-01 | 深圳市锐骏半导体股份有限公司 | 半导体装置及其制造方法 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101593740A (zh) * | 2008-05-30 | 2009-12-02 | 万国半导体股份有限公司 | 用于半导体器件封装的导电夹片 |
CN102956509A (zh) * | 2011-08-31 | 2013-03-06 | 飞思卡尔半导体公司 | 功率器件和封装该功率器件的方法 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5015206A (en) | 1990-04-05 | 1991-05-14 | Die Tech, Inc. | Solder terminal |
US6657313B1 (en) | 1999-01-19 | 2003-12-02 | International Business Machines Corporation | Dielectric interposer for chip to substrate soldering |
US6521982B1 (en) | 2000-06-02 | 2003-02-18 | Amkor Technology, Inc. | Packaging high power integrated circuit devices |
JP4085768B2 (ja) * | 2002-10-08 | 2008-05-14 | トヨタ自動車株式会社 | 上部電極、パワーモジュール、および上部電極のはんだ付け方法 |
TWI221343B (en) | 2003-10-21 | 2004-09-21 | Advanced Semiconductor Eng | Wafer structure for preventing contamination of bond pads during SMT process and process for the same |
US7683464B2 (en) | 2005-09-13 | 2010-03-23 | Alpha And Omega Semiconductor Incorporated | Semiconductor package having dimpled plate interconnections |
US7622796B2 (en) | 2005-09-13 | 2009-11-24 | Alpha And Omega Semiconductor Limited | Semiconductor package having a bridged plate interconnection |
US7285849B2 (en) | 2005-11-18 | 2007-10-23 | Fairchild Semiconductor Corporation | Semiconductor die package using leadframe and clip and method of manufacturing |
US7859089B2 (en) | 2006-05-04 | 2010-12-28 | International Rectifier Corporation | Copper straps |
JP5384913B2 (ja) | 2008-11-18 | 2014-01-08 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
KR100959866B1 (ko) | 2009-07-20 | 2010-05-27 | 삼성전기주식회사 | 패키지 기판용 리드핀 |
JP2013161941A (ja) * | 2012-02-06 | 2013-08-19 | Renesas Electronics Corp | 半導体装置 |
EP2930747A1 (en) | 2014-04-07 | 2015-10-14 | Nxp B.V. | Lead for connection to a semiconductor device |
US9640465B2 (en) * | 2015-06-03 | 2017-05-02 | Infineon Technologies Ag | Semiconductor device including a clip |
-
2015
- 2015-06-03 US US14/729,672 patent/US9640465B2/en active Active
-
2016
- 2016-06-02 DE DE102016110235.0A patent/DE102016110235B4/de active Active
- 2016-06-03 CN CN201610391189.0A patent/CN106252287B/zh active Active
-
2017
- 2017-05-02 US US15/584,491 patent/US10424534B2/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101593740A (zh) * | 2008-05-30 | 2009-12-02 | 万国半导体股份有限公司 | 用于半导体器件封装的导电夹片 |
CN102956509A (zh) * | 2011-08-31 | 2013-03-06 | 飞思卡尔半导体公司 | 功率器件和封装该功率器件的方法 |
Also Published As
Publication number | Publication date |
---|---|
US20170250125A1 (en) | 2017-08-31 |
US10424534B2 (en) | 2019-09-24 |
US9640465B2 (en) | 2017-05-02 |
DE102016110235A1 (de) | 2016-12-08 |
US20160358843A1 (en) | 2016-12-08 |
DE102016110235B4 (de) | 2023-08-10 |
CN106252287A (zh) | 2016-12-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN106252287B (zh) | 包括夹件的半导体装置 | |
JP4294161B2 (ja) | スタックパッケージ及びその製造方法 | |
CN104218013B (zh) | 半导体装置以及半导体装置的制造方法 | |
CN105264659B (zh) | 半导体装置 | |
CN107210289B (zh) | 半导体器件 | |
US7547626B2 (en) | Semiconductor package and method of forming wire loop of semiconductor package | |
CN102986025B (zh) | 密封型半导体装置的制造方法 | |
CN103608917B (zh) | 超薄功率晶体管和具有定制占位面积的同步降压变换器 | |
US8952509B1 (en) | Stacked multi-chip bottom source semiconductor device and preparation method thereof | |
JP2014093431A (ja) | 半導体装置およびその製造方法 | |
TW404030B (en) | Dual-chip semiconductor package device having malposition and the manufacture method thereof | |
US20160111379A1 (en) | Semiconductor device | |
JP5819052B2 (ja) | 半導体装置および半導体装置の製造方法 | |
CN107431342A (zh) | 回路构成体 | |
JP6499642B2 (ja) | ワイヤボンディング構造の製造方法、ワイヤボンディング構造、電子装置 | |
JP5103731B2 (ja) | モールドパッケージ | |
JP5654470B2 (ja) | 電子部品用リードフレームの製造方法及び電子部品用リードフレーム | |
US8581378B2 (en) | Semiconductor device and method of manufacturing the same | |
US10553524B2 (en) | Integrated circuit (IC) die attached between an offset lead frame die-attach pad and a discrete die-attach pad | |
US20160064253A1 (en) | Method for manufacturing a semiconductor device | |
US20080197461A1 (en) | Apparatus for wire bonding and integrated circuit chip package | |
JP2016146457A (ja) | 半導体装置およびその製造方法 | |
JPWO2019082344A1 (ja) | 半導体装置の製造方法 | |
US10541194B2 (en) | Semiconductor package with interconnected leads | |
JP5104020B2 (ja) | モールドパッケージ |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |