CN103608917B - 超薄功率晶体管和具有定制占位面积的同步降压变换器 - Google Patents

超薄功率晶体管和具有定制占位面积的同步降压变换器 Download PDF

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CN103608917B
CN103608917B CN201280028281.0A CN201280028281A CN103608917B CN 103608917 B CN103608917 B CN 103608917B CN 201280028281 A CN201280028281 A CN 201280028281A CN 103608917 B CN103608917 B CN 103608917B
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thickness
chip
contact pad
terminal
band
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CN103608917A (zh
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J·A·赫尔嵩末
O·J·洛佩斯
J·A·浓趣勒
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Texas Instruments Inc
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Texas Instruments Inc
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Abstract

本发明涉及一种封装的功率晶体管器件（100），其具有引线框，所述引线框包括扁平板片（110）和被所述板片隔开的共面扁平条带（120），所述板片具有第一厚度（110a），并且所述条带具有比所述第一厚度更小的第二厚度（120a），所述板片和条带具有端子（212；121a）。一种场效应功率晶体管芯片（210），其具有第三厚度（210a），在所述芯片一侧的第一和第二接触焊盘，以及在所述芯片相反侧的第三接触焊盘（211），所述第一焊盘被连接到所述板片，所述第二焊盘被连接到所述条带，并且所述第三焊盘与所述端子共面。板片与条带之间厚度差异以及芯片与端子之间的间隔由封装化合物（130）填充，其中所述化合物具有与所述板片表面（111）共面的表面（101），以及与所述第三焊盘（211）和端子（212；212a）共面的相反表面（102），所述表面之间的距离（104）等于所述第一（110a）和第三（210a）厚度的总和。

Description

超薄功率晶体管和具有定制占位面积的同步降压变换器
技术领域
本发明主要涉及半导体器件及其工艺领域，更具体的，涉及非常薄但是具有良好热效率的电源模块的系统结构和制造方法。
背景技术
在受欢迎的功率开关器件的族系之中，其中一种是DC-DC电源电路，尤其是开关模式电源电路一类。特别适合用于涌现出的功率输送需求的是同步降压变换器，其具有串联连接并通过共同的交换节点耦合在一起的两个功率MOS场效应晶体管（FET）。在降压变换器中，控制FET芯片连接在电源电压VIN与LC输出滤波器之间，并且同步FET芯片连接在LC输出滤波器与接地电位之间。
控制FET芯片与同步FET芯片的栅极连接到包括集成电路（IC）的半导体芯片，其中集成电路作为变换器的驱动器，驱动器反过来连接到控制器IC。优选地，驱动器和控制器IC两者集成在单一芯片上，该单一芯片也连接到地电位。
对于当今的许多功率开关器件来说，功率MOSFET芯片与驱动器芯片和控制器IC被组装为单独的组件。通常每个芯片连接到金属引线框的矩形或方形焊盘；作为输出端子的焊盘被引线包围。所述引线往往形成为不具有悬臂延伸，并且设置在四方扁平无引线（QFN）或小外形无引线（SON）器件中。从芯片到引线的电气连接由键合线提供，由于键合线的长度和电阻，键合线引入明显的寄生电感到功率电路。每个组装件通常封装在塑料封装中，并且封装后的组件用作用于电源系统的板组装的分立构筑块。
在其他功率开关器件中，功率MOSFET芯片和驱动器-控制器IC水平并排组装在引线框焊盘上，其反过来又被充当器件输出端子的引线四面包围。引线以QFN或SON的方式形成。芯片与引线之间的电气连接由键合线提供。器件封装在塑料封装中。
在一些最近引进的先进组装件中，夹子替代许多连接线。这些夹子是宽的，并引入最小的寄生电感。不过，在具有垂直电流流动的功率MOSFET芯片中，夹子需要将控制FET芯片的前金属连接到同步FET芯片的引线框。这种方法占用面积，并增加模块的占位面积。
在另一个最近引入的功率MOSFET组装件中，通过为功率芯片提供组装件焊盘分为两部分的引线框而避免使用连接夹子和键合线，该功率芯片具有第一和第二端子在一个管芯侧，并且第三端子在相反管芯侧。芯片被翻转组装在引线框焊盘上（利用注射器分配的金属凸点或焊膏），以便使第一端子接触一个焊盘部分，并且第二端子接触其他焊盘部分。这两个引线框部分具有弯曲的边缘，以便在翻转组装后，该边缘变成与第三端子共面；因此，所有三个MOSFET端子可以连接到印刷电路板（PCB）。在这种连接后，引线框焊盘远离PCB，但由于它被分为服务于两个管芯端子的两个部分，散热片不能连接到焊盘。
在另一个最近引入的功率MOSFET封装中，向引线框提供分为两个部分的扁平焊盘，其可以被连接到PCB。功率芯片的第一和第二端子连接到这些焊盘部分。远离引线框焊盘的第三芯片端子接触金属夹子，该金属夹子具有朝引线框的引线弯曲的边缘，从而允许所有三个管芯端子组装在PCB上。夹子由金属制成，该金属厚到足以允许用于冷却第三芯片端子的散热片连接到夹子。因此，该MOSFET封装具有引线框-芯片-芯片的三个地层结构。
发明内容
申请人意识到非常薄，但仍提供接近理论最大值的热性能和电气效率的功率变换器在市场中的广泛应用，例如掌上电脑、笔记本电脑、汽车以及需要MOS场效应晶体管（FET）封装和变换器的医疗产品，。申请人看到包括引线框、芯片和芯片的厚度的现有MOSFET的三个地层结构，这对许多新兴的应用来说太厚了。此外，这些器件往往担负寄生的电和热电阻，因此，距离达到最大热性能和电气效率还有一定距离。作为客户友好使用的额外新兴需求，申请人意识到功率FET封装应当优选允许在印刷电路板（PCB）中直接实施，而没有首先更改占位面积的麻烦。
当申请人发现连接到引线框的FET芯片的两地层组装件导致具有第一、第二或第三端子在封装的一侧，和第一、第二或第三端子在封装的相反侧的封装，其中在相反侧面上的端子能够用于强冷却，申请人解决了降低高功率MOSFET封装的总体厚度的问题。在所述相反侧面上的专用端子通过在具有截然不同厚度的两部分的引线框焊盘上组装FET芯片实现；在封装后，较薄部分在绝缘材料涂层下被屏蔽，保留未屏蔽的较厚部分裸露并用于冷却。
在示例性优选实施例中，第一端子是FET的源极，第二端子是漏极，并且第三端子是栅极；所有三个端子在一个封装侧面上示出，并可用于连接到PCB；在所述封装的相反侧面上的专用端子是FET的源极，其连接到较厚的引线框部分。因此，在总体厚度小于0.5mm的示例性实施例中，封装具有两个地层结构，和由芯片厚度和厚引线框部分的厚度总和组成的厚度。当冷却时，例如通过连接到厚引线框部分的散热片，该FET封装可以处理高达35A的电流。
示例性两地层EFT管芯封装的构造开始于具有两个扁平部分的引线框焊盘；第一部分具有第一厚度，以及第二部分具有小于第一厚度的第二厚度。两个部分的一个表面是共面的，从而提供用于连接FET芯片的平面；相反表面呈现出由厚度差异产生的台阶。下一步，FET管芯穿过焊盘部分连接；作为例子，源极连接到第一部分，且栅极连结到第二部分；优选连接方法是焊接丝网印刷。接着，金属部件添加到焊盘部分的共平面表面，作为两个部分的端子（优选使用焊接丝网印刷）。选择连接端子的高度，以便该端子和未连接管芯表面共面；在该例子中，未连接管芯表面是FET漏极。
在下列封装工艺中，前述厚度台阶用封装化合物填充，较薄焊盘部分的表面掩藏在绝缘材料下面，且较厚焊盘部分的表面保持裸露。因此，这种裸露引线框表面可用于散热片的连接，该散热片用于直接冷却由FET的可操作电流导致的热量。
附图说明
图1示出本发明实施例的具有透明封装化合物的功率场效应晶体管（FET）封装组件的顶面透视图。
图2示出与图1实施例相同的实施例的具有透明封装化合物的功率FET封装组件的底面透视图。
图3示出另一个实施例的具有透明封装化合物的功率FET封装组件的顶面透视图。
图4示出与图3实施例相同实施例的具有透明封装化合物的功率FET封装组件的底面透视图。
图5示出从底面观看的功率FET封装组件的另一个实施例，其示出明显比可用板片和条带面积小的芯片。
图6示出图5的实施例，其具有模式化的沉积金属层以适合在PCB上的组件的常规占位面积。
图7示出从底部观看的另一个实施例。双芯片是用于同步降压变换器的构造块，其具有引线框的较厚板片作为裸露在顶侧的开关节点（未示出）。
图8到12示出用于功率FET的两地层封装组件的制造工艺流程的特定步骤。
图8示出引线框的共面表面的透视图，所述引线框共面表面具有第一厚度的扁平板片和具有比第一厚度更小的第二厚度的扁平条带。
图9示出施加于图8的引线框板片和条带的连接材料补片的透视图，连接材料例如焊膏。
图10示出连接到图9的引线框的功率FET芯片的透视图。
图11示出包括与图10的引线框对齐的端子的多片部件，其被准备用于连接到引线框的步骤。
图12示出在连接端子之后且在将组合件密封在封装材料之前，在引线框上的芯片组合件。
具体实施方式
图1和图2示出本发明的示例性实施例，旨在用于在基板例如母板上的组合件的半导体功率器件的封装。封装对于封装处理大电流（例如，20到35A）并因此生成明显热量的功率场效应晶体管（FET）、功率开关、功率变换器特别有用。被指定为100的封装从两个视角观看：一个视角，在这里被称为顶视图并如图1所示，其示出在板上组装后观看的封装。另一个视角，在这里被称为底视图并如图2所示，其示出在连接到板之前观看的封装。为了清楚起见，假设图1和2中的封装组件以透明绝缘化合物130封装；事实上，所述化合物必须是不透明的（例如，黑色基于环氧树脂的成型化合物），以便保护半导体芯片，使其免受可见波长范围的光的影响。
图1和2示出器件100具有平面顶部表面101、平面底部表面102、与顶部表面和底部表面成直角的侧表面103，以及与器件的水平尺寸相比要小的厚度104。优选的厚度范围小于0.5mm，例如在0.42mm与0.45mm之间。裸露在顶部表面101上的大金属面积111属于被指定为110的扁平引线框板片。
通过金属面积111，引线框板片110可以将大量的热量消散在周围环境中；在功率芯片210的操作期间产生热能，其中功率芯片210连接到与面积111相反的板片110的表面112。当散热片连接到金属面积111时，热消散可以大大加强。为了方便散热片的连接，提供具有可焊接冶金制备例如锡层或镍层的金属面积111是有利的。板片110优选由铜或铜合金制成；其他备选材料包括铁镍合金（例如合金42）、铝和科伐合金TM。板厚度110a优选在0.15mm与0.25mm之间，但是可以更薄或更厚。板片厚度110a在这里被称为第一厚度110a。
引线框板片110构成封装器件100第一地层。正如本文所使用的，地层指的是一个被置于另一个上面的几种材料中的一种伸出来的部分。如图1所示，板片110可以在其整个延伸部分具有统一的厚度110a；可替代地，其可以具有一个或更多变薄部分，以便增强对密封化合物的强劲锁定和粘合。当包括变薄部分时，变薄部分优选地通过相同制造步骤产生；其果是，其厚度与条带120的厚度120a相同（参照下面）。
FET芯片在图2中被强调。作为场效应晶体管，芯片210具有三个接触焊盘：第一和第二接触焊盘在一个芯片侧；这个侧面以及第一和第二接触焊盘未在图2中示出。第三接触焊盘在芯片相反侧面上，其在图2中被示为裸露在底部表面102上的大金属面积211。面积211具有允许焊连接到基板的金属区域的可焊接冶金成分，基板例如印刷电路板（PCB）。接触焊盘211在这里被称为第三接触焊盘。接触焊盘211的大面积尺寸能够让在功率芯片210操作期间产生的大量热量耗散。当连接到金属化PCB时，该板起散热片的作用。
在示例性实施例中，芯片210可以是场效应功率晶体管或由硅、砷化镓、另一种III-V化合物或II-VI化合物制成的另一种晶体管。芯片210具有厚度210a；这个厚度在这里被称为第三厚度210a。第三厚度210a范围优选在0.10mm到0.25mm之间，但是可以更厚或更薄。芯片210构成封装器件100第二地层。如图1和2所示，器件封装100是两个地层的器件；作为第一地层的板片110置于作为第二地层的芯片210顶部。由于器件封装100不使用金属夹子和键合线，所以其不包括第三地层。结果，器件厚度104基本是板片厚度110a和芯片厚度210a的总和；器件厚度104可以在0.25mm与0.50mm之间变化，且优选地，在0.25mm与0.30mm之间。
毗邻于接触焊盘211的是多个引线212。在某些实施例中，引线212由用于制造引线框的原始金属片冲压或半蚀刻形成。引线212的高度可以大约是0.10mm到0.13mm。在这些实施例中，引线212由与板片110和条带120相同的金属制成。在其他实施例中，引线212可以单独连接到扁平板片110（工艺流程参照下面）。在这些实施例中，引线212可以由与板片110和条带120相同的金属制成，或其可以由与板片110和条带120不同的金属制成。引线212是器件100的端子，并且和第三接触焊盘面积211共面。当焊盘211的尺寸和和外围以及引线212的数量和位置符合由PCB提供的标准化占位面积，例如QFN-8占位面积时，可以取得电路板快速装配、客户满意和市场渗透的优势。
除了扁平板片110以外，图1和2进一步示出在封装组件100中的板片条带120。扁平条带120和板片110被间隙140隔开；进一步地，条带120具有与板片表面112共面的表面122。横跨间隙140，芯片210连接到共面表面112和122。芯片210连接到板片110和条带120，以便所述芯片的第一接触焊盘连接到板片，以及芯片的第二接触焊盘连接到条带。在优选FET例子中，第一焊盘是晶体管的源极端，并且第二焊盘是晶体管的栅极端。结果，在优选例子中，被指定为212的两行引线（图2）是器件100的源极端，并且被指定为212a的引线是栅极端。如上所述，第三焊盘，即优选来自中的晶体管的漏极端，裸露在组装后的器件100的底部表面102上，并且具有与端子引线212共面的大接触面积211。
芯片210的焊盘到引线框板片110的连接采用在图2中指定为230的导电导热层。所述层从包括焊料、导电粘合剂、z轴导体、碳管和石墨烯材料的组中选择的材料制成。优选材料是焊膏，并且优选的连接方法包括焊接丝网印刷技术，这是由于该技术的简单性和成本效益。与板片厚度110a和芯片厚度210a相比，层230的厚度是小的。
条带120具有厚度120a；这个厚度在这里被称为第二厚度120a（参考图1）。第二厚度120比板片110的第一厚度110a更小。作为这种厚度差异的结果，条带120的表面121不与板片110的表面111共面，而是有偏移。在封装组装芯片和引线框的工艺步骤后，该厚度差异由绝缘化合物130填充。相对于板片110的未封装和裸露表面111，条带表面121隐藏在封装材料130下面（并因此在图1和2中以虚线轮廓示出）。绝缘化合物130的优选材料是在传递模塑技术中使用的基于环氧树脂的成型化合物，该聚合化合物优选地对引线框金属例如铜或氧化铜具有很强的粘性。
如图1和2所示，封装化合物130还填充引线框板片与条带之间的间隙140，以及芯片210与端子212之间的任何空间。封装化合物130具有与板片表面111共面的表面（参照图1），从而构成器件顶部表面101，以及与第三焊盘表面211和端子212共面的相反表面（参照图2），从而构成器件的底部表面102。如上所述，表面101与表面102之间的距离104等于板片的第一厚度110a和芯片的第三厚度210a（以及连接层230的厚度）的总和。
图3和图4描述了通常指定为300的另一个示例性实施例，图3示出为从顶面观看并且图4示出为从底面观看。再一次，为了清楚起见，假设在图3和4中的封装用透明绝缘化合物330封装。器件300具有小于0.5mm的优选厚度范围，例如在0.42mm与0.45mm之间。裸露在顶部表面301上的大金属面积311属于指定为310的扁平引线框板片。面积311适合将大量的热量消散在周围环境中，尤其是当散热片连接到金属面积311的时候。扁平板片310具有厚度310a（被称为第一厚度），其优选在0.15与0.25mm之间。板片310构成封装器件300的第一地层。
类似于图1中的器件100，实施例300具有扁平条带320，间隙340将其与板片310隔开（参照图4），并且具有与板片表面312共面的表面322。条带320具有比板片310的第一厚度310a更小的厚度320a（被称为第二厚度）。此外，实施例300具有另一个扁平条带350，间隙360将其与板片310隔开，并且具有与板片表面312共面的表面352。条带350具有比第一厚度320a更小的厚度350a。厚度350a优选地与条带320的第二厚度320a相同（参照图3）。如上所述，第二厚度320a比板片310的第一厚度310a更小。作为310a与320a（以及350a）之间厚度差异的结果，条带320的表面321和条带350的表面351不与板片310的表面311共面，而是有偏移。在封装组装芯片和引线框的工艺步骤后，该厚度差异由绝缘化合物330填充。相对于板片310的未封装且裸露表面311，条带表面321和351隐藏在封装材料330下面（并且因此在图3和4中以虚线轮廓示出）。
在这个实施例中，场效应晶体管的FET芯片410在图4中被强调。第一和第二接触焊盘在图4中未示出的芯片侧；第三接触焊盘是大金属面积411，其裸露在器件300的底部表面302上。面积411具有允许焊连接到PCB的金属区域的可焊接冶金成分。芯片410具有厚度410a，在这里被称为第三厚度。第三厚度410a范围优选在0.10mm与0.25mm之间，但是可以更厚或更薄。芯片410构成封装器件300的第二地层，这反映出器件300是具有两个地层的器件。其结果是，器件厚度304是板片厚度310a和芯片厚度410a（以及连接层430的小厚度）的总和；器件厚度304可以在0.25mm与0.50mm之间变化，以及优选地，在0.25与0.30mm之间。
在图4中，板片310的对齐引线指定为412；条带320的引线指定为412a；以及条带350的对齐引线指定为413。在某些实施例中，该引线由用于制造引线框的原始金属片冲压或半蚀刻形成。引线的高度可以大约是0.10mm到0.13mm。在这些实施例中，引线由与板片310和条带320以及条带350相同的金属制成。在其他实施例中，引线可以分别连接到板片和条带（工艺流程参照下面）。在这些实施例中，引线可以由与板片和条带相同的金属制成，或引线可以由与板片和条带不同的金属制成。引线412、412a以及413与第三接触焊盘面积411共面。
利用导电和导热层430，芯片410连接到板片310和条带320。在该连接中，芯片的第一接触焊盘连接到板片，并且芯片的第二接触焊盘连接到条带。在优选FET例子中，第一焊盘是晶体管的源极端，并且第二焊盘是晶体管的栅极端。结果，在优选例子中，指定为412的一行引线（图4）是器件100的源极端，并且指定为412a的引线是栅极端。如上所述，优选例子中的第三焊盘，即优选例子中晶体管的漏极端，裸露在组装的器件100的底部表面302上，并且具有与端子引线412共面的大接触面积411。在图4中，引线413保持为孤立的。
金属面积311可以将大量的热量消散在周围环境中；在功率芯片410的操作期间产生热能，其中功率芯片410具有连接到板片310的源极。当散热片连接到金属面积311时，热消散可以大大加强。为了方便散热片的连接，提供具有可焊接冶金制备，例如锡层或镍层的金属面积311是有利的。
虽然引线413在组装芯片封装在封装化合物后仍然保持孤立，但是他们可以用于将具有各种不同芯片尺寸和配置的封装功率晶体管调整到标准化的占位面积，其如图5、6和7的示例性实施例所示。在图5中指定为500的器件采用比可用引线框提供的轮廓尺寸明显小的芯片510。芯片510具有接触焊盘面积511。并非花费时间和精力去开发用于将芯片510组装在引线框上的适合的小尺寸新引线框，图5示出在现成可用的引线框上组装芯片510的方法，其中现成可用的引线框与在图3和4中描述的是相同的。类似于图2和4，底部器件表面502通过封装的工艺步骤产生；封装材料530、裸露芯片接触焊盘511以及引线512、512a和513是共面的。
在下一个工艺步骤中，具有厚度大约在10μm与20μm之间的金属层沉积在表面502上。优选沉积方法包括用铜籽晶层敷涂表面，其后使用镍和锡或仅使用锡电镀大约为10μm到20μm厚度的层。。备选沉积方法包括喷镀法。沉积的金属层不仅提供跨越绝缘化合物530表面部分的导电性，而且提供对裸露芯片焊盘511（例如，漏极端）的保护，使其免受直接机械接触应力（例如在测试期间或在多头探针测试期间的波戈管脚）和热机械应力的影响。
在下一个工艺步骤中，如图6所示，指定为601的金属层通过例如蚀刻成型，以便模仿标准的QFN占位面积。通过成型步骤，金属层601将芯片接触焊盘511导电连接到覆盖引线513的引线613。由于在上述例子中，小面积芯片的裸露焊盘511是FET漏极端，引线613现在成为具有标准占位面积的器件漏极端-对于不需要为了适应定制的占位面积来重新布局其组装板的用户来说是一个优势。
使用沉积金属层的优点的另一个实施例在图7中以器件的透视底视图示出。一般指定为700的实施例示出薄封装的同步降压变换器的构筑块。为了清楚起见，封装材料760在图7中示出为透明的。第一FET芯片710和第二FET芯片720组装在引线框板730上。板片730的厚度指定为730a；其被称为第一厚度。板片730具有由封装化合物覆盖的表面733。器件700进一步包括两个引线框条带740和750，其被定位平行于板片侧面并与板片730隔开。条带740具有与板片表面733共面的表面743，并且条带750像表面753一样与板片表面733共面。表面743和表面753两者均被封装化合物覆盖。条带740和750优选具有比第一厚度730a更小的相同第二厚度740a。
第一FET芯片710和第二FET芯片720组装在共面表面733、743和753上，以便板片起同步降压变换器的开关节点的作用。结果，在优选的组装芯片710中，芯片710具有连接到板片730的源极和连接到条带740的栅极；芯片720具有连接到板片730的漏极和连接到条带750的栅极。可替代地，芯片的位置可以颠倒。
作为优选组装的结果，图7示出从封装化合物裸露的芯片710的漏极711，而芯片710的栅极接触引线712；进一步地，芯片720的源极721从封装化合物裸露，并且芯片720的栅极接触引线722。图7中未示出的是器件700的顶面，其具有连接到引线框板片的变换器的开关节点，开关节点起降压变换器700的有效散热器的作用。
本发明的另一个实施例是制造低成本引线框的方法，其适合将功率FET器件组装进不用键合线和夹子的两个地层器件，并且将该组装件封装为功率场效应晶体管封装，该封装小于0.5mm厚，并在连接散热片到引线框的暴露部分之后能处理20A-25A电流。。用批量生产的方式执行该方法是经济有效的。图8到12示出制造工艺流程的特定步骤。
该方法由提供大约为0.15mm与0.25mm厚的扁平金属片开始；该金属片可以更薄或更厚。优选的金属包括铜、铝和铁镍合金。接着，引线框由如图8所述的金属片形成。引线框包括扁平板片810和被间隙840将其与板片隔开的共面扁平条带820。在冲压或蚀刻步骤（所谓的半蚀刻），板片810具有第一厚度810a，并且条带820具有比第一厚度810a更小的第二厚度820a。如图8所示，在半蚀刻工艺后，条带820的表面821保持与板片810的表面811共面，而条带820的表面822相对于板片820的表面812凹进。凹进量由虚线828指示。
该方法通过提供具有第三厚度的场效应功率晶体管芯片继续。优选地，芯片厚度在大约0.10mm与0.20mm之间，但是可以更厚或更薄。FET芯片具有在芯片一侧的第一和第二接触焊盘，以及在芯片相反侧的第三接触焊盘。下一步，选择材料，其使得FET焊盘能够连接到引线框；优选地，材料从包括焊料、导电粘合剂、z轴导体、碳管和石墨烯材料的组中选择。优选的材料是焊膏。在图9中示出的工艺步骤中，施加相同连接材料的层给引线框板片（补片930和931）和引线框条带两者（补片930a和932）。当连接材料是焊膏时，优选的施加方法是低成本的丝网印刷技术。
接着，在图10中指定为1010的FET芯片连接到引线框，以便第一焊盘连接到在板片810上的焊料层930，并且第二焊盘连接到在条带820上的焊料层930a。芯片1010从而桥接板片与条带之间的间隙840。当第一FET接触焊盘是源极焊盘并且第二FET接触焊盘是栅极焊盘时，板片810成为FET源极的触点，并且条带820成为FET栅极的触点。FET的漏极焊盘是区域1011，漏极焊盘在与源极和栅极相反的芯片侧。
在图11中示出的下一个工艺步骤中，提供片部件1110，其用于在焊接补片931和932上的连接。形成该片部件以便其提供多个引线（端子）1112和1112a，其中多个引线用于连接到在扁平引线框板片和条带的共面表面上的焊接补片：端子1112用于连接到焊接补片931上，并且端子1112a用于连接到焊接补片932上。将端子作为附加片部件添加到扁平引线框端子，而不是将他们与板片一起形成的优点是在短时间内定制端子数量、尺寸和位置以便满足客户愿望而无需明显增加成本和制造时间的机会。附加优点是使用与引线框相同的金属（例如，铜）制造端子1110，或使用不同金属（例如，镍）制造端子的自由。进一步的优点是，选择性地用薄金属层电镀端子1112和1112a的表面，以便加强可焊接性的选项；金属的示例包括银层，或包括镍层、钯层和金层的叠加层。端子的高度由芯片1010的厚度确定，以便在连接后，端子表面与芯片表面1011共面（芯片的第三接触焊盘）。端子1112之间的连接金属1111通过封装工艺的最终单片化步骤中的修整技术（例如锯（sawing））清除。
如图9所示，施加相同的连接材料（例如，焊料）到引线框板片和条带。在片部件1110已经对齐并接触到焊接补片931和932后，最终连接步骤对于芯片和片部件来说是共同的。例如，当连接材料是焊膏时，对于补片930、930a、931和932的焊接，回流焊的温度漂移是共同的。芯片的第一焊盘（源极）和第二焊盘（栅极）与端子1112和1112a的连接点同时连接。结果在图12中示出。其结果是，第三芯片焊盘（漏极）1011的表面和端子1112以及1112a的表面是共面的，因此上述表面适合连接到外部的板。
在下一个工艺步骤中，图12的组装器件在封装化合物中封装，以便形成如图2所示的互相密合着的器件。优选的封装方法是使用电绝缘的基于环氧树脂的热固性成型化合物的传递模塑成型技术。封装工艺将FET芯片、引线框和端子集成在封装中，该封装的厚度等于板片（第一）厚度和芯片（第三）厚度的总和。最后，沿图12的虚线1200方向的修正和单片化步骤产生如图2所示的器件轮廓。应当强调的是，封装工艺填充引线框板片110与引线框条带120之间的厚度差异（参照图2和图1），以及芯片210与端子212和212a之间的任何间隔。其结果是，在从器件顶部表面观看时，封装化合物覆盖引线框条带。此外，在器件（图2中的102）底面上的封装化合物表面与第三芯片焊盘（漏极；图2中的211；图12中的1011）以及端子（图2中的212和212a；图12中的112和112a）共面。封装化合物的相反表面（图1中的101）与板片表面111共面。
本发明不仅应用于场效应晶体管，而且应用于其他合适的功率晶体管。而且，封装器件可以包括一个，两个或更多半导体芯片。其还可以包括多于一个散热片。此外，功率FET芯片可以经配置具有在器件一侧的栅极端和在相反侧的源极端（连接到引线框板片），或其可以经配置在器件一侧具有源极和栅极端，以及在相反侧具有漏极端（连接到引线框板片）。
本领域的技术人员应当明白，在本发明权利要求的范围内，可以对上述实施例做出附加的更改，并且许多其他的实施例也是可能的。

Claims (15)

1.一种功率晶体管封装组件，其包括：
引线框，其包括扁平板片和与所述扁平板片隔开的共面扁平条带，所述扁平板片具有第一厚度，并且所述条带具有比所述第一厚度小的第二厚度，所述扁平板片和条带具有端子；
具有第三厚度的场效应功率晶体管芯片，第一接触焊盘和第二接触焊盘在所述芯片的一侧，并且第三接触接触焊盘在相反芯片侧，所述第一接触焊盘连接到所述扁平板片，所述第二接触焊盘连接到所述条带，并且所述第三接触焊盘与所述端子共面；以及
封装化合物，其填充扁平板片与条带之间厚度差异以及芯片与端子之间的间隔，其中所述封装化合物具有与所述扁平板片共面的表面，以及与所述第三接触焊盘和所述端子共面的相反表面，所述封装化合物的所述表面之间的距离等于所述第一厚度和第三厚度的总和。
2.根据权利要求1所述的封装组件，其进一步包括连接到所述引线框的扁平板片的散热片。
3.根据权利要求1所述的封装组件，其中所述第一接触焊盘与所述引线框的扁平板片的连接以及所述第二接触焊盘与所述引线框的条带的连接包括材料层，所述材料层的材料从包括焊料、导电粘合剂、z轴导体、碳管和石墨烯材料的组中选择。
4.根据权利要求3所述的封装组件，其中通过从包括焊料、导电粘合剂、z轴导体、碳管和石墨烯材料的组中选择的材料层，所述端子连接到所述扁平板片和条带。
5.根据权利要求1所述的封装组件，其中所述引线框和所述端子由相同的金属制成。
6.根据权利要求1所述的封装组件，其中所述引线框和所述端子由不同的金属制成。
7.根据权利要求1所述的封装组件，其进一步包括成型为覆盖所述第三接触焊盘和所述端子的沉积金属层。
8.根据权利要求7所述的封装组件，其中所述沉积金属层的金属从包括锡，铜，铜、镍和锡的连续层，铜、镍和金的连续层以及难熔金属和铝的连续层的组中选择。
9.根据权利要求8所述的封装组件，其中所述沉积金属层以定制的图样模式成型。
10.根据权利要求1所述的封装组件，其中所述封装组件不用金属夹子和线。
11.一种用于制造功率场效应晶体管封装组件的方法，其包括步骤：
提供引线框，所述引线框包括扁平板片和与所述扁平板片隔开的共面扁平条带，所述扁平板片具有第一厚度，并且所述条带具有比所述第一厚度小的第二厚度；
提供场效应功率晶体管芯片，所述场效应功率晶体管芯片具有第三厚度，在芯片一侧上的第一接触焊盘和第二接触焊盘，以及在相反芯片侧上的第三接触焊盘；
将所述第一接触焊盘连接到所述扁平板片，以及将所述第二接触焊盘连接到所述条带；
将端子同时连接到所述扁平板片和条带，以便所述端子与所述第三接触焊盘共面；以及
用封装化合物填充扁平板片与条带之间的厚度差异以及芯片与端子之间的间隔，其中所述封装化合物具有与所述扁平板片共面的表面和与所述第三接触焊盘和端子共面的相反表面，由此所述芯片、引线框和端子集成到封装组件中，所述封装组件具有等于所述第一厚度和第三厚度总和的厚度。
12.根据权利要求11所述的方法，其中将所述第一接触焊盘与所述引线框的扁平板片以及将所述第二接触焊盘与所述引线框的条带连接的步骤包括从包括焊料、导电粘合剂、z轴导体、碳管和石墨烯材料的组中选择的材料层。
13.根据权利要求12所述的方法，其中将所述端子与所述引线框的扁平板片和所述引线框的条带连接的步骤包括从包括焊料、导电粘合剂、z轴导体、碳管和石墨烯材料的组中选择的材料层。
14.根据权利要求13所述的方法，其中沉积用于覆盖所述第三接触焊盘和所述端子的金属层的方法包括丝网印刷技术。
15.根据权利要求11所述的方法，其进一步包括在所述封装组件表面上沉积金属层和成型用于覆盖所述第三接触焊盘和所述端子的层的步骤，其中所述封装组件表面具有所述第三接触焊盘和所述端子。
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