CN105283956B - 具有竖直堆叠的半导体芯片的集成化多路输出电源转换器 - Google Patents

具有竖直堆叠的半导体芯片的集成化多路输出电源转换器 Download PDF

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CN105283956B
CN105283956B CN201480033379.4A CN201480033379A CN105283956B CN 105283956 B CN105283956 B CN 105283956B CN 201480033379 A CN201480033379 A CN 201480033379A CN 105283956 B CN105283956 B CN 105283956B
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terminal
chip
transistor
wire clamp
common
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CN105283956A (zh
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M·丹尼森
B·A·卡彭特
O·J·洛佩斯
J·A·赫尔布斯摩
J·诺克尔
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Texas Instruments Inc
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Texas Instruments Inc
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Dc-Dc Converters (AREA)
  • Wire Bonding (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

本发明涉及一种封装的多路输出转换器(200)，其包括：具有作为接地终端的芯片焊盘(201)和包括电输入终端(203)的多条引线(202)的引线框架；复合第一FET芯片(同步芯片，220)，其源极终端附连到引线框架，并且在其相对的表面上第一漏极终端(221)临近第二漏极终端(222)被设置，该漏极终端分别通过第一(241)和第二(242)金属线夹连接到第一(204)和第二(205)输出引线；第二FET芯片(控制芯片，211)，其竖直地设置在第一漏极终端上并且其源极终端附连到第一线夹上；第三FET芯片(控制芯片，212)，其竖直地设置在第二漏极终端上并且其源极终端附连到第二线夹上；并且第二和第三芯片的漏极终端(213,214)附连到第三金属线夹(260)上，该第三金属线夹(260)连接到输入引线(203)。

Description

具有竖直堆叠的半导体芯片的集成化多路输出电源转换器
技术领域
本发明通常涉及半导体设备和工艺，并且更具体地，涉及具有竖直堆叠的半导体芯片，特别是具有不同的向下终端类型的半导体芯片的多相半桥和多路输出电源开关的结构和制作方法。
背景技术
在电源电路的普及家族中，电源开关设备(Power Switching Device)用于将一种DC电压转换成另一种DC电压。电源模块(Power Block)特别适于新兴的电源输送要求，该电源模块具有串联连接并且通过共同的开关节点耦合在一起的双功率MOS场效应晶体管(FET)；这种组装件(assembly)也称为半桥。当添加调节驱动器和控制器时，该组装件也被称为功率级，或更普遍地，被称为同步降压转换器。在同步降压转换器中，控制FET芯片(也被称为高侧开关)被连接在电源电压VIN和LC输出滤波器之间，而同步FET芯片(也被称为低侧开关)被连接在LC输出滤波器和地电位之间。控制FET芯片和同步FET芯片的栅极被连接到包括用于转换器的驱动器和控制器的电路的半导体芯片；该芯片也被连接到地电位。
对于很多目前的电源开关设备，功率MOSFET的芯片以及驱动器和控制器IC的芯片被水平地并排组装为独立组件。每一个芯片通常被附连到金属引线框架的长方形或正方形焊盘上；该焊盘由作为输出终端的引线围绕。在其他电源开关设备中，功率MOSFET芯片以及驱动器和控制器IC被水平地并排组装在单个引线框架焊盘上，该焊盘进而在所有四侧上由用作设备输出终端的引线围绕。引线通常被成形而不具有悬臂延伸(cantileverextension)，并且以四方扁平无引线(QFN)封装或小轮廓无引线(Small Outline No-Lead,SON)设备的方式被布置。从芯片到引线的电气连接可以由键合线来提供，由于键合线的长度和电阻，其引入显著的寄生电感到电力电路中。在某些最近引进的先进组装件中，线夹(clip)取代很多连接线。这些线夹是宽的并且引入最小的寄生电感。每一个组装件通常被封装在塑料封装中，并且被封装的组件通常作为电源系统的板组装件的分立式构造模块(discrete building block)来使用。
在其他最近引进的方案中，控制FET芯片和同步FET芯片被作为堆叠竖直地组装在彼此的顶部上，其中这两种芯片中在物理上具有较大面积的芯片被附连到引线框架焊盘，并且其中线夹提供到开关节点和堆叠顶部的连接。由于考虑到占空比(duty cycle)和传导损耗，不管物理尺寸如何，同步FET芯片需要比控制FET芯片的有效面积更大的有效面积。当同步芯片和控制芯片被组装为源极向下时，较大的(物理尺寸和有效面积)同步芯片被组装到引线框架焊盘上并且较小的(物理尺寸和有效面积)控制芯片的源极被关联到同步芯片的漏极，从而形成开关切点，并且其漏极被关联到输入电源VIN；线夹被连接到两个芯片之间的开关节点。焊盘处于地电位并且用作操作上产生的热的扩散器；堆叠顶部的细长线夹被关联到输入电源VIN。
在图1中描绘在最后的段落中描述的典型的转换器，其通常被标记为100。控制MOS场效应晶体管(FET)110被堆叠在同步MOSFET120之上。该示例模块的控制FET芯片110相对于同步FET芯片120具有更小的面积。QFN金属引线框架具有被指定成为封装件(package)的散热器的长方形扁平焊盘101；引线102a和102b沿着焊盘的两个相对侧成直线设置；其他的焊盘侧可以被保持没有引线。FET芯片的堆叠通过被称为源极向下的配置来完成：通过焊料层121将同步FET120的源极焊接到引线框架焊盘101。由焊料层121焊接到同步FET120的漏极上的第一线夹140通过焊料层111附连控制FET110的源极；第一线因此用作转换器的开关节点终端。第二线夹160通过焊料层112被连接到控制FET110的漏极。第二线夹160被附连到引线框架的引线102b，并且因此被连接到输入电源VIN。这种转换器可以在500kHz到1MHz的频率上有效地操作。
发明内容
对于很多应用(特别是自动和手持式产品)来说，使用电源开关将是有利的，所述电源开关具有仅一个电源输入而同时提供多路电源输出。这样的多路输出转换器(也被称为多相半桥)可以被扩展为同时工作的多路电源输入和多路电源输出。
在目前的技术中，对于每个电压通道用于两路输电压的多相桥需要：一个封装的同步FET、一个封装的控制FET和一个封装的驱动器/控制器，因而，对于双通道来说，总数六个封装的元件连同它们的相应的电路板(PCB)的消耗需要真实的基板(estate)面积。在分析中，申请人发现，如果多路输出电源开关将仅消耗最小的板面积，结合低电阻抗，则它们可以通过许多应用找到广泛的市场。
当发现一种通过将同步FET合并到一个硅芯片上以集成第一和第二竖直堆叠(每个均包括在同步n沟道FET的顶部上的控制n沟道FET)使得它们在一个芯片表面上仅具有一个源极终端并且在相对的芯片表面上具有两个或更多相邻的漏极终端的方法时，本发明提供从一个输入电压VIN中产生两个或更多输出电压VSM同时仅消耗最小的PCB面积的单个设备。
在公开的方法中，每个输出电压VSW需要一个FET的堆叠，例如，两个VSW需要两个堆叠。堆叠被完成使得两个堆叠共用电输入并且两个堆叠共用电接地。在被制造成源极在底部上的芯片的示例实施例的每个堆叠中，控制芯片在相应的VSW线夹上被取向为源极向下，并且共用的同步芯片在共同的引线框架上被取向为源极向下。对于由通过相应的驱动器/控制器芯片调节的占空比确定的每个输出电压，存在独立的Vsw线夹。共用的同步芯片具有附连到共同引线框架上的共同源极，和附连到独立的VSW线夹的两个独立的漏极。如上所述，从共同的输入电压中导出的两个不同的输出电压的真实值由通过两个驱动器/控制器芯片调节的占空比来确定。
在具有漏极被制造在底部上的控制芯片和源极被制造在底部上的同步芯片的另一示例实施例中，控件必须被倒装以便将其组装在堆叠中。在倒装之后，控制源极可以面向安置在同步芯片的漏极上的线夹；额外的线夹部分必须用来接触倒装的芯片的栅极终端。
由于集成，具有多路输出电源开关的设备完全避免了PCB迹线的寄生阻抗。另外，堆叠的功率FET提供接近于理论最大值的热和电效率。该设备允许直接实施到PCB，而不需要首先修改器件封装(footprint)的令人麻烦的事情。
附图说明
图1显示根据现有技术组装的同步降压转换器的横截面图，其中大面积同步FET芯片被附连到引线框架焊盘并且小面积控制FET芯片在其顶部；后者通过细长的线夹被连接到引线。
图2根据本发明示出具有竖直堆叠的半导体芯片的集成多路输出电源转换器的透视图。
图3显示利用以源极向下配置制造的FET的图2的转换器的电路图；虚线轮廓指示集成同步芯片。
图4显示利用以漏极向下配置制造的FET的多路-输出电源转换器的模拟电路图；虚线轮廓指示集成控制芯片。
图5显示利用以漏极向下配置制造的FET作为控制芯片和以源极向下配置制作的FET作为同步芯片的多路输出电源转换器的电路图；虚线轮廓指示集成芯片。
图6至图10B描述组装和封装利用以漏极向下配置制造的FET作为集成控制芯片和以源极向下配置制造的FET作为集成同步芯片的多路输出电源转换器的工序。
具体实施例
可以从诸如转换和调节的电子功能中发现从单个输入产生两个或更多输出的单个电子设备的实施例，并且被用来实现这些功能的有源电子组件可以被多样化为MOS场效应晶体管(MOSFET)，基于GaN、GaAs和其他III-V和II-IV材料、SiC的晶体管，以及双极型晶体管。然而，为了说明和清楚的原因，下列优选实施例集中于多路输出电源转换器的示例。
图2图示被总体标记为200的多路输出电源转换器的实施例，其被示为带有透明的封装290。优选的实际封装利用传递模塑技术的黑色着色的环氧树脂配方。图2的示例转换器具有7mm的长度292和5mm的宽度293以及1.0mm的厚度191。转换器200被构造在基底上，该基底可以是金属引线框架或使用带条(tape)的层压板(laminate)。在所有情况下，基底具有用于组装(优选地，通过焊接)芯片或芯片的堆叠的焊盘和诸如金属引线和金属接触焊盘的多个终端。
通过透明封装可以看到的是适合于四方扁平无引线封装(QFN)和小轮廓无引线封装(SON)类型模块的金属引线框架。该引线框架包括长方形焊盘201和多条引线202。这些引线在如图2中所示的示例设备中可以在焊盘的所有四侧上大约均匀地分布，或它们可以被分布使得引线框架的一个或多个侧可以没有引线。焊盘201可以作为转换器的接地终端来操作，并且至少一个引线203是电输入终端VN。引线框架优选地由铜或铜合金制成，可替换的金属选择包括铝、铁镍合金、和柯伐合金TM(KovarTM)。引线框架的两个表面可以被制备从而便于焊料附连，例如，通过一系列镍、钯和金的电镀层。另外，至少一个表面可以具有被沉积的金属层从而增强热传导性，例如，通过银的电镀层。图2所示的示例实施例的引线框架金属的优选厚度是0.2mm；其他实施例可以使用更薄或更厚的引线框架金属。从低成本和批量加工的立场来看，优选的是，以金属薄片开始并且通过冲压或蚀刻将引线框架制造为条带，并且在封装过程之后通过修剪条带使用于模块的引线框架单立化(singulate)。
图2显示粘连到焊盘201的第一芯片220。对于图2所示的实施例，芯片220具有大约3.5x 2.85mm的尺寸和0.1mm的厚度。对于其他实施例，芯片尺寸和芯片厚度可以具有显著更小或更大的值。芯片220具有第一和第二场效应晶体管，该第一和第二场效应晶体管被合并使得一个芯片表面(图1中没有显示)具有该晶体管的共同的源极终端。具有合并或集成的晶体管终端的芯片在本文中被称为复合芯片。具有共同的终端的芯片表面被粘连到焊盘201。粘连的优选方法是通过使用诸如电镀或丝网印刷的晶圆级焊料涂覆方法(application method)来焊接。焊料材料(例如，焊膏)被选择使得相同的材料可以用于多路输出电源转换器的所有的焊接点，从而允许用于组装转换器的单个焊料回流步骤。焊料层的优选的厚度是至少25μm。
在相对的芯片表面上(远离焊盘201)，芯片220具有第一漏极终端221，其属于合并的晶体管中的第一晶体管，和第二漏极终端222，其属于合并的晶体管中的第二晶体管。漏极终端221和222被彼此临近地设置，而在它们之间没有切割线(scribe line)。在本文中将包括芯片220的源极终端和第一漏极终端221的第一场效应晶体管称为Q1；在本文中将包括芯片220的源极终端和第二漏极终端222的第二场效应晶体管称为Q2。第一漏极终端221通过第一金属线夹241连接到第一输出引线204。第二漏极终端222通过第二金属线夹242连接到第二输出引线205上。用于线夹241和242的优选金属是铜，因为其良好的导电性和导热性，适于功率晶体管。因此，第一芯片220可操作作为电源转换器200的同步FET芯片。
术语线夹和一组线夹指代功率晶体管模块的预制成的传导互连件，在从含有功率晶体管的其他单元的半导体晶元中单立化功率晶体管之后，其被附连到功率晶体管。线夹可以被提供作为零部件(piece part)，一组线夹可以被提供作为通过导轨(rail)保持在一起的网络单元，其将在单立化时被修剪。
如图2图示，第二芯片211和第三芯片212被竖直地设置在第一芯片220上。具体地，第二芯片211竖直地设置在第一漏极终端221上并且第三芯片212竖直地设置在第二漏极终端222上。这些竖直芯片位置通常被称为芯片的堆叠。对于图2所示的实施例，芯片211和212每个均具有大约2.5x 1.8mm的尺寸和0.1mm的厚度。对于其他实施例，管芯尺寸和管芯厚度可以具有显著更小或更大的值。芯片211具有FET(在本文中被称为第三晶体管Q3)，其源极终端(图2中没有显示)被附连到第一线夹214，使线夹214成为第一开关节点VSW1，并且芯片212FET(在本文中被称为第四晶体管Q4)，其源极终端(图2中没有显示)被附连到第二线夹242，使线夹242成为第二开关节点VSW2。附连的优选方法是通过焊接；焊料层的优选厚度是大约25μm。如图2显示，第一线夹241和第二线夹242具有用来作为在同步芯片220的相应的漏极和作为控制芯片的芯片211和212的相应的源极之间的相应的开关节点的结构。线夹也操作作为开关节点到多条引线204和205的低阻抗接触件，其中该多条引线204和205能够将负载电流传导到输出电感器。线夹241和242优选地由厚度范围从大约0.2至0.3mm的铜制成；线夹的两个表面优选地都是可焊接的。第一线夹241和第二线夹242优选地采用条带的形式，并且被蚀刻以获得其轮廓和厚度。
在本文中将包括第二芯片211的源极终端以及漏极终端213的场效应晶体管称为Q3；在本文中将包括第三芯片212的源极终端以及漏极终端214的场效应晶体管称为Q4。第二芯片211的漏极终端213和第三芯片212的漏极终端214被附连到共同的金属线夹260上，其被称为第三线夹。附连的优选方法是通过大约25μm厚度的焊料层来焊接。如图2显示，共同的线夹260具有用作控制FET的漏极终端到能够引导输入电流的输入电源的低阻抗接触件的结构。共同的线夹260优选地由厚度范围从大约0.2至0.3mm的铜制成，更优选地其厚度大约为2.5mm。共同的线夹260的底表面是可焊接的。共同的线夹260优选地采用条带形式，并且被蚀刻以获得其轮廓和厚度。
如图2显示，共同的线夹260被连接到作为输入终端的输入引线203。因此，第二芯片211和第三芯片212可操作作为转换器的相应的控制芯片。对于图2显示的实施例，芯片220具有大约3.5x 2.85mm的尺寸和0.1mm的厚度。对于其他实施例，芯片尺寸和芯片厚度可以具有显著更小或更大的值。
图2将第一芯片220描述为包括第一栅极终端230和临近第一漏极终端221的第一栅极返回终端(gate return terminal)231，并且进一步包括第二栅极终端232和临近第二漏极终端222的第二栅极返回233。同步FET芯片220的终端在冶金学上适合于线键合。另外，第二芯片211包括临近漏极终端213的栅极终端215，并且第三芯片212包括临近漏极终端214的栅极终端216。控制FET芯片221和222的终端在冶金学上适合于线键合。
集成到与芯片堆叠结合的一个芯片内的组件可以被扩展至每个芯片内的任意数量的组件和任意数量的竖直堆叠的组件。因此，该设备应用包括多路输出电源转换器、调节器、具有感测终端或开尔文(Kelvin)终端的应用等等。
多路输出转换器200进一步包括第一驱动器/控制器芯片251和第二驱动器/控制器芯片252；这些芯片为转换器提供驱动和控制功能并且通过设定占空比来确定相对于DC输入电压的转换器的DC输出电压。作为示例，从12V的输入电压中，0.5的占空比能够实现6V的输出电压；0.25的占空比能够实现3V的输出电压。两个驱动器/控制器芯片均被附连到引线框架焊盘201并且紧密接近同步芯片220设置。在图2的示例实施例中，芯片251和252以及芯片220之间的距离为大约300μm。芯片251和252具有背侧金属镀膜(metallization)从而允许通过焊料(层厚度优选为大约25μm)附连到引线框架焊盘201。金属焊料提供高的导热性从而将热从芯片251、252传播到焊盘201。除了焊接，传导性的环氧树脂或银烧结是其他可能的芯片与线夹附连技术。在图2所示的示例实施例中，芯片251和252是正方形的(边长大约1.4至1.5mm)并且厚0.2mm。其他实施例可以具有更小或更大以及更厚或更薄的芯片。还有其他实施例可以将两个驱动器/控制器芯片组合到单个芯片中。此外，在某些转换器中，芯片251和252以及芯片220、211和212可以具有相同的厚度。第一驱动器/控制器芯片251被电地连接到(例如，通过键合线)栅极终端230和栅极返回终端231，并且进一步被连接到栅极终端215。第二驱动器/控制器芯片251被连接到(例如，通过键合线)栅极终端232和栅极返回终端233，并且进一步被连接到栅极终端216。
第一驱动器/控制器芯片251被电连接到(例如，通过键合线)栅极终端230和栅极返回终端231，并且进一步被连接到栅极终端215。第二驱动器/控制器芯片252被连接到(例如，通过键合线)栅极终端232和栅极返回终端233，并且进一步被连接到栅极终端216。矩形焊盘201的宽度和芯片251和252的相对较小的边长之间的差提供芯片终端和引线之间的距离，其可以如图2所示的那样显著。这个距离将线跨度从芯片终端拉伸到相应的引线，使得由于芯片251和252的厚度产生的任何高度差变得无关紧要。因此，可以在没有向下键合的情况下提供线连接253，从而增强转换器组件的可靠性。键合线253的优选直径是大约25μm，但是可以更小或更大。
图3代表图2的实施例的简化的电路图。场效应晶体管Q3(310)和Q1(320)是源极向下晶体管。Q3的芯片(图2中的211)被竖直堆叠在Q1的芯片(图2中的220)上，使得晶体管共用开关节点SW1(241)。场效应晶体管Q4(330)和Q2(340)是源极向下晶体管。Q4的芯片(图2中的212)被竖直堆叠在Q2的芯片(图2中的220)上，使得晶体管共用开关节点SW2(242)。晶体管Q3和Q4(通过共同的线夹260)被连接，以便共用相同的输入终端VIN(203)。晶体管Q1和Q2(通过引线框架焊盘201)被连接，以便共用相同的电接地终端360。如由虚线轮廓350指示的，晶体管Q1和Q2被集成到单个芯片220中。
对另一实施例保持相似的电路图和相似的考虑因素，其中芯片被制造使得晶体管Q3(410)和Q1(420)以及晶体管Q4(430)和Q2(440)是漏极向下晶体管。针对这种配置，在图4中描述电路图。如由虚线轮廓451指示的，两个漏极向下的晶体管Q3和Q3被集成到单个芯片中。这个共同的芯片被竖直地放置在晶体管Q1和Q2的芯片上，使得晶体管Q3和Q1可以共用开关节点SW1，并且晶体管Q4和Q2可以共用开关节点SW2。晶体管Q3和Q4被连接以便共用相同的输入终端VIN(203)。晶体管Q1和Q2被连接以便共用相同的电接地终端460。因为晶体管Q1和Q2的栅极终端位于芯片的与源极终端相同的侧面，因此必须将它们与源极终端电气隔离。Q1和Q2栅极到它们的相应的引脚或驱动器终端之间的连接可以诸如通过引线框架图案化或通常通过封装基底(例如，层压板)图案化来实现。例如，到驱动器的连接可以通过线键合来实现。在这个概念的实现中，晶体管Q1和Q2的栅极面向引线框架；因此，引线框架焊盘必须被设计带有细分部分(subdivision)，以便允许到晶体管Q1和Q2的栅极的电分离的连接。图4也可以用于其中封装的基底处于VIN的漏极向下晶体管的情况。
在本发明的另一个实施例中，晶体管Q3和Q4被制成漏极向下FET，而晶体管Q1和Q2被制成源极向下FET。在图5的简化的电路图中总结这种实施例，并且通过图6至图9的组装过程步骤更详细地描述了这种实施例，从而产生由图10A的顶视图和图10B的横截面图图示的被完成和封装的多路输出转换器，其总体被标记为1000。如图5所示，该实施例允许晶体管Q3和Q4被集成到单个芯片中(通过轮廓线551指示)，并且允许晶体管Q1和Q2被集成到另一个的单个芯片中(通过轮廓线550指示)。
该组装方法适于快速和低成本的批量生产，因为所有的附连可以通过单种焊料材料和单个回流温度来执行，使得可以采用一步到位附连工艺(one-step-fits-allattachment process)。焊膏被选择使得焊料回流温度高于线键合的温度。此外，几乎完全地避免了向下的线键合；线键合的温度低于焊料回流温度。此外，优选的是以条带的形式提供诸如引线框架和线夹的零部件，并且该零部件在封装步骤之后仅单立化。
3-维复合材料中零件的位置，例如半导体芯片的堆叠，可以利用诸如“低侧”或“高侧”的几何含义来描述。因为下面描述的示例实施例是同步降压转换器类型的多路输出电流转换器，因此零件的位置也可以以诸如“同步”或“控制”的功能含义来表达。
在图6中描述图5的实施例的组装方法的第一阶段。该方法通过提供基底的步骤开始，在这个示例中，金属引线框架具有矩形扁平组装焊盘201和与焊盘的侧边成直线设置的多条终端引线201。优选的引线框架金属是厚度范围从大约150至250μm的铜或铜合金；其他选项包括铝、铁-镍合金和柯伐合金TM。焊盘的两个表面都具有冶金学部署，这有助于焊料湿润和可焊性。作为铜引线框架的示例，焊盘表面可以具有附加的镍、钯和金(最外面的)的电镀层。对于引线，面向要被组装的芯片的表面是可诸如通过金的点电镀层而线键合的(优选的线金属是金和铜)。相对的引线表面优选地是可焊接的。可替换地，可以使用层压箔结构的基底，其具有组装焊盘和多个金属终端。
在接下来的步骤中，选择焊料混合物，优选地配置为基于锡的膏剂，其具有高于用于线键合的温度(大约220℃)的回流温度；在整个组装中使用该膏剂。
该组装开始于通过使用厚度大约为25μm或更大的焊膏层来将驱动器和控制器芯片650放置在引线框架焊盘201上；焊膏可以通过灌注或丝网印刷分配在焊盘201上。芯片650具有背侧金属喷镀(例如，镍或钛-钨层，随后是钯层)，以便使半导体芯片650的背侧可焊接。
在接下来的步骤中，低侧FET(同步FET)芯片210(其集成了两个集成的源极向下FET)临近驱动器和控制器芯片650被源极向下地放置在分配在焊盘201上的焊膏层上。FET芯片220的源极向下放置使两个集成的同步FET的共同的源极面向引线框架焊盘。因此，图6的顶视图显示两个集成的FET的漏极终端221和222。图6也显示分别临近漏极终端221和222的集成的FET的两个栅极终端230和232。组装焊料层的优选厚度是大约25μm或更大。为了保持寄生尽可能小，在不会冒液化的焊料层的相邻的弯月面(meniscus)偶然合并的风险的情况下，芯片650和芯片220之间的距离660优选地被选择为与组装布局规则允许的那么窄，并且在回流过程期间，其将于芯片650和220的表面张力诱导的相对运动配合。作为示例，对于某些焊料合金和层厚度，大约300μm是优选的距离。
图7A和7B图示下一个过程步骤，其包括放置和附连金属线夹，该金属线夹优选地作为一组线夹来提供(低侧组线夹附连)。金属线夹241(在本文中被称为第一线夹)和另一个金属线夹242(在本文中被称为第二线夹)被沉积在漏极终端221和222上的焊膏层上。第一线夹241和第二线夹242优选地是一组线夹；它们被成形以便作为多路输出转换器的开关节点；通过冲压和成型或蚀刻开始的金属片(大约厚0.2至0.3mm)，线夹获得某种结构，该结构使线夹部分开始停留在第一输出引线204(第一开关节点VSW1)上和第二输出引线205(第二开关节点VSW2)上。在图10B中描述线夹241和242的横截面。通过第一线夹241和第二线夹242的附连，第一FET芯片220可操作作为转换器的同步芯片。
图7A进一步显示另外的金属线夹的设置，其优选地被提供为一组线夹部分(gangclip segments)。作为栅极引线使用的引线206具有附连的线夹部分706(本文称为第四线夹)，和作为另一个栅极引线使用的引线207具有附连的线夹部分707(本文称为第五线夹)。直到下一个组装步骤，两个线夹部分的末端远离松弛地居于芯片220的绝缘体保护的表面上的各自的引线。保护绝缘体可以是氮化硅、二氧化硅、聚酰亚胺或其他适当的太空钝化处理。
在图8中图示的接下来的组装步骤中，高侧FET(控制FET)芯片210被放置在分配在线夹241和242上的焊膏层上，竖直地堆叠在同步芯片220上。芯片210包括双FET；两个均被制成漏极向下FET，使得源极终端和相邻的栅极终端在一个芯片表面上，并且漏极终端在相对的芯片表面上。然而，对于图8中描述的组装，芯片210被倒装使得源极和栅极终端面向同步芯片220并且漏极终端213和214远离同步芯片面向。在倒装芯片220之后，相应的源极终端(图8中没有显示)与线夹241和242对齐，被覆盖焊料膏层。当芯片210被降低以使源极终端与焊料层接触时，同时使栅极终端(图8没有显示)分别与(焊料层覆盖的)线夹706和707接触。因此，引线206和207变成芯片210的FET的栅极引线(高侧栅极引线)。
图9描述将共同的线夹(高侧线夹，第三金属线夹)260附连到高侧(控制芯片)210的漏极终端213和214的步骤。线夹260优选地作为一组线夹被提供。通过冲压和成型或蚀刻开始的金属片(大约厚0.2至0.3mm)，使被指定成为多路输出转换器的输入电源VIN的连接件的第三线夹260获得某种结构，该结构使得线夹部分与控制FET芯片210的放置并行地开始停留在分配在引线框架的(至少一个)引线203上的相同的焊膏层上。引线203作为转换器的输入终端，连接至输入电源VIN。
在接下来的工艺步骤中，热能被施加以升高温度从而使焊膏层在焊料融化温度回流。焊料合金被选择使得焊料回流温度充分高于接下来的工艺步骤中用于线键合所需要的温度。因为所有的焊料层由相同的材料组成，所以所有的焊料连接可以通过单个回流步骤并行地完成。这种简化特征显著地有利于低成本的制造方法。
图10A和10B描述线键合的接下来的工艺步骤。优选地，金或铜线(或偶尔地，带状物)用于将驱动器和控制芯片650的终端连接到引线框架的相应的引线，并且进一步连接到同步FET芯片的栅极终端和栅极返回终端以及栅极线夹，该栅极线夹连接到控制FET芯片的栅极。键合步骤几乎完全地避免了向下的键合并且因此使封装步骤期间线短路的熟知的可靠性问题最小化。
图10B示出接下来的将驱动器/控制芯片650、同步FET芯片220、控制FET芯片210、金属线夹，以及线键合封装在封装化合物290中的工艺步骤，因而产生转换器100的外部尺寸。使焊盘201的底部201a和引线的底部未封装，从而使得焊盘底部表面201a和引线底部表面可以被焊接到基底或电路板，其也可以是散热器。因为可以使第二线夹260上的化合物的厚度很小，所以可以将示例转换器的总厚度291保持为1.5mm。进一步通过保持第二线夹260的顶部表面未封装来减少该厚度是可能的，通过事实实现某一特征，即将驱动器/控制FET连接到控制FET的漏极终端和栅极终端不涉及线键合。
示例转换器1000的总体尺寸可以是长度292大约为7mm并且宽度293大约为5mm。
由于批量生产和低制作成分的缘由，优选的是以条带形式提供引线框架、第一线夹和第二线夹。在修剪工艺步骤中，将封装的条带单立化为分立式转换器单元，如同图2描述的转换器。优选的单立化技术是锯切。
上述不仅应用于场效应晶体管，而且应用于其他适当的功率晶体管、双极型晶体管、绝缘栅晶体管、晶体闸流管，等等。
多路输出电源转换器的结构和制作方法的上述考虑事项应用于多路输出调节器、多路输出电源转换器、具有感测终端的应用、具有开尔文终端的应用等等。
通过使第二线夹的顶表面未封装从而使得第二线夹可以优选地通过焊接被连接到散热器，多路输出转换器的高电流能力可以被进一步扩展，并且效率被进一步增强。在这种配置中，六面体形状的模块可以使其热量从两个大的表面耗散至散热器。
集成到与芯片堆叠结合的一个芯片内的组件的概念可以被扩展至每个芯片内的任意数量的组件和任意数量的竖直堆叠的组件。
本领域的技术人员将明白，可以对描述的实施例作出修改，并且也将明白，在要求保护的发明的范畴内，许多其他实施例是可能的。

Claims (20)

1.一种电子多路输出设备，其包括：
包括焊盘和引脚的基底；
复合第一芯片，其具有第一和第二晶体管，所述第一和第二晶体管被集成使得这些晶体管的第一终端在一个芯片表面上被合并成共同的终端，并且图案化的第二和第三终端在相对的芯片表面上；
所述共同的第一终端被附连到所述基底焊盘，并且所述第二终端通过分立式第一和第二金属线夹连接到相应的基底引脚；
具有第三晶体管的第二芯片，所述第三晶体管在一个芯片表面上具有第一终端，并且在相对的芯片表面上具有第二和第三终端，所述第二芯片的第一终端竖直地附连到所述第一金属线夹；和
具有第四晶体管的第三芯片，所述第四晶体管在一个芯片表面上具有第一终端，并且在相对的芯片表面上具有第二和第三终端，所述第三芯片的第一终端竖直地附连到所述第二金属线夹；和
所述第二和第三芯片的第二终端通过共同的线夹连接到基底引脚。
2.根据权利要求1所述的设备，其中所述设备是电源转换器。
3.根据权利要求1所述的设备，其中所述设备是调节器。
4.根据权利要求1所述的设备，其中所述基底选自包括引线框架、层压板和金属箔的群组。
5.根据权利要求1所述的设备，其中所述第一、第二、第三和第四晶体管是源极向下MOS场效应晶体管，其中所述第一终端是相应的晶体管的源极终端，所述第二终端是相应的晶体管的漏极终端，并且所述第三终端是相应的晶体管的栅极终端。
6.根据权利要求5所述的设备，其中所述基底焊盘是接地终端，被连接到所述共同的线夹的基底引脚是输入终端，并且被连接到所述第一和第二线夹的基底引脚是输出终端。
7.根据权利要求1所述的设备，其中所述第一、第二、第三和第四晶体管是漏极向下MOS场效应晶体管，其中所述第一终端是相应的晶体管的漏极终端，所述第二终端是相应的晶体管的源极终端，并且所述第三终端是相应的晶体管的栅极终端。
8.根据权利要求1所述的设备，其中所述第一、第二、第三和第四晶体管是双极型晶体管，其中所述第一终端是相应的晶体管的发射极终端并且所述第二终端是相应的晶体管的的集电极终端。
9.根据权利要求1所述的设备，其中所述第一、第二、第三和第四晶体管是双极型晶体管，其中所述第一终端是相应的晶体管的集电极终端并且所述第二终端是相应的晶体管的发射极终端。
10.根据权利要求1所述的设备，其中所述芯片由选自包括SiC、GaN、GaAs和其他III-V和II-IV化合物的群组的材料制成。
11.一种电子多路输出设备，其包括：
包括第一和第二焊盘和多个引脚的基底；
具有第一晶体管的第一芯片，所述第一晶体管在一个芯片表面上具有第一终端，并且在相对的芯片表面上具有第二和第三终端，所述第一芯片的第一终端关联到第一焊盘；和
具有第二晶体管的第二芯片，所述第二晶体管在一个芯片表面上具有第一终端，并且在相对的芯片表面上具有第二和第三终端，所述第二芯片的第一终端被关联到第二焊盘；
所述第一芯片和所述第二芯片的所述第二终端通过分立式第一和第二线夹连接到相应的基底引脚；和
具有第三和第四晶体管的复合第三芯片，所述第三和第四晶体管被集成使得该晶体管的第一终端在一个芯片表面上，并且被合并到共同的终端的第二终端和图案化的第三终端在相对的芯片表面上；
所述第三和第四晶体管的所述第一终端分别竖直地附连到所述第一和第二金属线夹，并且所述共同的终端通过共同的线夹连接到基底引脚。
12.根据权利要求11所述的设备，所述第一和第二焊盘连接到电接地电位，并且具有所述共同的线夹的基底引脚连接到VIN。
13.根据权利要求11所述的设备，其中所述第一、第二、第三和第四晶体管是漏极向下MOS场效应晶体管，其中所述第一终端是相应的晶体管的漏极终端，所述第二终端是相应的晶体管的源极终端，并且所述第三终端是相应的晶体管的栅极终端。
14.一种电子多路输出设备，其包括：
包括焊盘和引脚的基底；
具有多个晶体管的复合芯片，所述多个晶体管被集成使得该晶体管的第一终端在一个芯片表面上被合并为共同的终端，并且图案化的第二和第三终端在相对的芯片表面上；
所述共同的第一终端附连到所述基底焊盘，并且所述第二终端通过多个单独的线夹连接到相应的基底引脚；和
具有分立式晶体管的多个独立芯片，每个独立芯片的晶体管的第一终端在一个芯片表面上，并且其晶体管的第二和第三终端在相对的芯片表面上，每个独立芯片的第一终端竖直地附连到相应的独立线夹中的一个；和
每个独立芯片的第二终端通过共同的线夹连接到基底引脚。
15.一种电子多路输出设备，其包括：
包括焊盘和引脚的基底；
具有第一和第二晶体管的复合第一芯片，所述第一和第二晶体管被集成使得该晶体管的第一终端在一个芯片表面上被合并为共同的终端并且图案化的第二和第三终端在相对的芯片表面上；
所述共同的第一终端附连到所述基底焊盘，并且所述第二终端通过分立式第一和第二金属线夹连接到相应的基底引脚，该线夹是一组线夹；和
具有第三和第四晶体管的复合第二芯片，所述第三和第四晶体管被集成使得该晶体管的第二终端在一个芯片表面上被合并成共同的终端，并且图案化的第一和第三终端在相对的芯片表面上，所述第二芯片被倒装以便其第一终端被分别竖直地附连到所述第一和第二金属线夹，并且所述第三终端通过分立式的一组线夹连接到相应的基底引脚；
共同的第二终端通过共同的线夹连接到基底引脚，所述共同的线夹是一组线夹。
16.根据权利要求15所述的设备，其中所述基底选自包括引线框架、层压板和金属箔的群组。
17.根据权利要求15所述的设备，其中所述第一和第二晶体管是源极向下MOS场效应晶体管，其中所述第一终端是相应的晶体管的源极终端，并且所述第二终端是相应的晶体管的漏极终端；所述第三和第四晶体管是漏极向下MOS场效应晶体管，其中所述第二终端是相应的晶体管的漏极终端并且所述第一终端是相应的晶体管的源极终端。
18.一种封装的多路输出转换器，其具有电输入终端和接地终端，包括：
包括芯片焊盘和多条引线的引线框架，所述引线框架的所述焊盘是所述接地终端并且引线是所述电输入终端；
复合第一FET芯片，其在粘连到所述引线框架焊盘的表面上具有集成的源极终端，进一步在相对的表面上具有临近第二漏极终端设置的第一漏极终端，所述第一漏极终端通过第一金属线夹连接到第一输出引线并且所述第二漏极终端通过第二金属线夹连接到第二输出引线，其中所述第一FET芯片可作为所述转换器的同步芯片操作；
竖直地设置在所述第一漏极终端上并且其源极终端附连到所述第一金属线夹的第二FET芯片；
竖直地设置在所述第二漏极终端上并且其源极终端附连到所述第二金属线夹的第三FET芯片；和
所述第二和第三FET芯片的漏极终端附连到共同的第三金属线夹上，所述共同的第三金属线夹连接到所述输入引线，其中所述第二和第三FET芯片可作为所述转换器的相应的控制芯片操作。
19.根据权利要求18所述的多路输出转换器，其中所述第一FET芯片进一步包括临近所述第一漏极终端的第一栅极终端和临近所述第二漏极终端的第二栅极终端。
20.根据权利要求19所述的多路输出转换器，其中，所述第二FET芯片进一步包括临近其漏极终端的栅极终端，并且所述第三FET芯片进一步包括临近其漏极终端的栅极终端。
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