TWI476842B - 用於半導體裝置封裝的導電夾片 - Google Patents

用於半導體裝置封裝的導電夾片 Download PDF

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Publication number
TWI476842B
TWI476842B TW097151119A TW97151119A TWI476842B TW I476842 B TWI476842 B TW I476842B TW 097151119 A TW097151119 A TW 097151119A TW 97151119 A TW97151119 A TW 97151119A TW I476842 B TWI476842 B TW I476842B
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Taiwan
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semiconductor device
clip
lead frame
semiconductor
finger
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TW097151119A
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English (en)
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TW200949966A (en
Inventor
Lei Shi
Kai Liu
Ming Sun
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Alpha & Omega Semiconductor
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Publication of TW200949966A publication Critical patent/TW200949966A/zh
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Publication of TWI476842B publication Critical patent/TWI476842B/zh

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Description

用於半導體裝置封裝的導電夾片
本發明一般涉及半導體晶片封裝，更具體的，涉及一種適用於晶片封裝的源極夾片以提供一種電性連接的方法來降低擴展電阻，並且增強熱耗散。
在半導體器件的封裝中，通常使用一個金屬夾片來提供安裝在導線框架上的半導體晶片和該導線框架之間的電性連接。例如，美國專利第6,624,522號公開了一種金屬氧化物半導體(MOS)柵極器件晶片，其具有一被鈍化層覆蓋的柵極側，該鈍化層最好是感光的液體環氧樹脂層，或者是氮化矽層，或者由其他相似的物質構成。所述的晶片上塗布了紡織物、遮罩物，或者在晶片表面上沉積液態的環氧樹脂。材料乾燥後，使用標準光刻技術來暴露被塗布的晶片，從而圖案化晶片，並且在鈍化層中形成的開口用於在源極金屬下方形成許多的間隔分開的暴露表面區域，並且形成一相似的開口用於將晶片上每個晶片的柵極電極下方暴露出來。所述的鈍化層除了作為鈍化層外，進一步可作為抗電鍍劑(如果需要)以及作為焊錫掩模，標示並形成該焊錫區域。
隨後，晶圓被鋸開或通過其他方法形成單個晶片。所述的單個晶片隨後呈U形或杯形狀被設置在源極側的下方，通過使用導電的環氧樹脂或焊錫或者類似方法，將電鍍漏極夾片的一部分和晶片上可軟焊的漏極側連接，從而將漏極夾片鍵合到晶片底部漏極電極。漏極夾片的引腳的底部和晶片源極側的表面(即為突出部分的接觸頂面)是位於同一平面的。隨後，晶片的外表面使用盤式模型封裝。封裝後，對該器件進行測試，鐳射掩模並鋸開成各個器件。但是，該器件和標準的導線框架的輸出引腳並不相容。
美國專利6,777,800號公開了一種包含垂直功率MOSFET(金屬氧化物半導體場效應電晶體)的半導體晶片封裝，該垂直功率MOSFET具有設置在其底部表面上的柵極區域和源極區域，以及設置在其頂部表面上的漏極區域。一柵極引腳電耦合至所述的柵極區域，一源極引腳電耦合至所述的源極區域。一漏極夾片壹耦合至所述的漏極區域。使用一不導電也模塑膠封裝該半導體晶片，其中漏極夾片的表面是外露於該不導電的模塑膠的。但是，所述的半導體晶片封裝需要進行倒裝過程。
美國專利申請公佈檔20080087992公開了一種半導體封裝，其具有一橋式互連板。該封裝利用了一橋式源極互連板，其包含一橋形部分，設置於橋形部分兩側的低凹部分，若干個設置於低凹部分與橋形部分兩側的平面部分，與一個依靠於其中一個平面部分的連接部分。所述的橋形部分所設置的平面是高於低凹部分所處平面的，而所述若干平面部分所設置的平面是介於橋形部分所處的平面與低凹部分所處的平面之間的。在封裝過程中，焊錫材料流入橋形部分下方，且為橋式源極互連板提供了機械強度。
需要開發一種能提供高效熱耗散，並且以低電阻接入半導體器件的半導體器件封裝。進一步，也需要開發一種與標準半導體引腳分佈相相容的封裝。更進一步，製造一種具有堅固的應力消除結構，且可靈活用於不同尺寸半導體器件上的半導體器件封裝也是需要的。
在這樣的背景下提出了本發明的各個實施例。
本發明的目的在於提供一種半導體器件封裝，用於該半導體器件封裝的夾片，以及製成該半導體器件封裝的方法，該半導體器件封裝具有高效熱耗散，以低電阻接入半導體器件；其與標準的半導體封裝的引腳分佈相相容，具有堅固的應力消除結構，可靈活用於不同尺寸的半導體器件上。
為達上述目的，本發明提供一種用於半導體器件封裝的夾片，其包含2個或2個以上的分隔開的、且相互間通過被間隙分隔開的導電橋電性連接的導電指狀引腳；其中，至少一個指狀引腳的第一端是適合與引線框架電性接觸的；所述的導電橋是適用於提供其與半導體器件的頂部半導體區域之間的電性連接的。
該用於半導體器件封裝的夾片是由具有導熱和導電性質的材料製成的。
在所述的指狀引腳的第一側面和相鄰指狀引腳的第二側面之間，包含2個或2個以上所述的導電橋，所述的2個相鄰導電指狀引腳是通過該2個或2個以上的導電橋連接的。
所述的2個或2個以上的分隔開的導電指狀引腳包含第一、第二和第三指狀引腳；所述的導電橋包含位於第一指狀引腳和第二指狀引腳間的第一組導電橋，和位於第二指狀引腳和第三指狀引腳間的第二組導電橋。
所述的每個導電橋都是“V”形的，該每個“V”形導電橋的底部是適於和第一半導體區域建立電性連接的。
所述的指狀引腳和導電橋被配置來提供多個電的平行路徑，該多個電的平行路徑的相互間通過相鄰指狀引腳和相鄰導電橋之間的間隙分隔開。
所述的其中一個指狀引腳的長度沒有完全延伸到和晶片一樣的長度，以此容納半導體封裝中的其他特徵。
本發明還提供一種半導體器件封裝，包含：一引線框架，包含一主體部分和若干引腳；一半導體器件，至少包含一位於頂部表面的第一半導體區域和一位於底部表面的第二半導體區域；一夾片，包含2個或2個以上的分隔開的、且相互間通過被間隙分隔開的導電橋電性連接的導電指狀引腳；其中，至少一個指狀引腳的第一端是與引線框架的引腳電性接觸的；所述的夾片通過所述的導電橋和半導體器件的第一半導體區域電性連接；所述的第二半導體區域位於引線框架的主體部分上，並且和該主體部分電性連接。
所述的第一半導體區域是源極區域。
所述的每個導電橋都是“V”形的，該每個“V”形導電橋的底部是適於和第一半導體區域建立電性連接的。
至少一個所述的指狀引腳在夾片的頂部平面外呈現彎曲，使得其能夠在觸點處和引線框架實現連接。
所述的半導體封裝用模塑膠封裝，且各個指狀引腳的頂部表面沒有被模塑膠覆蓋。
進一步，所述的半導體器件是MOS器件；則第一半導體區域是源極，第二半導體區域是漏極；該金屬氧化物半導體器件進一步包含位於其頂部表面的柵極區域。
所述的柵極通過一鍵合線和引線框架電性連接；該鍵合線是被模塑膠覆蓋的。
所述的柵極通過一柵極夾片和引線框架電性連接；該柵極夾片的頂部表面可以和指狀引腳的頂部表面處於同一平面，用模塑膠封裝後，所述的柵極夾片的頂部表面是外露的；該柵極夾片的頂部表面也可以低於指狀引腳的頂部表面，且該柵極夾片的頂部表面被模塑膠覆蓋。
由所述的引線框架的主體部分引出的所述的一個或多個引腳是和引線框架的主體部分以及第二半導體區域電性連接的；所述的引腳是彎曲的，使得其頂部表面外露於模塑膠。
所述的引線框架可以是非熔接引線框架；也可以是熔接的引線框架。
所述的一個或多個指狀引腳在位於導電橋和引線框架的接觸點之間的夾片頂部平面區域內呈現彎曲，使得指狀引腳與引線框架的引腳對準從而和引線框架的引腳連接。
所述的夾片是由具有導熱和導電性質的材料製成的， 可配置使用於各種尺寸的半導體器件，提供貫穿半導體器件的第一半導體區域的多個平行的導電導熱路徑。
本發明還提供一種製成半導體器件封裝的方法，包含以下步驟：(a)將一半導體器件安裝到引線框架上，該半導體器件包含一位於其頂面的第一半導體區域和一位於其底面的第二半導體區域；由此該第二半導體區域依靠並電性連接該引線框架的主體部分；(b)將一夾片安裝到半導體器件和引線框架上，所述的夾片包含2個或2個以上分隔開的、且相互間通過被間隙分隔開的導電橋電性連接的導電指狀引腳；其中，至少一個指狀引腳的第一端與引線框架的引腳電性接觸；所述的導電橋是適用於為其和半導體器件的第一半導體區域提供電性連接的；所述的導電橋是安裝在半導體器件的第一半導體區域上的，且和該第一半導體區域電性連接；所述的夾片的至少一個指狀引腳和引線框架的引腳連接；以及(c)用模塑膠封裝半導體器件、部分引線框架和夾片，使得夾片的指狀引腳的頂部表面外露於模塑膠。
上述步驟中，所述的半導體器件是一垂直MOSFET，其中第一半導體區域是源極區域，第二半導體區域是漏極區域，該MOSFET進一步包含一位於其頂面的柵極區域；在步驟(a)與步驟(c)之間，進一步包含步驟(d)：將MOSFET的柵極區域連接到引線框架的柵極引腳上。
本發明可提供一種能提供高效熱耗散，並且以低電阻接入半導體器件的半導體器件封裝，其與標準半導體引腳分佈相相容，可靈活用於不同尺寸的半導體器件上。
雖然為了說明的目的下文的詳盡描述包含了許多特定的細節，但是任何本領域的普通熟練技術人員都將意識到，對於下文細節的許多變化和替代都將屬於本發明的範圍。因此，下文描述的本發明的示例性實施例將不背離本發明要求保護的基本原理，也不對本發明施加任何限制。
根據本發明的一個實施例，如第1A圖-第1B圖所示的一個半導體器件封裝100，其包含一個V形夾片，該V形夾片利用非外露的柵極金屬線鍵合到引線框架。如第1A圖所示，所述的器件封裝100包含一個熔接的引線框架102和一個半導體器件114，例如，一個具有頂部源極S，頂部柵極G和底部漏極D的MOS器件，其通過底部漏極D和引線框架102的主體部分連接從而位元於該引線框架102的頂部。例如，但不限定，所述的引線框架102可以是熔接的或者是非熔接的。在此所說的熔接的引線框架是指該引線框架中的若干源極引腳被熔接在一起。相反的，非熔接引線框架是指該引線框架中的若干源極引腳是相互獨立的，沒有熔片的(參見第4A圖-第4E圖所示)。如第1B圖中清晰所示，無論是上述哪種情況，所述的源極引腳和引線框架的主體部分之間是不存在電性接觸的。
根據本發明的一個實施例，所述的半導體器件封裝100 包含一個夾片112，該夾片112包含若干分隔開的相互平行的導電指狀引腳104，該些指狀引腳104通過導電橋106相互間電性且機械連接，並且通過導電橋106和半導體器件114的頂部源極之間建立電性連接。這種結構提供了多個電性平行路徑，該多個電性平行路徑是通過位於相鄰的指狀引腳104之間以及相鄰導電橋106之間的間隙107而相互間分隔開的。例如，但不限定，每個導電橋106具有近似於“V”的形狀，且通過“V”形的底部和半導體器件114頂部的源極襯墊實現電性連接。電流可從指狀引腳流向頂部源極，或者反過來也是一樣的，電流由頂部源極流向“V”形的底部，並通過“V”形兩側和“V”形頂部，流向指狀引腳104。所述的導電橋106可以具有其他的形狀，例如，“U”形也可以實現所述的源極和相鄰指狀引腳104之間的電性連接。本文中，“V”形用於描述一種通常的倒拱形狀，包括但不僅限於“U”形和其他等同的形狀。更好的，導電橋106的形狀要考慮到指狀引腳104和半導體器件114表面之間的距離，相鄰指狀引腳104間的縫隙大小，以及半導體器件114表面上的接觸區域。在一個優選實施例中，夾片112是由單獨的整塊材料製成的，例如，由單獨的一整塊金屬衝壓製成。
例如，但不限定，半導體器件114可以是金屬氧化物半導體(MOS)器件，其具有一頂部源極、一頂部柵極和一底部漏極。在這個例子中，夾片112有時被稱為“源極夾片”。夾片112僅僅通過導電橋106與半導體器件114 的頂部源極電性連接。每個“V”形的底部被弄平以促進導電橋106和半導體器件114的頂部源極之間的電性連接。半導體器件114的頂部柵極可以通過鍵合線108與柵極引腳110實現電性連接。導電指狀引腳104彎曲在夾片112的平面外發生彎曲，從而使得其能夠垂直的連接到熔接的源極引腳118，由此可節省半導體器件封裝100的封裝空間。
如第1C圖所示，半導體器件封裝100被封裝進模塑膠116中，且僅僅外露出各個指狀引腳104的頂部。但是在這個例子中，鍵合線108完全被模塑膠116覆蓋住了。例如，但不限定，所述的模塑膠116可以是環氧樹脂。
由於熱膨脹導致的矽和金屬之間的不匹配會引起壓力甚至分裂。如果在所述的矽和金屬之間具有一個大的單獨的接觸區域，那麼這個問題會更惡化。可以通過在半導體器件100內將所述的接觸區域分裂成若干較小的區域塊來解決上述問題。所述的夾片112通過由導電橋106提供的多個接觸點，在夾片112和MOS器件114之間提供一個壓力緩解結構，當夾片112被封裝進模塑膠116中時，這個壓力緩解結構對製作指狀引腳104的頂部表面提供較大的幫助。該導電橋106也可以增加封裝的機械強度，因為其為模塑膠116提供了多個位於不同角度的固定性能。
在夾片112中，通過導電橋106和指狀引腳104實現電性接觸的方法降低了擴展電阻。所述的擴展電阻是指由於電流由接觸點橫向流向導體時，導體中的電流發生擴散 而產生的電阻。可以通過分佈多個平行的傳導路徑來引導電流穿過位於半導體器件114頂部的觸點襯墊的方式來減少擴展電阻。相比於在美國專利申請公佈檔20080087992中所描述的觸點被密集設置，或者觸點的數目較少的源極夾片結構，如第1A圖-第1D圖中所示的夾片類型具有一個較低的電阻。在第1A圖-第1D圖所示的例子中，夾片112包含3個長的指狀引腳104和一個較短的指狀引腳104。在這個特殊的例子中，當外露區域的面積增加以使得通過導電橋的接觸點更多時，該較短的指狀引腳104可以調節平衡柵極區域。
本發明的另一個優點是和標準的半導體封裝的引腳相相容匹配。由此，本發明可以通過現存的設備實現，而不需要改變電路板或者其他周邊元件的設計。
第2A圖-第2D圖是根據本發明的一個較佳實施例所示的半導體器件封裝200。該半導體器件封裝200基本包含以上第1A圖-第1C圖中所描述的半導體器件封裝100的所有元件，除了用柵極夾片208替換之前的柵極鍵合線108。所述的器件封裝200包含一熔接的引線框架102，一包含頂部源極、頂部柵極和底部漏極的MOS器件114，該MOS器件114位於引線框架102的頂部，一包含若干分隔開的相互平行的導電指狀引腳104的夾片112，其中所述的若干導電指狀引腳104通過導電橋106相互間電性連接。所述的夾片112僅僅通過導電橋106和MOS器件114的頂部源極電性接合。如第1A圖-第1C圖所示，該指狀引腳 104在夾片112的平面外發生彎曲，使得其能夠垂直的連接到熔接的源極引腳118。在本實施例中，頂部柵極通過柵極夾片208電連接到引線框架102的柵極引腳110。在第2B圖所示的側視圖中可以看到，本實施例中，柵極夾片208的頂部表面和夾片112的頂部表面是在同一平面上的。第2D圖是半導體器件封裝200在被模塑膠116覆蓋封裝後的透視圖。如第2D圖所示，夾片112和柵極夾片208的頂部表面是外露的。
第3A圖根據本發明的另一個實施例所示的半導體器件封裝300的透視圖。本實施例是如第2A圖-第2D圖所示的實施例的一種變化。半導體器件封裝300基本包含了如第2A圖-第2D圖所示的半導體器件封裝200的所有元件。本實施例中，頂部柵極通過一柵極夾片308和引線框架102的柵極引腳110實現電性連接。但是，如第3B圖所示，柵極夾片308的頂部表面要低於夾片112的指狀引腳104的頂部表面。如第3C圖所示，當半導體器件封裝300被裝進模塑膠116後，由於夾片112和柵極夾片308的高度不同，當柵極夾片308被模塑膠116覆蓋住時，而指狀引腳104的頂部表面是外露的。
第4A圖-第4D圖是根據本發明的一個實施例描述了一半導體器件封裝400。例如，但不限定，所述的半導體器件封裝400包含一非熔接的引線框架402，一包含頂部源極、頂部柵極和底部漏極的MOS器件414，該MOS器件414位於該非熔接的引線框架402的頂部，還包含一源 極V形夾片412，其和MOS器件414的頂部源極電性連接。該非熔接的引線框架402包含若干非熔接的源極引腳413。所述的源極夾片412包含若干分隔開的相互平行的導電指狀引腳404，該導電指狀引腳404相互間通過導電橋406電性連接。該源極夾片412僅僅通過導電橋406和MOS器件414的頂部源極電耦合連接。相鄰的指狀引腳404和相鄰的導電橋406之間被間隙407分隔開。所述的在導電橋和引線框架402的非熔接的源極引腳413之間的那部分指狀引腳404在夾片412的平面內發生彎曲，使得指狀引腳404和非熔接的源極引腳413對準。進一步，所述的指狀引腳404在夾片412的平面外發生彎曲，使得其與非熔接的源極引腳413接觸連接。MOS器件的頂部柵極和引線框架402的柵極引腳410通過柵極夾片408實現電性連接。如第4B圖所示，柵極夾片408的頂部表面低於夾片412的指狀引腳404的頂部表面。可替換的(未顯示)，柵極夾片的頂部表面可以和夾片412的指狀引腳404的頂部表面位於同一片面，並且在封裝進模塑膠418後均外露頂部。
如第4D圖-第4E圖所示，所述的V形夾片412可以用於不同設計的MOS器件。詳細的，半導體器件封裝401和403可以各自包含不同大小尺寸的半導體器件415和416。所述導電橋分散的分佈形式保證了MOS器件的充分接觸，即使有些導電橋並未使用到。由於相同的夾片能被用於不同尺寸大小的器件，這會同時增加設計的靈活性以 及因經營規模擴大而得到的經濟節約。當然，對於熔接引線框架的夾片而言，例如第1A圖中所示的夾片112，其也可用於不同尺寸大小的器件。如第4F圖所示，為第4A圖-第4D圖以及第4E圖所描述的不同類型的半導體器件封裝被模塑膠418封裝覆蓋後的示意圖。第4F圖中，夾片412的頂部表面是外露的，而柵極夾片408是被模塑膠418覆蓋住的。
第5A圖為根據本發明的另一實施例所示的半導體器件封裝500的透視圖。該半導體器件封裝500是上述第2A圖-第2D圖所描述的半導體器件封裝200的變化。該半導體器件封裝500包含一熔接的引線框架102，一包含頂部源極、頂部柵極和底部漏極的半導體器件114，該半導體器件114位於引線框架所述引線框架102的頂部，一包含若干分隔開的指狀引腳104的夾片112，其中所述的若干指狀引腳104通過導電橋106相互間電性連接。所述的夾片112僅僅通過導電橋106和半導體器件114的頂部源極電性接合。指狀引腳104在夾片112的平面外發生彎曲，使得其能夠垂直的連接到熔接的源極引腳118。半導體器件114的頂部柵極通過柵極夾片208和引線框架102的柵極引腳110電性連接。導線框架102的漏極引腳和半導體器件114的底部漏極電性連接，該漏極引腳包含漏極引腳延伸區504，其被建立並彎曲以提供一個外露的頂部連接區，該頂部連接區的表面和源極夾片112以及柵極夾片208的表面在同一平面上。如第5B圖所示，即漏極引腳延伸區504、 柵極夾片208以及源極夾片112的頂部表面是位於同一平面的。半導體器件封裝500的部分被模塑膠516覆蓋。如第5C圖所示，漏極引腳延伸區504、柵極夾片208以及源極夾片112的頂部表面都是外露的。由於漏極、柵極和源極的電性接觸區域均設置在頂部，該半導體器件封裝500可以倒裝安裝在電路板上。在倒裝結構中，引線框架102的底部表面(也就是現在朝上的正表面)可以被設置為外露的，以用於熱耗散。可替代的，也可在引線框架102的底部表面(仍舊為現在朝上的正表面)上安裝一散熱片。
有很多不同的方法可以用來在半導體器件封裝中使用上述的各種類型的夾片以製成該半導體器件封裝。第6圖中顯示的流程圖僅舉例描述了製成半導體器件封裝的一種方法600。該方法可以參考上述根據第1A圖-第1C圖所示的半導體器件封裝的例子來瞭解。如在步驟610中所指出的，半導體器件114包含一位於其頂部的第一半導體區域，以及一位於其底部的、且連接到引線框架102上的第二半導體區域，由此，該第二半導體區域依靠並電性連接該引線框架的主體部分。例如，可以通過以下步驟來完成：首先，在引線框架102的主體部分上分配設置焊錫膏，隨後將半導體器件114放置到焊錫膏上。
如在步驟620中所指出的，將具有導電指狀引腳104和導電橋106的夾片112粘附安裝到半導體器件114上，使得導電橋106的基底和半導體器件114的第一半導體區域相接觸連接，並且使得一個或多個指狀引腳104和引線 框架102的引腳118相接觸連接。上述過程可以通過以下步驟來完成：首先，在第一半導體區域和引腳118的接觸區域上分配設置焊錫，隨後將夾片112粘附上去。此時，進行焊錫回流的操作，用以分別在引線框架102和半導體器件114、半導體器件114和夾片112以及夾片112和引腳118之間形成焊錫接合點。隨後，如在步驟630中所指出的，模塑膠116被封裝在半導體器件114、夾片112和引線框架102的部分的周圍。然而，夾片112的指狀引腳104的頂部表面是穿過模塑膠116暴露在外的。然後，進行一些標準的步驟，包括硬化模具，在封裝上鐳射打標，去除垃圾，去除毛刺，電鍍和/或修整引線框架/封裝元件。可選擇的，還可在指狀引腳104的外露頂部表面上附加安裝一散熱片。
儘管本說明書中所提到的實施例是頂部源極半導體器件，但本發明的範圍並不僅限於這種器件。例如，本發明的實施例也同樣適用於底部源極的半導體器件。本發明的核心夾片112和412也都適用於除了MOS器件以外的各種半導體器件，例如但不限定：功率雙極結型電晶體(BJT)，絕緣柵雙極型電晶體(IGBT)，晶體閘流管，二極體，電容器或電阻器。當然，夾片112和412在設計上可以有非常多的變化。指狀引腳的數量，長度，寬度和形狀，指狀引腳間的間距，以及導電橋之間的間距僅僅只是變化的一小部分，而且是可以調整的。並且，儘管本說明書中僅僅舉例說明瞭適用於一種特殊類型的半導體封裝(例如 DFN5x6)的夾片，但是，本發明的各實施例可以適用於其他類型的半導體封裝，例如，TO220，TSOP和SOT等。因此，本發明的實施例沒有限制適用於任何一種特殊類型的半導體封裝。
雖然上文對本發明的優選實施例進行了完整的描述，但是還可以使用各種替代，修改和等效形式。因此，本發明的範圍不應參考上文的描述確定，而是應該參考附後的權利要求及其等效內容的全部範圍確定。任何技術特徵不論是否優選都可以和任何其他不論是否優選的技術特徵組合。在附後的權利要求中，原文中的不定冠詞"A"或"An"指該冠詞之後的專案的數量為一個或多個，除非另有明確的指定。附後的權利要求不應解釋為包括方法加功能的限制，除非這樣的限制在所給出的權利要求中用詞語“其意義為”明確地指出。
100、200、300、400、401、500‧‧‧半導體器件封裝
102、402‧‧‧引線框架
104、404‧‧‧導電指狀引腳
106、406‧‧‧導電橋
107、407‧‧‧間隙
108‧‧‧鍵合線
110、410‧‧‧柵極引腳
112‧‧‧夾片
114、415、416‧‧‧半導體器件
116、216、316、418、516‧‧‧模塑膠
118、413‧‧‧源極引腳
208、308、408‧‧‧柵極夾片
412‧‧‧源極夾片
414‧‧‧MOS器件
504‧‧‧漏極引腳延伸區
MOS‧‧‧金屬氧化物半導體
在參考附圖閱讀下文的詳細描述後，本發明的目的和優點將顯而易見，附圖中：
第1A圖為根據本發明的實施例所示的一種半導體器件封裝的透視圖，該半導體器件封裝包含一個沒有外露柵極金屬線的V形夾片；
第1B圖為第1A圖所示的器件封裝的側視圖；
第1C圖為第1A圖所示的器件封裝被封裝進模塑膠後的透視圖；
第2A圖為根據本發明的另一實施例所示的一種半導體器件封裝的透視圖，該半導體器件封裝包含一個源極夾片和一個外露的柵極夾片；
第2B圖為第2A圖所示的器件封裝的側視圖；
第2C圖為第2A圖所示的器件封裝的俯視圖；
第2D圖為第2A圖所示的器件封裝被封裝進模塑膠後的透視圖；
第3A圖為根據本發明的另一實施例所示的一種半導體器件封裝的透視圖，該半導體器件封裝包含一個源極夾片和一個非外露的柵極夾片；
第3B圖為第3A圖所示的器件封裝的側視圖；
第3C圖為第3A圖所示的器件封裝被封裝進模塑膠後的透視圖；
第4A圖為根據本發明的另一實施例所示的一種半導體器件封裝的透視圖，該半導體器件封裝包含一個源極夾片，該源極夾片具有若干與一個非熔接的引線框架相配的指狀引腳；
第4B圖為第4A圖所示的器件封裝的側視圖；
第4C圖為第4A圖所示的器件封裝的俯視圖；
第4D圖為根據本發明的另一實施例所示的一種半導體器件封裝的透視圖，該半導體器件封裝包含一個源極夾片，該源極夾片具有若干與一個非熔接的引線框架相配的指狀引腳；
第4E圖為根據本發明的另一實施例所示的一種半導體器件封裝的透視圖，該半導體器件封裝包含一個源極夾片，該源極夾片具有若干與一個非熔接的引線框架相配的指狀引腳；
第4F圖為第4A圖、4D和4E所示的各器件封裝被封裝進模塑膠後的透視圖；
第5A圖為根據本發明的另一實施例所示的一種半導體器件封裝的透視圖，該半導體器件封裝包含一個源極夾片，該源極夾片具有若干漏極引腳和暴露在同一側面上的源極和柵極襯墊；
第5B圖為第5A圖所示的器件封裝的側視圖；
第5C圖為第5A圖所示的器件封裝被封裝進模塑膠後的透視圖；
第6圖為根據本發明的實施例所示的形成一個半導體器件封裝的流程圖。
在上述附圖中，相同的技術特徵引用相同的附圖標號。
400．．．半導體器件封裝
402．．．引線框架
404．．．導電指狀引腳
406．．．導電橋
407．．．間隙
408．．．柵極夾片
410．．．柵極引腳
412．．．源極夾片
413．．．源極引腳
414．．．MOS器件
MOS．．．金屬氧化物半導體

Claims (27)

  1. 一種用於半導體器件封裝的夾片，其特徵在於，包含：2個或2個以上的、分隔開的、設置在半導體器件上方的、且相互間通過複數個導電橋而電性連接的導電指狀引腳，其中該等導電橋被間隙分隔開，且至少一個指狀引腳的第一端是適合與引線框架電性接觸的；所述的導電橋於半導體器件的頂部半導體區域有多個電性連接的接觸點。
  2. 如申請專利範圍第1項所述的夾片，其特徵在於，在指狀引腳的第一側面和相鄰指狀引腳的第二側面之間，包含2個或2個以上所述的導電橋，所述的2個相鄰導電指狀引腳是通過該2個或2個以上的導電橋連接的。
  3. 如申請專利範圍第1項所述的夾片，其特徵在於，所述的2個或2個以上的分隔開的導電指狀引腳包含第一、第二和第三指狀引腳；所述的導電橋包含位於第一指狀引腳和第二指狀引腳間的第一組導電橋，和位於第二指狀引腳和第三指狀引腳間的第二組導電橋。
  4. 如申請專利範圍第1項所述的夾片，其特徵在於，所述的每個導電橋都是“V”形的，該每個“V”形導電橋的底部是適於和第一半導體區域建立電性連接的。
  5. 如申請專利範圍第1項所述的夾片，其特徵在於，所述的夾片是由具有導熱和導電性質的材料製成的。
  6. 如申請專利範圍第1項所述的夾片，其特徵在於，所 述的指狀引腳和導電橋被配置來提供多個電的平行路徑，該多個電的平行路徑的相互間通過相鄰指狀引腳和相鄰導電橋之間的間隙分隔開。
  7. 如申請專利範圍第1項所述的夾片，其特徵在於，所述的其中一個指狀引腳的長度沒有完全延伸到和晶片一樣的長度，以此容納半導體封裝中的其他特徵。
  8. 一種半導體器件封裝，其特徵在於，包含：一引線框架，其包含一主體部分和若干引腳；一半導體器件，其至少包含一位於頂部表面的第一半導體區域和一位於底部表面的第二半導體區域；一夾片，其包含2個或2個以上的、分隔開的、設置在半導體器件上方的、且相互間通過複數個導電橋而電性連接的導電指狀引腳，其中該等導電橋被間隙分隔開，且至少一個指狀引腳的第一端是與引線框架的引腳電性接觸的；所述的夾片通過所述的導電橋的多個接觸點和半導體器件的第一半導體區域電性連接；所述的第二半導體區域位於引線框架的主體部分上，並且和該主體部分電性連接。
  9. 如申請專利範圍第8項所述的半導體器件封裝，其特徵在於，所述的第一半導體區域是源極區域。
  10. 如申請專利範圍第8項所述的半導體器件封裝，其特徵在於，所述的每個導電橋都是“V”形的，該每個“V”形導電橋的底部是適於和第一半導體區域建立電性 連接的。
  11. 如申請專利範圍第8項所述的半導體器件封裝，其特徵在於，至少一個指狀引腳在夾片的頂部平面外呈現彎曲，使得其能夠在觸點處和引線框架實現連接。
  12. 如申請專利範圍第8項所述的半導體器件封裝，其特徵在於，所述的半導體封裝用模塑膠封裝，且各個指狀引腳的頂部表面沒有被模塑膠覆蓋。
  13. 如申請專利範圍第12項所述的半導體器件封裝，其特徵在於，所述的半導體器件是金屬氧化物半導體器件；所述的第一半導體區域是源極，第二半導體區域是漏極；以及所述的金屬氧化物半導體器件進一步包含位於其頂部表面的柵極區域。
  14. 如申請專利範圍第13項所述的半導體器件封裝，其特徵在於，所述的柵極通過一鍵合線和引線框架電性連接。
  15. 如申請專利範圍第14項所述的半導體器件封裝，其特徵在於，所述的鍵合線是被模塑膠覆蓋的。
  16. 如申請專利範圍第13項所述的半導體器件封裝，其特徵在於，所述的柵極通過一柵極夾片和引線框架電性連接。
  17. 如申請專利範圍第16項所述的半導體器件封裝，其特徵在於，所述的柵極夾片的頂部表面和指狀引腳的 頂部表面處於同一平面，用模塑膠封裝後，所述的柵極夾片的頂部表面是外露的。
  18. 如申請專利範圍第16項所述的半導體器件封裝，其特徵在於，所述的柵極夾片的頂部表面低於指狀引腳的頂部表面，且該柵極夾片的頂部表面被模塑膠覆蓋。
  19. 如申請專利範圍第12項所述的半導體器件封裝，其特徵在於，由引線框架的主體部分引出的所述的一個或多個引腳是和引線框架的主體部分以及第二半導體區域電性連接的；所述的引腳是彎曲的，使得其頂部表面外露於模塑膠。
  20. 如申請專利範圍第8項所述的半導體器件封裝，其特徵在於，所述的引線框架是非熔接引線框架。
  21. 如申請專利範圍第8項所述的半導體器件封裝，其特徵在於，所述的引線框架是熔接的引線框架。
  22. 如申請專利範圍第8項所述的半導體器件封裝，其特徵在於，所述的一個或多個指狀引腳在位於導電橋和引線框架的接觸點之間的夾片頂部平面區域內呈現彎曲，使得指狀引腳與引線框架的引腳對準從而和引線框架的引腳連接。
  23. 如申請專利範圍第8項所述的半導體器件封裝，其特徵在於，所述的夾片是由具有導熱和導電性質的材料製成的。
  24. 如申請專利範圍第8項所述的半導體器件封裝，其特 徵在於，所述的夾片配置使用於各種尺寸的半導體器件。
  25. 如申請專利範圍第8項所述的半導體器件封裝，其特徵在於，所述的夾片提供貫穿半導體器件的第一半導體區域的多個平行的導電導熱路徑。
  26. 一種製成半導體器件封裝的方法，其特徵在於，包含步驟：(a)將一半導體器件安裝到引線框架上，該半導體器件包含一位於其頂面的第一半導體區域和一位於其底面的第二半導體區域；由此該第二半導體區域依靠並電性連接該引線框架的主體部分；(b)將一夾片安裝到半導體器件和引線框架上，所述的夾片包含2個或2個以上、分隔開的、設置在半導體器件上方的、且相互間通過複數個導電橋而電性連接的導電指狀引腳，其中該等導電橋被間隙分隔開，且至少一個指狀引腳的第一端與引線框架的引腳電性接觸；所述的導電橋是安裝在半導體器件的第一半導體區域上的，且經由多個接觸點和該第一半導體區域電性連接；所述的夾片的至少一個指狀引腳和引線框架的引腳連接；以及(c)用模塑膠封裝半導體器件、部分引線框架和夾片，使得夾片的指狀引腳的頂部表面外露於模塑膠。
  27. 如申請專利範圍第26項所述的方法，其特徵在於，所述的半導體器件是一垂直金屬氧化物半導體場效應電晶體，所述的第一半導體區域是源極區域，第二半導體區域是漏極區域，所述的金屬氧化物半導體場效應電晶體進一步包含一位於其頂面的柵極區域；並且所述方法在步驟(a)與步驟(c)之間，進一步包含：(d)將金屬氧化物半導體場效應電晶體的柵極區域連接到引線框架的柵極引腳上。
TW097151119A 2008-05-30 2008-12-26 用於半導體裝置封裝的導電夾片 TWI476842B (zh)

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US8680658B2 (en) 2014-03-25

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