CN101512741A - 半导体器件的制造方法及制造装置 - Google Patents
半导体器件的制造方法及制造装置 Download PDFInfo
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Abstract
提供半导体器件的制造方法及制造装置。在进行回流焊时,首先将凸块(12)的上部(12b)加热至该凸块(12)的熔融温度以上的规定温度,使得先从该上部(12b)开始熔融。接着,将凸块(12)的下部(12a)加热至该凸块(12)的熔融温度以上的规定温度,使该下部(12a)熔融。此时,凸块(12)的上部(12b)已开始熔融,处于焊料粘性降低的状态,而且,在下部(12a)熔融的阶段,凸块(12)无偏斜且大致均匀地熔融,呈大致球状的稳定形状。因此,即使发生热振动等,由于已形成为稳定形状,因此不存在凸块(12)发生倾倒等担心,而且各凸块(12)在彼此相邻处不会发生短路,从而能够获得所希望的良好的回流焊状态。
Description
技术领域
本发明涉及一种对在形成于表面上的多个电极上分别设置凸块而成的衬底进行加热,使凸块熔融以实现回流焊的半导体器件的制造方法及制造装置。
背景技术
以往,在制造半导体器件或电子部件时,为了对在形成于衬底表面上的多个电极上分别设置的凸块、例如焊料凸块进行回流焊,将该衬底设置在加热处理腔室内,从衬底背面进行加热以使凸块熔融,以此进行回流焊。
另外,在专利文献1、2中公开了如下技术:在进行该回流焊处理时,为了通过还原除去形成在凸块表面上的氧化膜,在加热处理腔室内导入蚁酸等。
专利文献1:JP特开2002-210555号公报
专利文献2:JP特开平7-164141号公报
发明内容
近年来,对半导体器件或电子部件的进一步的细微化和高集成化日益发展,与此相伴,要求缩短衬底表面的电极间的距离、即焊料凸块间的距离。缩短该凸块间距离引发了如下问题。
图7A~图7C是用于说明现有的焊料凸块的回流焊处理技术的问题的示意图。在图7A~图7C中,上方的图表示加热处理腔室内的情形,下方的图表示对上方图中的矩形框内的焊料凸块进行了放大的情形。
首先,如图7A的上图所示,将半导体晶片110设置在加热处理腔室101内的支撑销102上,其中,该半导体晶片110是在形成于表面上的多个电极端子111上分别设置有焊料凸块112的半导体晶片。在此,例示了例如通过电镀法将焊料凸块112形成为其上部(伞状部分)112b比下部112a(根部)大的所谓的悬垂(overhang)形状的情况。
然后,向加热处理腔室101内导入还原性气体,在此导入的是蚁酸,并通过配置在加热处理腔室101内的下部的加热器104,即通过与半导体晶片110的背面相对地配置的加热器104,将加热处理腔室101内部加热至形成在焊料凸块112表面上的表面氧化膜(未图示)的还原温度以上且焊料凸块112的熔融温度以下的规定温度。此时,如图7A的下图所示,表面氧化膜被除去,处于使焊料凸块112的表面露出的状态。
接着,如图7B的上图所示,衬底移动机构(未图示)在上下方向上驱动支撑销102,使支撑销102向下方移动,从而使半导体晶片110接近加热器104。在该状态下,加热器104将半导体晶片110从其背面加热至焊料凸块112的熔融温度以上的规定温度。在该加热处理中,由于从下方对焊料凸块112进行加热,因此在焊料凸块112的下部112a和上部112b,开始熔融的时机(timing)分别不同,先从下部112a开始熔融。
此时,当相邻的焊料凸块112的间隔距离小时,如图7B的下图所示,相邻的焊料凸块112在上部112b接触。其原因在于,通过上述加热,下部112a的焊料粘性降低,而上部112b几乎处于未熔融状态,因此焊料凸块112因热振动等而发生倾倒。如果相邻的焊料凸块112的间隔距离相对大,则即使焊料凸块112倾倒,相邻的焊料凸块112之间也不会发生接触,但该间隔距离越小,发生接触的可能性就越大。
一旦接触的焊料凸块112,即使通过上述加热完全熔融,也保持接触的状态。因此,存在如下问题:如图7C所示,在接触的焊料凸块112之间发生桥接(bridge)113,从而引起短路。
本发明是鉴于上述课题而提出的,其目的在于,提供一种半导体器件的制造方法及制造装置,上述装置和方法即使为了响应对半导体器件或电子设备的进一步的细微化和高集成化的要求而缩短了相邻的凸块间距离,也不会使该凸块之间发生短路,从而能够实现良好的所希望的凸块回流焊,因此能够提供可靠性高的产品。
本发明的衬底处理方法包括:第一工序,仅对在半导体衬底的一侧主面的电极上形成的凸块的上部进行加热以使其熔融;第二工序,对所述凸块的下部也进行加热,使所述凸块的整体熔融。
本发明的半导体器件的制造装置包括:第一加热单元,其设置在腔室内的上部;第二加热单元,其设置在所述腔室内的下部。
根据本发明,即使为了响应对半导体器件或电子设备的进一步的细微化和高集成化的要求而缩短相邻的凸块间距离,也不会使该凸块之间发生短路,从而能够实现良好的所希望的凸块回流焊,因此能够提供可靠性高的产品。
附图说明
图1是表示本实施方式的半导体器件的制造装置的概略结构的示意图。
图2A是按照工序顺序表示用于形成本实施方式中所使用的焊料凸块的方法的概略截面图。
图2B是接着图2A,按照工序顺序表示用于形成本实施方式中所使用的焊料凸块的方法的概略截面图。
图2C是接着图2B,按照工序顺序表示用于形成本实施方式中所使用的焊料凸块的方法的概略截面图。
图2D是接着图2C,按照工序顺序表示用于形成本实施方式中所使用的焊料凸块的方法的概略截面图。
图3A是按照工序顺序表示本实施方式的衬底处理方法的示意图。
图3B是接着图3A,按照工序顺序表示本实施方式的衬底处理方法的示意图。
图3C是接着图3B,按照工序顺序表示本实施方式的衬底处理方法的示意图。
图4A是接着图3C,按照工序顺序表示本实施方式的衬底处理方法的示意图。
图4B是接着图4A,按照工序顺序表示本实施方式的衬底处理方法的示意图。
图4C是接着图4B,按照工序顺序表示本实施方式的衬底处理方法的示意图。
图5A是接着图4C,按照工序顺序表示本实施方式的衬底处理方法的示意图。
图5B是接着图5A,按照工序顺序表示本实施方式的衬底处理方法的示意图。
图6是表示成为本实施方式的处理对象的另一半导体晶片的例子的概略截面图。
图7A是用于说明现有的焊料凸块的回流焊处理技术的问题的示意图。
图7B是接着图7A,用于说明现有的焊料凸块的回流焊处理技术的问题的示意图。
图7C是接着图7B,用于说明现有的焊料凸块的回流焊处理技术的问题的示意图。
具体实施方式
本发明的基本要点
本发明人着眼于对凸块进行回流焊时的相邻凸块之间的短路起因于从该凸块的下方进行的加热,想到了本发明。在本发明中,在进行回流焊时,首先,将凸块的上部加热至该凸块的熔融温度以上的规定温度,使得先从该上部起开始熔融。接着,将凸块的下部加热至该凸块的熔融温度以上的规定温度,使该下部熔融。此时,凸块的上部已经开始熔融,处于焊料粘性降低的状态,而且,在该下部熔融的阶段,该凸块无偏斜且大致均匀地熔融,成为大致球状(或者半球状)的稳定形状。因此,即使发生热振动等,由于已经处于稳定形状,因此不存在凸块发生倾倒等担心,而且各凸块在彼此相邻处不会发生短路,从而能够获得所希望的良好的回流焊状态。
进而,本发明人想到了实现上述加热处理的半导体器件的制造装置的具体结构。本发明的半导体器件的制造装置采用了如下结构:为了自如地对凸块上部以及下部进行各加热处理,在加热处理腔室内,与衬底表面相对地配置第一加热单元,与衬底背面相对地配置第二加热单元,而且,能够对各加热单元分别独立地或者同时进行加热控制。
进而,在本发明的半导体器件的制造装置中,配置有使衬底对于第一加热单元或者第二加热单元进行相对移动的衬底移动单元。通过该结构,能够调整衬底的位置,使得在对衬底表面以及背面中的一个面进行加热时,另一个面不会受到该加热的影响。
应用本发明的最佳实施方式
图1是表示本实施方式的半导体器件的制造装置的概略结构的示意图。
该半导体器件的制造装置具有:加热处理腔室1,用于容纳作为被处理对象的衬底,在此,容纳的是半导体晶片;支撑销2,用于支撑容纳在加热处理腔室1内的衬底;作为加热单元的上部加热器3以及下部加热器4;移动机构5、6,分别使上部加热器3以及下部加热器4移动;真空泵7,用于对加热处理腔室1内部抽真空;气体导入机构8,用于向加热处理腔室1内导入环境气体。
支撑销2用于在半导体晶片的外周部支撑半导体晶片,在此,设置有4个(在图示的例子中,仅显示了2个)。通过这些4个支撑销2来均匀地支撑固定半导体晶片。支撑销2贯通下部加热器4内部,而且设置有使支撑销2相对于下部加热器4在上下方向上移动的移动机构(未图示)。
上部加热器3例如是红外线灯加热器等,在加热处理腔室1内,设置在上部,即设置在所设置的半导体晶片的表面(设置有焊料凸块的面)侧,并具有能够自由地控制为所期望的加热温度及加热时间的加热控制机构(未图示)。
下部加热器4例如是红外线灯加热器等,在加热处理腔室1内,设置在下部,即设置在所设置的半导体晶片的背面(未设置有焊料凸块的面)侧,并具有能够自由地控制为所期望的加热温度及加热时间的加热控制机构(未图示)。
此外,上部加热器3以及下部加热器4采用能够分别独立地或者同时(协同动作)进行加热控制的结构。
移动机构5用于使上部加热器3相对于所设置的半导体晶片的表面在上下方向上自由地移动,在此,该移动机构5具有气缸(air cylinder)。
移动机构6用于使下部加热器4相对于所设置的半导体晶片的背面在上下方向上自由地移动,在此,该移动机构6具有气缸。
移动机构5以及移动机构6能够分别独立地工作(对上部加热器3和下部加热器4独立地进行移动控制)。除了该独立工作功能外,在本实施方式中,通过两者的协同动作来驱动上部加热器3和下部加热器4,使得第一加热器3和第二加热器4之间的间隔距离保持恒定,例如保持为30mm左右。由于采用这样的结构,例如在通过上部加热器3对衬底表面进行加热时,不受来自下部加热器4的加热所带来的影响。
为了在对凸块进行回流焊处理之前除去形成于凸块表面上的氧化膜,气体导入机构8向加热处理腔室1内导入还原性气体,例如导入规定量的蚁酸气体。
下面,对使用了图1的半导体器件的制造装置的处理方法进行说明。
图2A~图2D是按照工序顺序表示用于形成本实施方式中所使用的焊料凸块的方法的概略截面图。图3A~图5B是按照工序顺序表示本实施方式的衬底处理方法的示意图。在此,在图3C、图4A~图4C中,上方的图表示加热处理腔室内的情形,下方的图表示对上方图中的矩形框内的焊料凸块进行放大的情形。
首先,在半导体晶片的表面形成焊料凸块。
首先,如图2A所示,准备半导体晶片(硅晶片)10,在该半导体晶片10形成有晶体管或半导体存储器等半导体元件,而且在该半导体晶片10表面上形成有多个用于与这些半导体元件进行外部连接的电极端子11。
接着,如图2B所示,以覆盖半导体晶片10的表面的方式涂布形成电镀种子层(未图示)以及光刻胶膜,通过光刻法对光刻胶膜进行加工,形成光刻胶掩模21,该光刻胶掩模使各电极端子11在表面形成有电镀种子层的状态下从开口21a露出。
接着,如图2C所示,例如通过电解电镀法,在从光刻胶掩模21的开口21a露出的电镀种子层上,利用焊料、在此为SnAg类焊料来进行电镀成膜,形成分别与各电极端子11连接的焊料凸块12。
将焊料凸块12形成为在回流焊后能够得到规定高度的形状,在此,使焊料凸块12的高度比光刻胶掩模21的厚度高,即,使焊料凸块12的上部高出光刻胶掩模21的表面。更具体地说,将焊料凸块12形成为其上部比下部(电镀填充在开口21a内的部分)大的伞形状。
另外,作为焊料凸块12的电镀材料,也可以采用SnAgCu类焊料或PbSn类焊料来取代SnAg类焊料。
接着,如图2D所示,通过灰化处理等来除去光刻胶掩模21,并使用规定的药水除去光刻胶掩模21下的电镀种子层。通过以上各工序,半导体晶片10处于在表面的各电极端子11上分别形成了焊料凸块12的状态。此时,并排形成的焊料凸块12的间距例如为200μm左右,其尺寸为180μm左右。
接着,对半导体晶片10的各焊料凸块12进行回流焊处理。
首先,如图3A所示,将半导体晶片10导入至图1的半导体器件的制造装置的加热处理腔室1内,其中,该半导体晶片10处于在其表面的各电极端子11上分别形成有焊料凸块12的状态。
图3B表示将半导体晶片10导入至加热处理腔室1内,并通过支撑销2在半导体晶片10的外周部支撑固定半导体晶片10的情形。
在此,如图3C的下图所示,由于自然氧化等,其处于在焊料凸块12的表面形成有氧化膜13的状态。在本实施方式中,如下所述,在进行回流焊处理之前除去氧化膜13。
首先,通过驱动真空泵7,使加热处理腔室1内处于规定的真空状态,然后如图3C的上图所示,通过气体导入机构8,向加热处理腔室1内导入还原性气体,在此,导入的是规定量的蚁酸气体。在导入蚁酸气体时,将加热处理腔室1的环境温度调节为低于焊料凸块12的熔融温度且达到氧化膜13的还原开始温度附近(还原开始温度±5℃左右)的温度,例如调节为170℃左右。
接着,如图4A的上图所示,通过加热驱动上部加热器3,从半导体晶片10的表面侧对各焊料凸块12进行加热。在此,以达到氧化膜13的还原开始温度以上且低于焊料凸块12的熔融温度的温度,例如以190℃左右的温度,进行2~3分钟左右的加热处理。通过该加热处理,如图4A的下图所示,氧化膜13与蚁酸气体发生反应而被还原,从而从焊料凸块12的表面被除去。由此,使焊料凸块12处于其表面露出的状态。
此外,在图4A的上图中,例示了如下情况:如图3B所示那样,在半导体晶片10被支撑固定在支撑销2上的阶段,将上部加热器3和半导体晶片10的表面之间的间隔距离调整为适合于上部加热器3对各焊料凸块12进行加热的值。在此,在进行该加热处理时,也可以通过移动机构5使上部加热器3移动,从而将上述间隔距离调整为适合于上部加热器3对各焊料凸块12进行加热的值。
接着,如图4B的上图所示,使上部加热器3的温度上升,继续从半导体晶片10的表面侧对各焊料凸块12进行加热。在此,以焊料凸块12的熔融温度以上的温度例如以270℃左右的温度,进行1分钟以上的加热处理。通过该加热处理,如图4B的下图所示,各焊料凸块12的上部(伞状部分)12b优先于下部12a(根部)(在下部12a之前)被熔融。
接着,如图4C的上图所示,通过移动机构6使下部加热器4(向上方)移动,使下部加热器4接近半导体晶片10的背面,从而将下部加热器4和半导体晶片10的背面之间的间隔距离调整为适合于下部加热器4对各焊料凸块12进行加热的值。在此,在通过移动机构6使下部加热器4移动时,移动机构5与移动机构6协同动作,使得上部加热器3和下部加热器4之间的间隔距离保持恒定,例如保持为30mm,其结果,移动机构5使上部加热器3(向上)移动,使上部加热器3远离半导体晶片10的表面。
然后,通过加热驱动下部加热器4,从半导体晶片10的背面侧对各焊料凸块12进行加热。在此,以焊料凸块12的熔融温度以上的温度例如以270℃左右的温度,进行1分钟以上的加热处理。此时,也可以适当地继续进行通过上部加热器3的加热处理。如上所述,由于上部加热器3和下部加热器4之间的间隔距离保持恒定,因此能够防止上部加热器3将各焊料凸块12的上部加热至必要温度以上。
通过该加热处理,如图4C的下图所示,各焊料凸块12的下部(根部)12a接着上部12b开始熔融。此时,各焊料凸块12的上部12b已经熔融,处于焊料粘性降低的状态,而且,在该下部12a熔融的阶段,各焊料凸块12无偏斜且大致均匀地熔融,处于例如大致球状的稳定形状。因此,即使发生热振动等,由于已经形成为稳定形状,因此不存在各焊料凸块12发生倾倒等的担心,而且各焊料凸块12在彼此相邻处不会发生短路,从而能够获得所希望的良好的回流焊状态。
接着,停止对上部加热器3以及下部加热器4的加热驱动,如图5A所示,通过移动机构5、6使上部加热器3以及下部加热器4的位置恢复到初始状态。之后,通过驱动真空泵7,排出加热处理腔室1内的蚁酸气体。
然后,如图5B所示,从加热处理腔室1向外部取出半导体晶片10。此时,半导体晶片10的各焊料凸块12在彼此相邻处没有发生短路等,保持回流焊时的良好的大致球状。
如上所说明,根据本实施方式,即使为了响应半导体器件或电子设备的进一步的细微化和高集成化的要求而缩短相邻的焊料凸块12之间的距离,也不会使该焊料凸块12之间发生短路,从而能够实现良好的所希望的凸块回流焊,因此能够提供可靠性高的产品。
此外,在本实施方式中,例示了将半导体晶片10的各焊料凸块12形成为其上部12b比下部12a大的所谓的蘑菇(mushroom)状的情况,但是在本发明中,并不限定于该焊料凸块12。例如,如图6所示,也可以将如下的半导体晶片10作为处理对象,该半导体晶片10通过电解电镀法在电极端子11上形成了直线(straight)形状(在上部和下部形状相同)的焊料凸块22。
当形成了直线形状的焊料凸块22时,若通过图7A~图7B所示的现有的衬底处理方法进行回流焊处理,则尽管不显著,但在焊料凸块12上同样也会存在倾倒、短路。因此,通过应用与本实施方式相同的衬底处理方法,例如与图5B同样,能够得到如下半导体晶片10,在该半导体晶片10上,各焊料凸块22在彼此相邻处没有发生短路等,呈回流焊时的良好的大致球状。
产业上的可利用性
根据本发明,即使为了响应半导体器件或电子设备的进一步的细微化和高集成化的要求而缩短相邻的凸块间距离,也不会使该凸块间发生短路,从而能够实现良好的所希望的凸块回流焊,因此能够提供可靠性高的产品。
Claims (14)
1.一种半导体器件的制造方法,其特征在于,包括:
第一工序,仅对在半导体衬底的一侧主面的电极上形成的凸块的上部进行加热以使其熔融;以及
第二工序,对所述凸块的下部也进行加热,使所述凸块的整体熔融。
2.根据权利要求1所述的半导体器件的制造方法,其特征在于,所述第一工序和第二工序是在蚁酸气体环境中进行的。
3.根据权利要求1所述的半导体器件的制造方法,其特征在于,在所述第一工序以及第二工序之前,利用蚁酸气体对所述半导体衬底进行所述氧化膜的除去处理,所述蚁酸气体是指,将温度调整为低于所述凸块的熔融温度且达到形成在所述凸块表面上的氧化膜的还原开始温度附近的温度的蚁酸气体。
4.根据权利要求3所述的半导体器件的制造方法,其特征在于,将所述蚁酸气体环境温度控制为低于所述凸块的熔融温度且在所述氧化膜的还原开始温度±5℃的范围内。
5.根据权利要求1所述的半导体器件的制造方法,其特征在于,所述凸块是焊料凸块。
6.根据权利要求1所述的半导体器件的制造方法,其特征在于,所述凸块形成为所述上部比所述下部大的悬垂形状。
7.一种半导体器件的制造装置,其特征在于,包括:
第一加热单元,其设置在腔室内的上部;以及
第二加热单元,其设置在所述腔室内的下部。
8.根据权利要求7所述的半导体器件的制造装置,其特征在于,所述第一加热单元以及所述第二加热单元分别独立地或者同时进行加热控制。
9.根据权利要求7所述的半导体器件的制造装置,其特征在于,在所述腔室内,所述第二加热单元设置为与所述第一加热单元相对。
10.根据权利要求7所述的半导体器件的制造装置,其特征在于,还包括:
第一移动单元,其使所述第一加热单元在上下方向上移动;以及
第二移动单元,其使所述第二加热单元在上下方向上移动。
11.根据权利要求10所述的半导体器件的制造装置,其特征在于,所述第一移动单元以及所述第二移动单元通过两者的协同动作来驱动所述第一加热单元以及所述第二加热单元,使得所述第一加热单元和所述第二加热单元之间的间隔距离保持恒定。
12.根据权利要求7所述的半导体器件的制造装置,其特征在于,还包括支撑单元,该支撑单元在所述腔室内支撑被处理物,并使所述被处理物在上下方向上移动。
13.根据权利要求7所述的半导体器件的制造装置,其特征在于,还包括气体导入单元,该气体导入单元向所述腔室内导入还原性气体。
14.根据权利要求13所述的半导体器件的制造装置,其特征在于,所述第一加热单元将向所述处理腔室内导入了还原性气体时的该处理腔室内的环境温度,控制为低于所述凸块的熔融温度且在所述氧化膜的还原开始温度±5℃的范围内。
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Cited By (3)
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Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012009597A (ja) * | 2010-06-24 | 2012-01-12 | Elpida Memory Inc | 半導体デバイスの製造方法および半導体デバイスの製造装置 |
JP5885135B2 (ja) * | 2010-07-23 | 2016-03-15 | アユミ工業株式会社 | 加熱溶融処理方法および加熱溶融処理装置 |
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JP2020150202A (ja) * | 2019-03-15 | 2020-09-17 | キオクシア株式会社 | 半導体装置の製造方法 |
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Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4833301B1 (en) * | 1984-01-18 | 2000-04-04 | Vitronics Corp | Multi-zone thermal process system utilizing non-focused infrared panel emitters |
JPH06164130A (ja) * | 1992-11-18 | 1994-06-10 | Toshiba Corp | プリント基板のリフロー炉 |
JPH07164141A (ja) | 1993-10-22 | 1995-06-27 | Nippon Sanso Kk | はんだ付け方法及び装置 |
US5532612A (en) * | 1994-07-19 | 1996-07-02 | Liang; Louis H. | Methods and apparatus for test and burn-in of integrated circuit devices |
JPH08155675A (ja) * | 1994-11-29 | 1996-06-18 | Sony Corp | はんだバンプ形成用フラックス |
JPH1197448A (ja) * | 1997-09-18 | 1999-04-09 | Kemitoronikusu:Kk | 熱処理装置とこれを用いた半導体結晶の熱処理法 |
JP3397313B2 (ja) | 1999-12-20 | 2003-04-14 | 富士通株式会社 | 半導体装置の製造方法及び電子部品の実装方法 |
JP3404021B2 (ja) | 2001-01-18 | 2003-05-06 | 富士通株式会社 | はんだ接合装置 |
TW570856B (en) * | 2001-01-18 | 2004-01-11 | Fujitsu Ltd | Solder jointing system, solder jointing method, semiconductor device manufacturing method, and semiconductor device manufacturing system |
JP4119740B2 (ja) * | 2002-12-18 | 2008-07-16 | 富士通株式会社 | 半導体装置の製造方法 |
JP4066872B2 (ja) * | 2003-04-22 | 2008-03-26 | セイコーエプソン株式会社 | リフロ−装置及びリフロ−装置の制御方法 |
WO2006087820A1 (ja) * | 2005-02-21 | 2006-08-24 | Fujitsu Limited | リフロー装置およびリフロー方法 |
US20060202001A1 (en) * | 2005-03-08 | 2006-09-14 | International Business Machines Corporation | Enhanced heat system for bga/cga rework |
US7402778B2 (en) * | 2005-04-29 | 2008-07-22 | Asm Assembly Automation Ltd. | Oven for controlled heating of compounds at varying temperatures |
-
2006
- 2006-09-29 WO PCT/JP2006/319586 patent/WO2008050376A1/ja active Application Filing
- 2006-09-29 JP JP2008540798A patent/JP5282571B2/ja active Active
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
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CN103128400A (zh) * | 2011-12-01 | 2013-06-05 | 富士电机株式会社 | 气体发生装置、焊锡接合装置和焊锡接合方法 |
CN103128400B (zh) * | 2011-12-01 | 2015-08-05 | 富士电机株式会社 | 气体发生装置、焊锡接合装置和焊锡接合方法 |
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JP5282571B2 (ja) | 2013-09-04 |
WO2008050376A1 (fr) | 2008-05-02 |
JPWO2008050376A1 (ja) | 2010-02-25 |
US20090184156A1 (en) | 2009-07-23 |
CN101512741B (zh) | 2013-10-16 |
US20120251968A1 (en) | 2012-10-04 |
KR101030764B1 (ko) | 2011-04-27 |
US8302843B2 (en) | 2012-11-06 |
KR20090051765A (ko) | 2009-05-22 |
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