CN101379601B - 用于减少应变硅中的缺陷的基于氮的植入 - Google Patents

用于减少应变硅中的缺陷的基于氮的植入 Download PDF

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CN101379601B
CN101379601B CN200680041561XA CN200680041561A CN101379601B CN 101379601 B CN101379601 B CN 101379601B CN 200680041561X A CN200680041561X A CN 200680041561XA CN 200680041561 A CN200680041561 A CN 200680041561A CN 101379601 B CN101379601 B CN 101379601B
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transistor
semiconductor substrate
strain
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nitrogen
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斯里尼瓦桑·查克拉瓦蒂
P·R·奇丹巴拉姆
拉杰什·哈曼卡
浩文·布
道格拉斯·T·格里德
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Abstract

一种制作于半导体衬底(202)上的晶体管(200)，其中增强或另外调整所述衬底的屈服强度或弹性。在所述晶体管上方形成应变诱发层(236)以对所述晶体管施加应变来改变晶体管的操作特性，且更特定来说增强所述晶体管内载流子的移动性。增强载流子移动性允许晶体管尺寸减小，同时还允许晶体管按需地操作。然而，与制作晶体管相关联的高应变及温度导致有害的塑性变形。因此，通过将氮并入到硅衬底中且更特定来说并入到所述晶体管的源极/漏极延展区域(220、222)及/或源极/漏极区域(228、230)来调整所述衬底的屈服强度。可在晶体管制作期间通过将添加氮作为源极/漏极延展区域形成及/或源极/漏极区域形成的一部分而容易地并入氮。所述衬底的经增强屈服强度减轻晶体管因应变诱发层所致的塑性变形。

Description

用于减少应变硅中的缺陷的基于氮的植入
技术领域
本文的揭示内容大体来说涉及半导体技术，且更特定来说涉及利用氮来调整衬底屈服强度。
背景技术
在半导体工业中存在制造具有更高装置密度的集成电路(IC)的趋势。为实现此目的，已经且继续向着在半导体晶片上按比例缩减尺寸(例如，以亚微米级)而努力。为达到所述高密度，需要更小的特征大小、特征与层之间的更小分离，及/或需更精确的特征形状，举例来说，例如金属互连或引线。集成电路尺寸的按比例缩减可有助于更快的电路性能及/或切换速度，且可通过(举例来说)在半导体电路小片上提供或“封装”更多电路及/或每个半导体晶片提供或“封装”更多电路小片而在IC制作过程中产生更高的有效生产量。
半导体技术中的一种基础建造块是金属氧化物半导体(MOS)晶体管。MOS晶体管通常在半导体衬底12(举例来说，例如硅)(图1)上形成。所述晶体管10通常包含在半导体衬底12内形成的源极14及漏极16区域及在衬底12内的源极14与漏极16之间界定的沟道区域18。栅极结构或叠层20在沟道区域18上方形成。栅极结构20包含栅极电介质或电绝缘材料薄层22及上覆在栅极电介质22上的栅极电极或导电材料层24。侧壁间隔物26驻存在栅极结构20的侧边缘上以有助于与源极14及漏极16区域相关联的延展区域28的间隔。侧壁间隔物26还用于保护栅极结构20的侧壁。沟道区域18具有相关联长度“L”，而晶体管10横断沟道18而延伸的程度称作晶体管宽度“W”。
为激活晶体管10，向栅极电极24施加偏压以使电流在沟道18内流动。可了解到，针对既定偏压产生的电流量是晶体管10的纵横比(W/L)以及沟道18内载流子的移动性的函数。举例来说，当载流子具有较高移动性时，电流可更容易地在沟道18内产生。举例来说，此允许较低偏压(以节约电力)下的更快电路操作。然而，随着减小尺寸来提高封装密度，晶体管宽度“W”及/或沟道长度“L”减小。减小这些尺寸可导致各种性能问题，例如较慢的晶体管操作(例如，降低的切换速度等)。
因此，将需要有助于装置的按比例缩减同时提高载流子移动性的技术。
发明内容
本文的揭示内容涉及增强或另外调整其上形成有晶体管的衬底的屈服强度或弹性。通过将氮并入到所述衬底中且更特定来说并入到所述晶体管的源极/漏极延展区域及/或源极/漏极区域中来调整所述衬底的屈服强度。可在晶体管制作期间通过将添加氮作为源极/漏极延展区域形成及/或源极/漏极区域形成的一部分而容易地将氮并入到所述衬底中。在所述晶体管上方形成应变诱发层在以对所述晶体管施加应变以改变晶体管操作性能，且更特定来说增强所述晶体管内载流子的移动性。增强载流子移动性允许所述晶体管在大小上按比例缩减，同时也允许需要的电流响应于所施加的偏压而产生。衬底的增强的屈服强度减轻所述晶体管因所述应变诱发层所致的塑性变形。
根据本发明的一个或一个以上方面或实施例，揭示一种形成晶体管的方法。所述方法包括调整半导体衬底的屈服强度，在所述半导体衬底上形成所述晶体管及在所述晶体管的一个或一个以上部分内诱发应变。
附图说明
图1是MOS晶体管的透视图。
图2是图解说明根据本文所提供揭示内容的MOS晶体管的形成的截面图。
图3是图解说明根据本文所提供揭示内容的MOS晶体管的形成的另一截面图。
图4以截面图解说明根据本文所提供的揭示内容形成的MOS晶体管。
具体实施方式
将了解，在MOS晶体管的沟道内诱发应变提高载流子移动性，此又增强晶体管操作。因此，本文的揭示内容提供在MOS晶体管上方形成应变诱发材料层。然而，应变诱发层的实施方案可对所述晶体管具有不利作用。举例来说，所述应变诱发层施加到晶体管的应变可超过其上形成有所述晶体管的衬底的屈服强度或弹性。如此，所述衬底可变得塑性变形或遭损伤，导致所述晶体管无法如需地操作(例如，因为源极及漏极区域可能一起“短路”)。因此，本文的揭示内容还提供将氮并入到所述衬底以提高所述衬底的屈服强度。
翻到图2，其图解说明根据本文所提供揭示内容的MOS晶体管200的形成。在半导体衬底202上形成晶体管200且晶体管200包括在衬底202上方形成的栅极结构或门叠层404。将了解，如本文所提及的“衬底”可包含例如半导体晶片或晶片上的一个或一个以上电路小片等任何类型的半导体(例如，硅、SiGe、SOI)以及与其相关联的任何其它类型的半导体及/或外延层。栅极结构204包括栅极电介质206及栅极电极208。通过在衬底202上方形成非导电材料层且在所述非导电材料层上方形成导电材料层来形成栅极结构204。然后，将这些层图案化以分别形成栅极电介质206及栅极电极208。
将了解，可以任何适合方式执行此图案化(如同本文所提及的所有掩模及/或图案化)，举例来说，例如光刻技术，其中光刻法广义上是指将一个或一个以上图案在各种媒介之间转移的过程。在光刻法中，在图案将要转移到的一个或一个以上层上方形成光敏抗蚀剂涂层(未显示)。然后，通过将所述抗蚀剂涂层暴露于(选择性地)透过包含所述图案的介入光刻法掩模的一个或一个以上类型的辐射或光来将所述抗蚀剂涂层图案化。光导致所述抗蚀剂涂层的暴露或未暴露部分变得或多或少地可溶，此取决于所使用抗蚀剂的类型。然后，使用显影剂来移除更可溶的区域，从而留下经图案化的抗蚀剂。然后，所述经图案化的抗蚀剂可用作可选择性地对其加以处置(例如，蚀刻)的下伏层的掩模。
栅极电介质206用其形成的非导电材料层通常包含基于氧化物的材料的薄层。可在存在(举例来说)O2的情况下在(举例来说)约600摄氏度与约1100摄氏度之间的温度下通过任何适合的材料形成过程(举例来说，例如热氧化处理)将此层形成为(举例来说)约10埃与约50埃之间的厚度。栅极电极208用其形成的导电材料层通常包含基于多晶硅的材料。可将此层形成为(举例来说)约800与约5000埃之间的厚度，且此层可包括掺杂剂，例如p型掺杂剂(硼)或n型掺杂剂(例如，磷)，此取决于正形成晶体管的类型。
在形成经图案化栅极结构204的情况下，执行实施方案过程210以在衬底202内在栅极结构204的任一侧上形成源极延展区域220及漏极延展区域222。将了解，可在栅极结构204的各侧上构建偏移间隔物(未显示)以保护所述栅极结构的侧壁并引导植入。仅以实例而非限制的方式，可将具有约1E19到1E21原子/cm3之间的浓度的p型掺杂剂(例如，硼)(针对PMOS晶体管)或具有约1E19到1E21原子/cm3的浓度的n型掺杂剂(例如，磷)(针对NMOS晶体管)植入到(举例来说)约150埃与约350埃之间的深度，以建立延展区域220、222。从而在延展区域220、222之间的衬底202内且在栅极结构204以下界定沟道区域224。将了解，可执行热过程(例如，快速热退火)以激活所述延展区域掺杂剂，从而导致其在门叠层204下方稍微侧向扩散。
还可在源极延展220及漏极延展222区域的形成之前或之后在此接合点处将氮作为源极/漏极延展区域植入过程210的部分或分离的过程植入到衬底202中。举例来说，可分离地将用来建立延展区域220、222的氮气及掺杂剂气体离子化(在同一或不同的离子化室中)，且然后通过分离的离子束将其置入到衬底202中。
然后，在栅极结构204的侧边缘上形成侧壁间隔物226(图3)。侧壁间隔物226包含绝缘材料，例如基于氧化物及/或氮化物的材料。通过以大致保形的方式将所述材料的一个或一个以上层沉积在所述装置上方来形成间隔物226，随后是其各向异性蚀刻，从而将所述间隔物材料从栅极结构204及衬底202的顶部移除，而留下栅极结构204的侧边缘上的区域。所述侧壁间隔物可具有(举例来说)约300埃与约700埃之间的厚度，且从而使后续形成的源极/漏极区域从栅极结构204的横向边缘偏移。
然后，通过植入过程232在衬底202内形成源极228及漏极230区域。仅以实例而非限制的方式，可将具有约1e19与5e21之间的浓度的p型掺杂剂(例如，硼)(针对PMOS晶体管)或具有约1e19与5e21之间的浓度的n型掺杂剂(例如，磷)(针对NMOS晶体管)植入到(举例来说)约300埃与约1500埃之间的深度，以建立源极228及漏极230区域。
替代或除在延展区域220、222形成时将氮并入到衬底202中之外，可在此接合点处将氮添加到衬底202。可作为用于形成源极228及漏极230区域的植入过程232的部分而添加氮。举例来说，可分离地将用于建立源极228及漏极230区域的氮气及掺杂剂气体离子化(在同一或不同的离子化室中)且然后通过分离的离子束将其植入到衬底202中。
无论如何，植入氮使得半导体衬底202中来自所述氮的植入损伤的峰值范围落到半导体衬底202中来自源极228及/或漏极230植入的植入损伤的峰值范围的约四分之一与来自源极228及/或漏极230植入的对所述半导体衬底的损伤的约范围末端(EOR)之间的某处。举例来说，如果在约40keV的能量下植入砷来建立源极228及/或漏极230区域而使得对衬底202的晶格结构的植入损伤的峰值范围在约300埃处出现且所述晶格结构被损伤到约600埃的深度或更确切其具有约600埃的EOR，那么在一能量下植入所述氮，使得来自所述氮的对所述晶格结构的植入损伤的峰值范围落到约300埃的四分之一与约600埃之间或约75埃与约600埃之间的某处。
还以用于形成源极228及/或漏极230区域的剂量的约四分之一与约用于形成源极228及/或漏极230区域的剂量之间的剂量植入所述氮。举例来说，如果使用每平方厘米2E15原子的砷的剂量来形成源极228及/或漏极230区域，那么将以所述量的约四分之一与约所述量之间或每平方厘米约1E15原子与每平方厘米约2E15原子之间的剂量植入所述氮。将了解，所述氮植入可以是可引入氮的任何离子化形式(例如，原子(N)、分子(N2)或其它簇/分子离子)。一旦已形成源极228及漏极230区域及对应的延展区域220、222且已将氮添加到衬底202中，那么视情况通过低热预算过程(例如，等离子增强型化学气相沉积(PECVD))沉积基于氧化物的材料的薄层234(图4)。举例来说，可将氧化物层234沉积到约20埃与约150埃之间的厚度。所述氧化物层通常用作基于氮化物的盖层的后续图案化的蚀刻终止层。
然后，形成应变诱发材料层236。可将所述应变诱发层形成到(举例来说)约100埃与约1000埃之间的厚度，且其可包含任何适合的应变诱发材料，举例来说，例如氧化物、氮化物、氧氮化物、SiC、SiC0、SiCN、SiOCN。将了解，可调节所述应变诱发层的厚度及/或组合物以控制应变诱发层所诱发的应变的量。还可执行退火过程以激活应变诱发层236。以实例的方式，可在约1000摄氏度与约1100摄氏度之间的温度下通过快速热退火(RTA)执行所述退火，及/或在约1100摄氏度与约1300摄氏度之间的温度下(举例来说)用激光及/或闪光灯执行所述退火约一毫秒。
将了解，应变诱发层236通过用于提高晶体管内载流子的移动性而有助于所需的装置操作。还将了解，向晶体管200添加氮用于提高衬底202的弹性或屈服强度，使得所述晶体管不响应于所述应变诱发层所施加的应变且更特定来说不因用于激活所述应变诱发层的退火过程而变形，其中所述退火或加热可降低衬底202的屈服强度。
然后，可执行进一步的处理活动，例如将源极228及/或漏极230区域退火，随后是移除应变诱发层236。在另一实例中，可选择性地将所述应变层从NMOS或PMOS装置蚀刻掉。举例来说，可将层236从PMOS区域蚀刻掉，使得仅NMOS区域具有所述应变层。再次，此后是将源极228及/或漏极230区域退火，随后是将应变诱发层236从所述NMOS装置移除。还可执行硅化物处理，其中在晶体管200上方形成难熔金属材料，随后是热处理，其中金属与硅界面反应以形成硅化物(例如，在栅极结构204的顶部以及在源极228及漏极230区域中)。然后将未反应的金属剥除，以便可形成层间电介质及金属化层。
将了解，出于简化及易于理解的目的，本文所描绘的层及/或元件以相对于彼此的特定尺寸(例如，层与层的尺寸及/或定向)进行图解说明，且元件的实际尺寸可实质不同于本文所图解说明的尺寸。另外，除非另有陈述及/或相反规定，本文所论述的层中的任何一者或一者以上可以任何数量的适合方式来形成，例如通过旋涂技术、溅射技术(例如，磁控溅射及/或离子束溅射)、(热)生长技术及/或沉积技术(举例来说，例如化学气相沉积(CVD)、物理气相沉积(PVD)及/或等离子增强型化学气相沉积(PECVD)或原子层沉积(ALD))，且可以任何适合方式(除非另外明确指示)图案化，举例来说，例如通过蚀刻及/或光刻技术。
本发明所属领域的技术人员将了解，可在不背离所请求本发明的范围的情况下对所阐述的实例性实施例及所实施的其它实施例做出各种修改。

Claims (4)

1.一种形成晶体管的方法，其包含：
调整半导体衬底的屈服强度，其中调整所述屈服强度包括将氮植入到所述半导体衬底中；
在所述半导体衬底上形成所述晶体管；及
在所述晶体管的一个或一个以上部分内诱发应变，其中诱发应变包括在所述晶体管上形成应变诱发层和将所述应变诱发层退火，其中，以下操作中的至少一者来执行所述退火：
在介于1000摄氏度与1100摄氏度之间的温度下执行的快速热退火；及
在介于1100摄氏度与1300摄氏度之间的温度下执行一毫秒的激光或闪光灯退火。
2.一种形成晶体管的方法，其包含：
调整半导体衬底的屈服强度，其中调整所述屈服强度包含当形成所述晶体管的源极/漏极延展区域及所述晶体管的源极/漏极区域中的至少一者时将氮植入到所述半导体衬底中；
在所述半导体衬底上形成所述晶体管；及
在所述晶体管的一个或一个以上部分内诱发应变，其中诱发应变包括在所述晶体管上形成应变诱发层和将所述应变诱发层退火，其中以下中的至少一者发生：
植入所述氮以使得所述半导体衬底中来自所述氮的植入损伤的峰值范围介于所述半导体衬底中来自源极及/或漏极掺杂剂的植入损伤的峰值范围的四分之一与来自源极及/或漏极掺杂剂的对所述半导体衬底的损伤的范围末端(EOR)之间，及
以介于所述源极及/或漏极掺杂剂的剂量的四分之一与所述源极及/或漏极掺杂剂的剂量之间的剂量来植入所述氮。
3.如权利要求2所述的方法，其中，以介于5×1014每平方厘米与5×1015每平方厘米的剂量植入所述氮。
4.一种形成晶体管的方法，其包含：
在半导体衬底上形成栅极结构；
在所述半导体衬底中形成源极/漏极延展区域，在所述半导体衬底中沟道区域将所述源极延展区域和所述漏极延展区域分开，其中所述栅极结构上覆所述沟道区域；
在所述半导体衬底中加入氮；
在所述半导体衬底中形成源极/漏极植入区域；
在所述源极/漏极植入区域及所述栅极结构上方形成应变诱发层；及将所述应变诱发层退火。
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