JP5379489B2 - 歪みシリコンにおける欠陥低減のための窒素ベース注入物 - Google Patents
歪みシリコンにおける欠陥低減のための窒素ベース注入物 Download PDFInfo
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- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 title claims description 83
- 229910052757 nitrogen Inorganic materials 0.000 title claims description 40
- 239000007943 implant Substances 0.000 title description 5
- 229910052710 silicon Inorganic materials 0.000 title description 5
- 239000010703 silicon Substances 0.000 title description 5
- 230000007547 defect Effects 0.000 title 1
- 239000000758 substrate Substances 0.000 claims description 67
- 238000000034 method Methods 0.000 claims description 51
- 239000004065 semiconductor Substances 0.000 claims description 46
- 230000001939 inductive effect Effects 0.000 claims description 37
- 238000000137 annealing Methods 0.000 claims description 18
- 238000002513 implantation Methods 0.000 claims description 16
- 239000002019 doping agent Substances 0.000 claims description 15
- 230000015572 biosynthetic process Effects 0.000 claims description 9
- 150000004767 nitrides Chemical class 0.000 claims description 5
- 238000004151 rapid thermal annealing Methods 0.000 claims description 5
- 239000000463 material Substances 0.000 description 13
- 230000008569 process Effects 0.000 description 13
- 125000006850 spacer group Chemical group 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 230000001965 increasing effect Effects 0.000 description 3
- 230000006698 induction Effects 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 239000012811 non-conductive material Substances 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000010884 ion-beam technique Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 150000001793 charged compounds Chemical class 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000002939 deleterious effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 239000012777 electrically insulating material Substances 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000001659 ion-beam spectroscopy Methods 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
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Description
(1)トランジスタを含む半導体デバイスの形成方法であって、
半導体基板の降伏強さを適合させる段階と、
前記半導体基板上にトランジスタを形成する段階と、
前記トランジスタの1つ又はそれ以上の部分内に歪みを誘起することにより歪み誘起層を形成する段階と、
を含む方法。
前記降伏強さを適合させる段階が、前記ソース/ドレイン延長領域の少なくとも1つ及び前記ソース/ドレイン領域が注入されたときに、前記基板に窒素を注入する段階を含み、
前記歪みを誘起する段階が、前記トランジスタを覆って歪み誘起層を形成する段階を含む、
ことを特徴とする上記(1)に記載の方法。
ことを特徴とする上記(2)に記載の方法。
ことを特徴とする上記(2)に記載の方法。
ことを特徴とする上記(2)、(3)、又は(4)に記載の方法。
ことを特徴とする上記(2)、(3)、又は(4)に記載の方法。
ことを特徴とする上記(6)に記載の方法。
a)約1000℃から約1100℃までの温度で行われる急速熱アニールと、
b)約1ミリ秒で約1100℃から約1300℃までの温度で行われるレーザ及び/又はフラッシュランプアニールと、
のうちの少なくとも1つにより実施される、
ことを特徴とする上記(6)に記載の方法。
ゲート誘電体とゲート電極とを含むゲート構造体を半導体基板上に形成する段階と、
前記基板内にソース/ドレイン延長領域を形成して、前記延長領域の間及び前記ゲート構造体の下にチャネル領域を定める段階と、
前記基板内に窒素を注入する段階と、
前記基板内にソース/ドレイン注入領域を形成する段階と、
前記ソース/ドレイン領域及び前記ゲート構造体を覆って歪み誘起層を形成する段階と、
前記歪み誘起層をアニーリングする段階と、
を含む方法。
ことを特徴とする上記(9)に記載の方法。
半導体基板内に形成されたソース領域と、
前記半導体基板内に形成され、前記基板内でチャネル領域によって前記ソース領域と分離されているドレイン領域と、
前記チャネル領域を覆って形成されたゲート構造体と、
前記トランジスタ内に歪みを誘起するために前記ソース領域と前記ドレイン領域と前記ゲート構造体とを覆って形成された歪み誘起層と、
を含み、
前記ソース及びドレイン領域が前記基板の降伏強さを高めるために窒素を含む、
ことを特徴とする半導体デバイス。
202 半導体基板
220 ソース延長領域
222 ドレイン延長領域
228 ソース領域
230 ドレイン領域
236 歪み誘起層
Claims (11)
- トランジスタを含む半導体デバイスの形成方法であって、
半導体基板に窒素を注入する段階と、
前記半導体基板上にトランジスタを形成する段階であって、ソース/ドレイン領域の形成のために前記半導体基板にドーパントを注入し、前記半導体基板をアニーリングする段階を含み、窒素を注入する段階が、前記ドーパントを注入する間又は後であって、前記半導体基板をアニーリングする前に行われる、段階と、
窒素が注入された半導体基板上に歪み誘起層を形成することにより、前記トランジスタの1つ又はそれ以上の部分内に歪みを誘起する段階と、
を含む方法。 - 請求項1に記載の方法であって、
前記歪み誘起層が、窒化物、酸化物、酸窒化物、SiC、SiCO、SiCN、及びSiOCNのうちの少なくとも1つを含む、方法。 - 請求項1に記載の方法であって、
前記歪みを誘起する段階が、前記歪み誘起層をアニーリングする段階を更に含む、方法。 - 請求項1乃至3の何れかに記載の方法であって、
前記歪み誘起層を形成する段階の前に、前記トランジスタ上に酸化物層を形成する段階を更に含む、方法。 - 請求項1に記載の方法であって、
前記アニーリングが、1000℃から1100℃までの間の温度で急速熱アニールで行われる、方法。 - 請求項1に記載の方法であって、
前記アニーリングが、1ミリ秒の間1100℃から1300℃までの間の温度でレーザ又はフラッシュランプアニールで行われる、方法。 - 請求項1に記載の方法であって、
前記歪み誘起層が、100オングストロームから1000オングストロームまでの間の厚みに形成される、方法。 - 請求項1又は7に記載の方法であって、
前記窒素注入が、原子状窒素(N)と分子状窒素(N2)の少なくとも1つを含む、方法。 - 請求項1に記載の方法であって、
半導体基板にドーパントを注入する段階が損傷された領域を生成し、注入された窒素からの注入損傷のピーク範囲が前記損傷された領域内に閉じ込められる、方法。 - トランジスタを形成する方法であって、
ゲート構造を半導体基板上に形成する段階と、
ソース/ドレイン領域の形成のために前記半導体基板にドーパントを注入する段階であって、前記半導体基板内に損傷された領域を生成する、段階と、
前記損傷された領域に窒素を注入する段階であって、窒素のピーク範囲が前記損傷された領域内である、段階と、
前記ゲート構造及び前記ソース/ドレイン領域上に歪み誘起層を形成する段階と、
前記半導体基板をアニーリングする段階と、
を含み、
窒素を注入する段階が、前記ドーパントを注入する後であって、前記半導体基板をアニーリングする前に行われる、
方法。 - 請求項10に記載の方法に従って形成されたトランジスタを有する、半導体デバイス。
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Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/268,040 | 2005-11-07 | ||
US11/268,040 US7670892B2 (en) | 2005-11-07 | 2005-11-07 | Nitrogen based implants for defect reduction in strained silicon |
PCT/US2006/060524 WO2007056689A2 (en) | 2005-11-07 | 2006-11-03 | Nitrogen based implants for defect reduction in strained silicon |
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JP2009515345A JP2009515345A (ja) | 2009-04-09 |
JP5379489B2 true JP5379489B2 (ja) | 2013-12-25 |
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JP2008539164A Active JP5379489B2 (ja) | 2005-11-07 | 2006-11-03 | 歪みシリコンにおける欠陥低減のための窒素ベース注入物 |
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US (2) | US7670892B2 (ja) |
EP (1) | EP1955372B1 (ja) |
JP (1) | JP5379489B2 (ja) |
KR (1) | KR101050602B1 (ja) |
CN (1) | CN101379601B (ja) |
WO (1) | WO2007056689A2 (ja) |
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Publication number | Priority date | Publication date | Assignee | Title |
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US7670892B2 (en) * | 2005-11-07 | 2010-03-02 | Texas Instruments Incorporated | Nitrogen based implants for defect reduction in strained silicon |
US20070298623A1 (en) * | 2006-06-26 | 2007-12-27 | Spencer Gregory S | Method for straining a semiconductor device |
US20090050980A1 (en) * | 2007-08-21 | 2009-02-26 | Texas Instruments Incorporated | Method of forming a semiconductor device with source/drain nitrogen implant, and related device |
US8124487B2 (en) * | 2008-12-22 | 2012-02-28 | Varian Semiconductor Equipment Associates, Inc. | Method for enhancing tensile stress and source/drain activation using Si:C |
US8252649B2 (en) | 2008-12-22 | 2012-08-28 | Infineon Technologies Ag | Methods of fabricating semiconductor devices and structures thereof |
US8236709B2 (en) | 2009-07-29 | 2012-08-07 | International Business Machines Corporation | Method of fabricating a device using low temperature anneal processes, a device and design structure |
CN102468162B (zh) * | 2010-10-29 | 2014-03-12 | 中芯国际集成电路制造(北京)有限公司 | Nmos晶体管的制作方法 |
US9741853B2 (en) | 2015-10-29 | 2017-08-22 | Globalfoundries Inc. | Stress memorization techniques for transistor devices |
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US5413949A (en) * | 1994-04-26 | 1995-05-09 | United Microelectronics Corporation | Method of making self-aligned MOSFET |
JPH09181305A (ja) * | 1995-12-21 | 1997-07-11 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
US5792699A (en) * | 1996-06-03 | 1998-08-11 | Industrial Technology Research Institute | Method for reduction of reverse short channel effect in MOSFET |
JP3949211B2 (ja) | 1997-03-06 | 2007-07-25 | 富士通株式会社 | 半導体装置の製造方法 |
US5885861A (en) | 1997-05-30 | 1999-03-23 | Advanced Micro Devices, Inc. | Reduction of dopant diffusion by the co-implantation of impurities into the transistor gate conductor |
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KR100288686B1 (ko) | 1999-04-13 | 2001-04-16 | 황인길 | 반도체 소자 제조 방법 |
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US7335545B2 (en) * | 2002-06-07 | 2008-02-26 | Amberwave Systems Corporation | Control of strain in device layers by prevention of relaxation |
US7307273B2 (en) * | 2002-06-07 | 2007-12-11 | Amberwave Systems Corporation | Control of strain in device layers by selective relaxation |
US6800887B1 (en) | 2003-03-31 | 2004-10-05 | Intel Corporation | Nitrogen controlled growth of dislocation loop in stress enhanced transistor |
US20050059260A1 (en) * | 2003-09-15 | 2005-03-17 | Haowen Bu | CMOS transistors and methods of forming same |
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US20050116360A1 (en) | 2003-12-01 | 2005-06-02 | Chien-Chao Huang | Complementary field-effect transistors and methods of manufacture |
US7670892B2 (en) * | 2005-11-07 | 2010-03-02 | Texas Instruments Incorporated | Nitrogen based implants for defect reduction in strained silicon |
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US8084312B2 (en) | 2011-12-27 |
JP2009515345A (ja) | 2009-04-09 |
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KR101050602B1 (ko) | 2011-07-19 |
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EP1955372A2 (en) | 2008-08-13 |
EP1955372A4 (en) | 2009-07-22 |
WO2007056689A2 (en) | 2007-05-18 |
US7670892B2 (en) | 2010-03-02 |
EP1955372B1 (en) | 2018-06-27 |
CN101379601B (zh) | 2013-01-16 |
US20070105294A1 (en) | 2007-05-10 |
US20100120215A1 (en) | 2010-05-13 |
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