KR100796825B1 - 반도체 디바이스 제조 방법 - Google Patents
반도체 디바이스 제조 방법 Download PDFInfo
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- KR100796825B1 KR100796825B1 KR1020017015928A KR20017015928A KR100796825B1 KR 100796825 B1 KR100796825 B1 KR 100796825B1 KR 1020017015928 A KR1020017015928 A KR 1020017015928A KR 20017015928 A KR20017015928 A KR 20017015928A KR 100796825 B1 KR100796825 B1 KR 100796825B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 239000007943 implant Substances 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 230000004913 activation Effects 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 3
- 230000003213 activating effect Effects 0.000 claims description 2
- 238000002513 implantation Methods 0.000 description 11
- 238000000137 annealing Methods 0.000 description 8
- 239000002019 doping agent Substances 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229910052785 arsenic Inorganic materials 0.000 description 4
- 230000002411 adverse Effects 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 125000001475 halogen functional group Chemical group 0.000 description 3
- 238000001459 lithography Methods 0.000 description 3
- 230000000873 masking effect Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- -1 arsenic ions Chemical class 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 230000035515 penetration Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910001439 antimony ion Inorganic materials 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910001449 indium ion Inorganic materials 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
Abstract
Description
Claims (6)
- PMOS 트랜지스터 및 NMOS 트랜지스터를 포함하는 반도체 디바이스를 제조하는 방법에 있어서,(a) 상기 NMOS 트랜지스터가 제공될 P 웰 영역(a P-well region) 및 상기 PMOS 트랜지스터가 제공될 N 웰 영역을 가지는 반도체 기판을 제공하는 단계와,(b) 상기 P 웰 영역 및 상기 N 웰 영역 상에 게이트 전극(gate electrodes)을 형성하는 단계와,(c) 상기 P 웰 영역 또는 상기 N 웰 영역 중 어느 한 영역을 피복하는 하드 마스크(a hard mask)를 도포하는 단계와,(d) 상기 하드 마스크에 의해서 피복되지 않은 영역 내에 소스(a source) 및 드레인(a drain)을 주입하고, 이어서 열 활성화(heat activation)하는 단계와,(e) 상기 하드 마스크에 의해서 피복되지 않은 영역 내에만 포켓 주입물(pocket implants)을 주입하고, 이어서 열 활성화하는 단계와,(f) 상기 하드 마스크를 제거하는 단계를 포함하는 반도체 디바이스 제조 방법.
- 제 1 항에 있어서,상기 하드 마스크의 도포에 앞서, 유전층이 도포되어 상기 반도체 기판 및 상기 게이트 전극을 피복하는 반도체 디바이스 제조 방법.
- 제 1 항 또는 제 2 항에 있어서,상기 단계 (c)는 하드 마스크층을 도포하며, 상기 하드 마스크층을 레지스트층으로 피복하고, 상기 레지스트층을 패터닝하며, 상기 패터닝된 레지스트층을 상기 하드 마스크층을 패터닝하기 위한 마스크로 이용하여 상기 하드 마스크를 형성함으로써 이루어지는 반도체 디바이스 제조 방법.
- 제 1 항 또는 제 2 항에 있어서,상기 하드 마스크는 적어도 0.05 마이크론의 두께로 도포되는 반도체 디바이스 제조 방법.
- 제 4 항에 있어서,상기 하드 마스크는 0.25 마이크론보다 작은 두께로 도포되는 반도체 디바이스 제조 방법.
- 제 1 항 또는 제 2 항에 있어서,상기 도포되는 하드 마스크는 Ge 도핑된 실리콘(Ge-doped silicon), Si 리치 SiN(Si-rich SiN) 또는 다결정 Ge(polycrystalline Ge)를 포함하는 반도체 디바이스 제조 방법.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP00201317 | 2000-04-12 | ||
EP00201317.5 | 2000-04-12 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20020025892A KR20020025892A (ko) | 2002-04-04 |
KR100796825B1 true KR100796825B1 (ko) | 2008-01-22 |
Family
ID=8171339
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020017015928A KR100796825B1 (ko) | 2000-04-12 | 2001-04-03 | 반도체 디바이스 제조 방법 |
Country Status (8)
Country | Link |
---|---|
US (1) | US6461908B2 (ko) |
EP (1) | EP1275147B1 (ko) |
JP (1) | JP4846167B2 (ko) |
KR (1) | KR100796825B1 (ko) |
AT (1) | ATE434831T1 (ko) |
DE (1) | DE60139068D1 (ko) |
TW (1) | TW533482B (ko) |
WO (1) | WO2001080310A1 (ko) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6784062B2 (en) * | 2002-06-03 | 2004-08-31 | Micron Technology, Inc. | Transistor formation for semiconductor devices |
JP3730947B2 (ja) * | 2002-10-08 | 2006-01-05 | 松下電器産業株式会社 | 半導体装置の製造方法 |
EP1730596B1 (en) * | 2004-03-30 | 2011-02-16 | Carl Zeiss SMT AG | Projection objective and projection exposure apparatus |
US8212988B2 (en) * | 2004-08-06 | 2012-07-03 | Carl Zeiss GmbH | Projection objective for microlithography |
US7511890B2 (en) * | 2005-02-04 | 2009-03-31 | Carl Zeiss Smt Ag | Refractive optical imaging system, in particular projection objective for microlithography |
US7704865B2 (en) * | 2005-08-23 | 2010-04-27 | Macronix International Co., Ltd. | Methods of forming charge-trapping dielectric layers for semiconductor memory devices |
US9679602B2 (en) | 2006-06-14 | 2017-06-13 | Seagate Technology Llc | Disc drive circuitry swap |
KR100779395B1 (ko) * | 2006-08-31 | 2007-11-23 | 동부일렉트로닉스 주식회사 | 반도체소자 및 그 제조방법 |
US9305590B2 (en) | 2007-10-16 | 2016-04-05 | Seagate Technology Llc | Prevent data storage device circuitry swap |
US20100330756A1 (en) * | 2009-06-25 | 2010-12-30 | International Business Machines Corporation | Integrated circuit structure manufacturing methods using hard mask and photoresist combination |
US8877596B2 (en) | 2010-06-24 | 2014-11-04 | International Business Machines Corporation | Semiconductor devices with asymmetric halo implantation and method of manufacture |
DE102010063782B4 (de) * | 2010-12-21 | 2016-12-15 | Globalfoundries Dresden Module One Limited Liability Company & Co. Kg | Verfahren zur Herstellung von Transistoren mit Metallgatestapeln mit großem ε und einem eingebetteten Verspannungsmaterial |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5904520A (en) * | 1998-01-05 | 1999-05-18 | Utek Semiconductor Corp. | Method of fabricating a CMOS transistor |
US5930615A (en) * | 1995-11-27 | 1999-07-27 | Micron Technology, Inc. | Method of forming CMOS having simultaneous formation of halo regions of PMOS and part of source/drain of NMOS |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5513953A (en) * | 1978-07-18 | 1980-01-31 | Fujitsu Ltd | Complementary integrated circuit |
JPS5651872A (en) * | 1979-10-05 | 1981-05-09 | Oki Electric Ind Co Ltd | Manufacture of complementary type mos transistor |
JPH01145849A (ja) * | 1987-12-01 | 1989-06-07 | Fujitsu Ltd | 半導体装置の製造方法 |
JPH029164A (ja) * | 1988-06-28 | 1990-01-12 | Matsushita Electric Ind Co Ltd | パターン形成方法および半導体装置の製造方法 |
JPH02162739A (ja) * | 1988-12-15 | 1990-06-22 | Fujitsu Ltd | 半導体装置の製造方法 |
US5227321A (en) * | 1990-07-05 | 1993-07-13 | Micron Technology, Inc. | Method for forming MOS transistors |
JP2917696B2 (ja) * | 1992-08-22 | 1999-07-12 | 日本電気株式会社 | Cmos半導体装置の製造方法 |
JP3062398B2 (ja) * | 1993-06-25 | 2000-07-10 | 松下電器産業株式会社 | Cmos半導体装置の製造方法 |
US5292681A (en) * | 1993-09-16 | 1994-03-08 | Micron Semiconductor, Inc. | Method of processing a semiconductor wafer to form an array of nonvolatile memory devices employing floating gate transistors and peripheral area having CMOS transistors |
US5489546A (en) * | 1995-05-24 | 1996-02-06 | Micron Technology, Inc. | Method of forming CMOS devices using independent thickness spacers in a split-polysilicon DRAM process |
US6004854A (en) * | 1995-07-17 | 1999-12-21 | Micron Technology, Inc. | Method of forming CMOS integrated circuitry |
JPH09205151A (ja) * | 1996-01-26 | 1997-08-05 | Sony Corp | 相補型半導体装置の製造方法 |
JP2980057B2 (ja) * | 1997-04-30 | 1999-11-22 | 日本電気株式会社 | 半導体装置の製造方法 |
US6187619B1 (en) * | 1998-02-17 | 2001-02-13 | Shye-Lin Wu | Method to fabricate short-channel MOSFETs with an improvement in ESD resistance |
US5920774A (en) * | 1998-02-17 | 1999-07-06 | Texas Instruments - Acer Incorporate | Method to fabricate short-channel MOSFETS with an improvement in ESD resistance |
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2001
- 2001-04-03 JP JP2001577605A patent/JP4846167B2/ja not_active Expired - Fee Related
- 2001-04-03 AT AT01938077T patent/ATE434831T1/de not_active IP Right Cessation
- 2001-04-03 EP EP01938077A patent/EP1275147B1/en not_active Expired - Lifetime
- 2001-04-03 DE DE60139068T patent/DE60139068D1/de not_active Expired - Lifetime
- 2001-04-03 WO PCT/EP2001/003749 patent/WO2001080310A1/en active Application Filing
- 2001-04-03 KR KR1020017015928A patent/KR100796825B1/ko not_active IP Right Cessation
- 2001-04-10 US US09/829,796 patent/US6461908B2/en not_active Expired - Lifetime
- 2001-04-19 TW TW090109425A patent/TW533482B/zh active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5930615A (en) * | 1995-11-27 | 1999-07-27 | Micron Technology, Inc. | Method of forming CMOS having simultaneous formation of halo regions of PMOS and part of source/drain of NMOS |
US5904520A (en) * | 1998-01-05 | 1999-05-18 | Utek Semiconductor Corp. | Method of fabricating a CMOS transistor |
Also Published As
Publication number | Publication date |
---|---|
WO2001080310A1 (en) | 2001-10-25 |
EP1275147A1 (en) | 2003-01-15 |
DE60139068D1 (de) | 2009-08-06 |
ATE434831T1 (de) | 2009-07-15 |
US6461908B2 (en) | 2002-10-08 |
US20010031522A1 (en) | 2001-10-18 |
JP2003531494A (ja) | 2003-10-21 |
JP4846167B2 (ja) | 2011-12-28 |
EP1275147B1 (en) | 2009-06-24 |
TW533482B (en) | 2003-05-21 |
KR20020025892A (ko) | 2002-04-04 |
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