JPS5651872A - Manufacture of complementary type mos transistor - Google Patents
Manufacture of complementary type mos transistorInfo
- Publication number
- JPS5651872A JPS5651872A JP12803279A JP12803279A JPS5651872A JP S5651872 A JPS5651872 A JP S5651872A JP 12803279 A JP12803279 A JP 12803279A JP 12803279 A JP12803279 A JP 12803279A JP S5651872 A JPS5651872 A JP S5651872A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- region
- type
- film
- films
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Weting (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
PURPOSE:To obtain a high-concentration diffusion region without causing any influence on the others by providing a PSG film prescribing for mole ratio on the surface of a substrate when forming the source and the drain regions of a transistor by diffusion wherein a selective etching is applied to the PSG film by using a hydrofluoric aqueous solution prescribing for composition. CONSTITUTION:A P<-> type region is formed by diffusion on the predetermined region of an N type substrate 7. Thick field oxide films 8 are formed by locating around the circumference of the substrate 7 and on borders between the P<-> type region and the substrate. A gate oxide films 11 with predetermined shape are provided on the surface of the substrate 7 surrounded by the films 8 and poly- crystalline layers 10 are formed on the films 11. Next, a low temperature PSG film 9 having 0.1-0.3 (PH3/SiH4) by mole ratio is formed on the whole surface and the removal of etching is applied to an NMOS transistor formation section by a hydrofluoric aqueous solution of 0.1-0.5%. Then, the remaining film 9 is used as a mask and an N<+> type source region and drain region 13 are formed in the P<-> type region by ion implantation. P<+> type region 14 is formed in the substrate 7 by renewing the film 9.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12803279A JPS5651872A (en) | 1979-10-05 | 1979-10-05 | Manufacture of complementary type mos transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12803279A JPS5651872A (en) | 1979-10-05 | 1979-10-05 | Manufacture of complementary type mos transistor |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5651872A true JPS5651872A (en) | 1981-05-09 |
JPS6152576B2 JPS6152576B2 (en) | 1986-11-13 |
Family
ID=14974816
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12803279A Granted JPS5651872A (en) | 1979-10-05 | 1979-10-05 | Manufacture of complementary type mos transistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5651872A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003531494A (en) * | 2000-04-12 | 2003-10-21 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Method for manufacturing semiconductor device |
-
1979
- 1979-10-05 JP JP12803279A patent/JPS5651872A/en active Granted
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003531494A (en) * | 2000-04-12 | 2003-10-21 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Method for manufacturing semiconductor device |
JP4846167B2 (en) * | 2000-04-12 | 2011-12-28 | エヌエックスピー ビー ヴィ | Manufacturing method of semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
JPS6152576B2 (en) | 1986-11-13 |
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