JPH01253958A - Manufacture of mask rom - Google Patents

Abstract

PURPOSE:To eliminate a process specially for programming by a method wherein a diffused layer is formed under the gate of an MOS transistor which constitutes a memory part simultaneously when the source and drain layers of another MOS transistor whose conductivity type is opposite to that of the former are formed. CONSTITUTION:After a p-type implanted layer 13 is formed near the gate of an NMOS transistor simultaneously when p-type source and drain implanted layers 12 of a PMOS transistor are formed, the p-type implanted layer 13 is extended as far as a channel part under the gate by diffusion so as to form an extended p-type diffused layer 13a. Therefore, it is not necessary to form a new resist layer and a threshold voltage can be elevated. With this constitution, a process specially for programming can be eliminated so that the increase of the number of processes can be avoided.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a mask ROM in which programming is performed during the manufacturing process.

[Conventional technology]

FIG. 2(a) shows a conventional method used in the mask ROM programming process.

There is a method of increasing the threshold voltage of a desired transistor by ion implantation as shown in (b).

The conventional method will be explained below with reference to FIGS. 2(a) and 2(b).

In these figures, 21 is a p-type single crystal Si substrate;
2 is an oxide film, 23 is an n-type source/drain layer, 24 is a gate oxide film, 25 is a gate electrode, 26 is a resist film, 2
7 is an injection layer.

First, as shown in FIG. 2(a), a thick oxide film 22 for local isolation is formed on a p-type nested crystal Si substrate 21, and then a gate oxide film 24 and a gate formed by a polycrystalline silicon film are formed. Electrodes 25 are formed and processed into a desired pattern.

Next, arsenic or phosphorus is ion-implanted to form an n-type source/drain layer 23, thereby forming an NMO3 transistor that will become a memory cell of the mask ROM.

After that, as shown in FIG. 2(b), the resist film 26
is coated and patterned to open a desired transistor portion in the memory cell, and then boron ions are accelerated to a predetermined energy and implanted to form an implantation layer 27.
Boron concentration is increased in the channel portion under the gate as well as in the n-type source/drain layer 23.

In other words, by doing this, a higher threshold voltage can be obtained compared to the NMO3I-transistor without boron implantation, so if the operating voltage is set to the intermediate potential of the difference, the implanted NMO3I-transistor and the implanted NMO3I-transistor can be As a result, the output of the NMO3I-transistor that was not
It is divided into "High" and "Low" and operates as a ROM.

[Problem to be solved by the invention]

In the conventional mask ROM manufacturing method as described above, an arbitrary one is selected from among the MOS transistors constituting the memory cell and its threshold voltage is increased. The steps shown in Figure 2(b) were necessary. That is, in the manufacturing process, a mask for photolithography and an ion implantation process are required just for programming, resulting in an increase in the number of steps.

The present invention was made to solve this problem, and an object of the present invention is to provide a method for manufacturing a mask ROM that allows programming without increasing the number of conventional process steps.

[Means to solve the problem]

A method for manufacturing a mask ROM according to the present invention includes a method for manufacturing a mask ROM using a MOS transistor of a conductivity type opposite to that of a MOS transistor constituting a storage section.
When forming the source and drain layers of the I-transistor,
Programming is performed by selectively forming a diffusion layer under the gate of the MO3 transistor constituting the memory section.

[Effect]

In this invention, when forming the source/drain layer of the MO8 transistor of the opposite conductivity type to the MOS transistor forming the storage section, at the same time, the MOS transistor forming the storage section is formed.
A diffusion layer is formed under the gate of the three transistors, and programming is performed by changing the threshold voltage.

〔Example〕

FIGS. 1(a) to 1(d) are cross-sectional views for explaining one embodiment of the method for manufacturing a mask ROM of the present invention. Here, a mask using an NMOS transistor as a memory cell and an 0M03 circuit as a peripheral circuit is shown. Indicates about ROM,
It is.

In these figures, 1 is a p-type nested crystal Si substrate, 2 is a thick oxide film for isolation, 3 is an n-type well, 4 is a D1 to oxide film, 5 is a gate electrode of a PMOS transistor in the CMO8 circuit section, 6 is NMO3I in the CMO3 circuit section
- Gate electrode of the transistor, 7 is the gate electrode of the NMO3 transistor in the storage section, 8 is p for channel cut
type diffusion layer, 9 is the first photoresist injection layer, 10a is the n-type source/drain layer, 11 is the second photoresist l-112 is the p-type source/drain a
12a is a p-type source/drain layer, 13 is a p-type injection layer, and 13a is a p-type diffusion layer.

Next, the manufacturing process of this invention will be explained with reference to FIGS. 1(a) to 1(d).

First, as shown in FIG. 1(a), the p-type nested crystal S! Oxide film 2 on substrate 1. n-type well 3. Gate oxidation gii4. Gate electrode 526p 7p P-type diffusion layer 8 is formed.

Next, as shown in FIG. 1(b), the first photoresist 9 is patterned to protect only the PMO3 transistor section, and arsenic is ion-implanted to form the NMO3 transistor.
3 transistor part, n-type source/drain injection layer 10
form.

Next, as shown in FIG. 1C, after removing the first photoresist 9 and applying a second photoresist 11, for example, the source of the PMO8 transistor section and the NMO8 transistor of the storage section is removed. The hole is patterned to extend from the side to a part of the gate electrode.

After this, boron is implanted to form a p-type implantation layer 13 on a part of the source side of the NMO3 transistor in the storage section at the same time as the p-type source/drain implantation layer 12 which is to become the p-type source/drain of the PMOS transistor. .

Then, as shown in FIG. 1(d), by processing a second photoresist, the n-type source/drain diffusion layer 10a is
Then, a p-type source/drain diffusion layer 12a is formed. At this time, the p-type implantation layer 13 implanted on the source side of the NMOS transistor in the storage section is also diffused. At this time, arsenic is used as an impurity for n-type, and boron is used as an impurity for p-type, and due to the difference in their diffusion coefficients, boron forms a diffusion layer deeper than arsenic and also wider in the lateral direction. Therefore, NMOS1. A high concentration p-type diffusion layer 13a is formed in a part of the channel section under the gate of the transistor. Therefore, the threshold voltage of NMOS1 to transistor becomes high and operates as a memory cell in which "IILow" is written.

That is, in the mask ROM manufacturing method of this embodiment,
Simultaneously with the formation of the p-type source/drain/in injection layer 12 of the PMOS transistor, a p-type injection layer 13 is formed near the gate of the NMOS transistor, and then by diffusion, the p-type is injected into the channel region under the gate. Diffusion layer 13a
There is no need to form a new resist, and it is possible to increase the threshold voltage using only the resist used in normal manufacturing procedures. It is now possible to form the p-type source/drain injection layer 12 and the p-type injection layer 13.

In the above embodiment, the p-type diffusion layer 13a is extended below the gate by utilizing the difference in the diffusion coefficients of boron and arsenic, which are impurities for determining the p-type and n-type conductivity types, to form an NMOSI-transistor. Although the threshold voltage of
It is also possible to use impurities other than boron and arsenic as long as the combination is such that the diffusion coefficient of the p-type impurity is sufficiently larger than the diffusion coefficient of the n-type impurity.

To increase the threshold voltage of a PMOS transistor, conversely, use a combination of impurities in which the diffusion coefficient of n-type impurities is sufficiently larger than that of p-type impurities, and follow the same procedure. The n-type diffusion layer may be extended to below the gate, and the same effect as in the above embodiment can be obtained in this case as well.

〔Effect of the invention〕

As explained above, the present invention provides MO
When forming the source/drain layers of the MOSl-transistor of the conductivity type opposite to the S transistor, a diffusion layer is selectively formed under the gate of the MOSl-transistor constituting the memory section for programming. There is no need for a special photolithography process or ion implantation process for programming, and it is only necessary to change the photoresist for forming the source/drain diffusion layer, so there is no increase in the number of processes and manufacturing time can be shortened. This also has the effect of reducing costs.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view for explaining an embodiment of the method for manufacturing a mask ROM of the present invention, and FIG. 2 is a cross-sectional view for explaining a conventional programming method for a mask ROM. In the figure, 1 is a p-type wheel crystal 81 substrate, 2 is a thick oxide film for isolation, 3 is an n-type well, 4 is a gate 1, oxide film, and 5 is a PMOS+ in the CMOS circuit section. Gate electrode of transistor, 6 is gate electrode of NMOS transistor in CMOS circuit section, 7 is NM of memory section
The gate electrode of the OS transistor, 8 is a p-type diffusion layer for channel cut, and 9 is the first photoresist! ,,10
10a is an n-type source/drain injection layer, and 10a is an n-type source/drain injection layer.
a drain layer; 11 is a second photoresist injection layer; 12a is a p-type source/drain layer; 13
13a is a p-type injection layer, and 13a is a p-type diffusion layer. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] In a method for manufacturing a mask ROM in which a storage section is a MOS transistor and a peripheral circuit section is a CMOS transistor circuit, when forming source/drain layers of a MOS transistor of a conductivity type opposite to that of the MOS transistor constituting the storage section, . A method of manufacturing a mask ROM, characterized in that programming is performed by selectively forming a diffusion layer under a gate of a MOS transistor constituting the storage section.