KR20040003648A - Mos 트랜지스터 형성 방법 - Google Patents
Mos 트랜지스터 형성 방법 Download PDFInfo
- Publication number
- KR20040003648A KR20040003648A KR1020020038400A KR20020038400A KR20040003648A KR 20040003648 A KR20040003648 A KR 20040003648A KR 1020020038400 A KR1020020038400 A KR 1020020038400A KR 20020038400 A KR20020038400 A KR 20020038400A KR 20040003648 A KR20040003648 A KR 20040003648A
- Authority
- KR
- South Korea
- Prior art keywords
- gate
- forming
- source
- drain
- mos transistor
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 239000004065 semiconductor Substances 0.000 claims abstract description 9
- 238000000059 patterning Methods 0.000 claims abstract description 4
- 239000007943 implant Substances 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 5
- 229920002120 photoresistant polymer Polymers 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 7
- 125000006850 spacer group Chemical group 0.000 abstract description 6
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 230000010354 integration Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- QVMHUALAQYRRBM-UHFFFAOYSA-N [P].[P] Chemical compound [P].[P] QVMHUALAQYRRBM-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
Claims (2)
- 반도체 기판 상에 게이트 산화막과 게이트용 물질 및 캡핑 산화막을 형성하는 단계와,상기 게이트 산화막과 게이트용 물질 및 캡핑 산화막을 패터닝하여 게이트를 형성하는 단계와,상기 게이트가 형성된 결과물 상에 포토레지스트 패턴을 형성하는 단계와,상기 포토레지스트 패턴을 마스크로 반도체 기판의 소오스가 형성될 영역만 식각하는 단계와,상기 게이트 에지 부분의 기판에 임플란트 공정을 통해 LDD 영역을 형성하는 단계와,상기 게이트의 양측벽에 LDD 스페이서를 형성하는 단계와,상기 LDD 스페이서를 마스크로 고농도 임플란트 공정을 통해 소오스/드레인 영역을 형성하는 단계와상기 소오스/드레인에 열처리 공정을 실시하는 단계를포함하는 것을 특징으로 하는 MOS 트랜지스터의 형성 방법.
- 제 1항에 있어서, 상기 소오스/드레인 열처리 공정은 RTP 어닐링 공정으로 실시하는 것을 특징으로 하는 MOS 트랜지스터의 형성 방법.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020020038400A KR100642905B1 (ko) | 2002-07-03 | 2002-07-03 | Mos 트랜지스터 형성 방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020020038400A KR100642905B1 (ko) | 2002-07-03 | 2002-07-03 | Mos 트랜지스터 형성 방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20040003648A true KR20040003648A (ko) | 2004-01-13 |
KR100642905B1 KR100642905B1 (ko) | 2006-11-03 |
Family
ID=37314636
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020020038400A KR100642905B1 (ko) | 2002-07-03 | 2002-07-03 | Mos 트랜지스터 형성 방법 |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR100642905B1 (ko) |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5775460A (en) * | 1980-10-28 | 1982-05-12 | Toshiba Corp | Manufacture of semiconductor device |
JPH06244411A (ja) * | 1993-02-18 | 1994-09-02 | Nippon Steel Corp | 半導体装置 |
KR20010065293A (ko) * | 1999-12-29 | 2001-07-11 | 박종섭 | 반도체 소자의 트랜지스터 제조방법 |
-
2002
- 2002-07-03 KR KR1020020038400A patent/KR100642905B1/ko active IP Right Grant
Also Published As
Publication number | Publication date |
---|---|
KR100642905B1 (ko) | 2006-11-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100512029B1 (ko) | 마스킹 단계들이 감소된 nmos 및 pmos 디바이스 제조 방법 | |
KR100574172B1 (ko) | 반도체 소자의 제조방법 | |
KR100580796B1 (ko) | 반도체 소자의 제조 방법 | |
KR20050070932A (ko) | 반도체 소자 제조방법 | |
KR100642905B1 (ko) | Mos 트랜지스터 형성 방법 | |
KR100623373B1 (ko) | Mos 트랜지스터 형성 방법 | |
KR100406591B1 (ko) | 반도체소자의제조방법 | |
KR100561977B1 (ko) | 반도체 소자 제조 방법 | |
KR100588785B1 (ko) | 반도체 소자 제조 방법 | |
KR100598303B1 (ko) | 반도체 소자의 제조 방법 | |
KR100600253B1 (ko) | 반도체 소자 제조 방법 | |
KR100572212B1 (ko) | 반도체 소자 제조 방법 | |
KR100588784B1 (ko) | 반도체 소자 제조방법 | |
KR100588783B1 (ko) | 반도체 소자 제조 방법 | |
US6369434B1 (en) | Nitrogen co-implantation to form shallow junction-extensions of p-type metal oxide semiconductor field effect transistors | |
KR100334968B1 (ko) | 매몰 채널 pmos 트랜지스터 제조 방법 | |
KR100973091B1 (ko) | Mos 트랜지스터 제조 방법 | |
KR100546812B1 (ko) | 반도체 소자 제조방법 | |
KR100501935B1 (ko) | 제 2 측벽 공정을 이용한 반도체 소자의 제조 방법 | |
KR101128699B1 (ko) | 반도체 소자의 제조방법 | |
KR20000032450A (ko) | 반도체 소자 제조방법 | |
KR20080002009A (ko) | 반도체 메모리 소자의 제조방법 | |
KR20020002879A (ko) | 시모스(cmos) 트랜지스터의 제조 방법 | |
KR20050011436A (ko) | 반도체 소자 제조방법 | |
KR20050028591A (ko) | 반도체 소자 제조 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
N231 | Notification of change of applicant | ||
E902 | Notification of reason for refusal | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20120924 Year of fee payment: 7 |
|
FPAY | Annual fee payment |
Payment date: 20130916 Year of fee payment: 8 |
|
FPAY | Annual fee payment |
Payment date: 20140917 Year of fee payment: 9 |
|
FPAY | Annual fee payment |
Payment date: 20150923 Year of fee payment: 10 |
|
FPAY | Annual fee payment |
Payment date: 20160926 Year of fee payment: 11 |
|
FPAY | Annual fee payment |
Payment date: 20170920 Year of fee payment: 12 |
|
FPAY | Annual fee payment |
Payment date: 20180918 Year of fee payment: 13 |