KR100642905B1 - Mos 트랜지스터 형성 방법 - Google Patents
Mos 트랜지스터 형성 방법 Download PDFInfo
- Publication number
- KR100642905B1 KR100642905B1 KR1020020038400A KR20020038400A KR100642905B1 KR 100642905 B1 KR100642905 B1 KR 100642905B1 KR 1020020038400 A KR1020020038400 A KR 1020020038400A KR 20020038400 A KR20020038400 A KR 20020038400A KR 100642905 B1 KR100642905 B1 KR 100642905B1
- Authority
- KR
- South Korea
- Prior art keywords
- forming
- gate
- source
- drain
- mos transistor
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 27
- 238000005530 etching Methods 0.000 claims abstract description 5
- 239000007943 implant Substances 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 11
- 239000004065 semiconductor Substances 0.000 claims description 8
- 239000002019 doping agent Substances 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 5
- 229920002120 photoresistant polymer Polymers 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims 1
- 229910052698 phosphorus Inorganic materials 0.000 claims 1
- 239000011574 phosphorus Substances 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 7
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- QVMHUALAQYRRBM-UHFFFAOYSA-N [P].[P] Chemical compound [P].[P] QVMHUALAQYRRBM-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
Claims (2)
- 반도체 기판 상에 게이트 산화막과 게이트용 물질 및 캡핑 산화막을 형성하는 단계와,상기 게이트 산화막과 게이트용 물질 및 캡핑 산화막을 패터닝하여 게이트를 형성하는 단계와,상기 게이트가 형성된 결과물 상에 포토레지스트 패턴을 형성하는 단계와,상기 포토레지스트 패턴을 마스크로 반도체 기판의 소오스가 형성될 영역만 식각하는 단계와,상기 게이트 에지 부분의 기판에 0°의 틸트(tilt)에서 포스포러스(phosphorus) 도펀트를 이용하여 50 KeV의 에너지와 2.0E15의 도즈량을 주입하는 N-임플란트공정과, 0°의 틸트에서 BF2 도펀트를 이용하여 40KeV의 에너지와 2.0E15의 도즈량으로 P-임플란트 공정을 실시하여 LDD 영역을 형성하는 단계와,상기 게이트의 양측벽에 LDD 스페이서를 형성하는 단계와,상기 LDD 스페이서를 마스크로 고농도 임플란트 공정을 통해 소오스/드레인 영역을 형성하는 단계와상기 소오스/드레인에 급속열처리(RTP) 열처리 공정을 실시하는 단계를포함하는 것을 특징으로 하는 MOS 트랜지스터의 형성 방법.
- 삭제
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020020038400A KR100642905B1 (ko) | 2002-07-03 | 2002-07-03 | Mos 트랜지스터 형성 방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020020038400A KR100642905B1 (ko) | 2002-07-03 | 2002-07-03 | Mos 트랜지스터 형성 방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20040003648A KR20040003648A (ko) | 2004-01-13 |
KR100642905B1 true KR100642905B1 (ko) | 2006-11-03 |
Family
ID=37314636
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020020038400A KR100642905B1 (ko) | 2002-07-03 | 2002-07-03 | Mos 트랜지스터 형성 방법 |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR100642905B1 (ko) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5775460A (en) * | 1980-10-28 | 1982-05-12 | Toshiba Corp | Manufacture of semiconductor device |
JPH06244411A (ja) * | 1993-02-18 | 1994-09-02 | Nippon Steel Corp | 半導体装置 |
KR20010065293A (ko) * | 1999-12-29 | 2001-07-11 | 박종섭 | 반도체 소자의 트랜지스터 제조방법 |
-
2002
- 2002-07-03 KR KR1020020038400A patent/KR100642905B1/ko active IP Right Grant
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5775460A (en) * | 1980-10-28 | 1982-05-12 | Toshiba Corp | Manufacture of semiconductor device |
JPH06244411A (ja) * | 1993-02-18 | 1994-09-02 | Nippon Steel Corp | 半導体装置 |
KR20010065293A (ko) * | 1999-12-29 | 2001-07-11 | 박종섭 | 반도체 소자의 트랜지스터 제조방법 |
Also Published As
Publication number | Publication date |
---|---|
KR20040003648A (ko) | 2004-01-13 |
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