CN101355085A - 半导体器件的竖直浮体单元及其制造方法 - Google Patents
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Abstract
本发明公开一种半导体器件，该半导体器件包括形成于半导体基板上的管型通道。所述管型通道与第一导线和第二导线连接。偏压电极形成于所述管型通道中。所述偏压电极与所述半导体基板连接。绝缘膜设置在所述管型通道和所述偏压电极之间。围绕型栅电极形成于所述管型通道上。
Description
技术领域
本发明概括而言涉及半导体器件。本发明尤其涉及竖直浮体单元及其制造方法。
背景技术
人们已致力于克服包括晶体管和电容器的单元结构的限制。举例而言，消除了对存储器的高度集成构成阻碍的电容器，并且存储单元构造成具有晶体管，这称为浮体单元(floating body cell，FBC)结构。FBC结构利用了浮体效应的现象，当电荷蓄积于晶体管通道底部时，阈值电压改变。
当空穴注入或蓄积于NMOS中时，便产生浮体效应，从而降低通道的阈值电压并增加晶体管的电流。在FBC中，需要绝缘体上硅(SOI)基板，从而使得通道底部的空穴可以保持比较长的时间。FBC的详细结构和操作解释可参考“浮体RAM技术及其对于32纳米及以上节点的可扩展性(Floating body RAM Technology and itsscalability to 32nm node and beyond)”，T.Shino等人，IEDM，2006年。
在动态随机存取存储器(DRAM)中，电容器与单元晶体管连接，并且需要复杂的工序来形成该结构。此外，需要高度热处理工序以改进晶体管的特性。FBC技术可以略过上述复杂的工序，从而使得器件可以实现高度集成。FBC技术有助于实现包括逻辑电路而不包括电容器的嵌入式DRAM，由此可以用于各种应用场合。
如果具有平面晶体管的FBC的通道长度变短，则可以蓄积电荷的区域便会缩减。此外，产生的电荷会重组于源极/漏极区域中，如此就难以保持数据。结果，难以缩减晶体管的尺寸。使用SOI晶片会增加制造成本，因而限制了FBC的商业化。
发明内容
本发明的实施例涉及包括FBC的半导体器件。根据本发明的实施例，所述FBC包括：管型通道；偏压电极，其在所述管型通道中与半导体基板连接；绝缘膜，其设置在所述管型通道和所述偏压电极之间；以及围绕型栅极，其形成于所述管型通道上。所述FBC确保有足够的电荷蓄积区域，由此改进器件的集成度以及器件的数据保持时间。
根据本发明的实施例，一种包括浮体单元结构的半导体器件包括形成于半导体基板上并与第一导线和第二导线连接的管型通道。偏压电极形成于所述管型通道中并且与所述半导体基板连接。绝缘膜位于所述管型通道和所述偏压电极之间。围绕型栅电极形成于所述管型通道上。
根据本发明的实施例，一种制造半导体器件的方法包括在半导体基板上形成传导柱。蚀刻所述传导柱和所述半导体基板的一部分以形成传导管。在所述传导管的内侧壁上形成绝缘膜。形成与所述半导体基板连接的偏压电极以填充所述传导管。在所述传导管的外表面上形成栅极绝缘膜。在所述栅极绝缘膜上形成围绕型栅电极。
附图说明
图1是根据本发明实施例的半导体器件的布局；
图2是示出根据本发明实施例的半导体器件的透视图；
图3a到3s是示出根据本发明实施例的半导体器件制造方法的剖视图；以及
图4a到4d是示出根据本发明另一实施例的半导体器件制造方法的剖视图。
具体实施方式
根据本发明的实施例，半导体器件具有包括竖直晶体管的FBC结构。
图1是根据本发明实施例的半导体器件的布局。半导体器件包括由器件隔离区域120所限定的通道区102、偏压电极区域104、源极线区域106、字线区域108、位线区域110。源极线区域106在半导体基板上方朝向某一方向延伸。通道区102设置在源极线区域106上方而具有竖直管结构。偏压电极区域104则位于通道区102中。
通道区102的外线宽是F，其中F是两个相邻通道区102之间的距离。虽然本发明实施例中的通道区102的顶面(如图1所示)形成矩形，但是通道区102的顶面可以形成圆形或多边形。
字线区域108朝向一侧延伸，使得字线区域108与源极线区域106交叉，并且在通道区102之外形成字线区域108，从而具有围绕型栅极结构。位线区域110设置在通道区102上方且与源极线区域106重叠，并且朝向一侧延伸。字线区域108的线宽大于通道区102的线宽，从而覆盖通道区102。
图2是示出根据本发明实施例的半导体器件的透视图。半导体器件包括半导体基板210、源极线220、通道结构230、偏压电极240、栅电极250、位线260。源极线220在半导体基板210上方朝向一侧延伸。
通道结构230形成于源极线220上方而具有竖直管结构。绝缘膜(未显示)形成于通道结构230的内侧壁上而具有SOI结构。栅极绝缘膜(未显示)形成于通道结构230的外侧壁上。偏压电极240形成于包括绝缘膜的通道结构230内部，从而使得偏压电极240与半导体基板210连接。偏压电极240被施加偏压以便于在通道结构230中捕获载子(例如空穴或电子)，由此增加数据保持时间。虽然通道结构230形成为圆形，但是并不限于圆形结构。
栅电极250形成于包括栅极绝缘膜的通道结构230外部，而具有围绕型栅极结构。栅电极250朝向一侧延伸，从而使得栅电极250与源极线220交叉。栅电极250的线宽大于通道结构230的外线宽，从而覆盖通道结构230。位线260形成于通道结构230上方而平行于源极线220。位线接触插塞270可以进一步形成于位线260和通道结构230之间，从而使得位线260与通道结构230连接。
图3a到3s是示出根据本发明实施例的半导体器件制造方法的剖视图。图3a(i)到3s(i)是沿着图1的I-I’截取的剖视图，而图3a(ii)到3s(ii)是沿着图1的II-II’截取的剖视图。在半导体基板310上进行清洁工序以移除残余氧化膜。在半导体基板310上方形成掺杂有第一型杂质的第一硅层312。在第一硅层312上方形成掺杂有第二型杂质的第二硅层314。在第二硅层314上方形成第一硬掩模层316。
第一硅层312包括单晶硅层。可以使用包含SiCl4/SiH4和SiH2Cl2的气体源和包含HCl和H2的额外气体，在范围为约400℃到1,000℃的温度下、范围为约1毫托耳(mTorr)到760毫托耳的压力下形成该单晶硅层。第一硅层312的厚度范围可以为约
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第一硅层312可以由n型硅层形成。可以通过将PH3植入单晶层或在形成单晶层的同时植入PH3而形成该n型硅层。可以通过将第一型杂质离子植入半导体基板310而形成第一硅层312。第一型杂质包括浓度范围为每立方厘米约1×1018个离子到每立方厘米约1×1021个离子的磷(P)。
第二硅层314包括未掺杂的单晶层。可以使用包含SiCl4/SiH4和SiH2Cl2的气体源和包含HCl和H2的额外气体，在范围为约400℃到1,000℃的温度下、范围为约1毫托耳到760毫托耳的压力下形成该未掺杂的单晶层。第二型杂质可以是包含硼(B)的p型杂质。可以通过在形成未掺杂的单晶层的同时植入p型杂质而形成掺杂有p型杂质的第二硅层314。为了使用第二硅层314作为通道，可以将p型杂质植入未掺杂的单晶层。第二硅层314的第二型杂质的浓度范围可以为每立方厘米约1×1017个离子到每立方厘米约1×1019个离子。在本发明的一个实施例中，竖直通道结构可以由第二硅层314、金属层及其组合形成。竖直通道结构可以包括氮化钛(TiN)膜、氮化钽(TaN)膜和钨(W)层。
第一硬掩模层316可以是氧化膜、氮化膜或其组合。可以使用包含TEOS(Si(OC2H5)4)和SiH4的气体源并借助于等离子CVD法来形成氧化膜。可以使用包含SiH2Cl2和NH3的气体源借助于LPCVD法来形成氮化膜。第一硬掩模层316的厚度范围为约
到第一硬掩模层316的蚀刻选择性高于硅层的蚀刻选择性。举例而言，第一硬掩模层316的蚀刻速率可以是硅层的一半或更低。
参照图3b，使用限定图1所示通道区102的掩模来蚀刻第一硬掩模层316，以形成第一硬掩模图案(未显示)。对第一硬掩模图案进行等向性蚀刻以形成第二硬掩模图案316a，这缩减了第一硬掩模图案的尺寸。在第二硅层314和第二硬掩模图案316a上方形成第二硬掩模层(未显示)。选择性地蚀刻第二硬掩模层，以便于在第二硬掩模图案316a的侧壁上形成第一间隙壁318。在本发明的一个实施例中，限定图1所示通道区102的掩模是矩形，其宽度F为相邻通道结构之间的距离。虽然有源区102形成为矩形(如图1所示)，但是有源区102也可以形成为圆形或多边形。
第二硬掩模层是使用包含SiH2Cl2和NH3的气体源借助于LPCVD法而由氮化硅膜所形成的。第一间隙壁318的厚度范围为约
到
第二硬掩模层的蚀刻选择性高于硅层的蚀刻选择性。举例而言，第二硬掩模层的蚀刻速率可以是硅层的一半或更小。此外，第二硬掩模层的蚀刻选择性高于第一硬掩模层的蚀刻选择性。第二硬掩模层的蚀刻速率可以是第一硬掩模层的一半或更小。
参照图3c和3d，使用第一间隙壁318和第二硬掩模图案316a作为蚀刻掩模来蚀刻图3b的第二硅层314以形成硅柱322。在第一硅层312、硅柱322、第一间隙壁318和第二硬掩模图案316a上形成第一绝缘膜324，以填充硅柱322。将第一绝缘膜324平坦化，直到第二硬掩模图案316a露出为止。使用限定图1所示源极线区域106的掩模来蚀刻第一绝缘膜324、第一硅层312以及半导体基板310的一部分，以形成用于源极线的第一硅图案320。在半导体基板310、第一硅图案320和第一绝缘膜324上形成第二绝缘膜326，以将第一硅图案320电气隔离。
第一绝缘膜324可以包括氧化硅膜。第一硅图案320可以形成线型的轮廓。形成第一硅图案320的蚀刻工序可以借助于间隙壁图案化技术(spacer patterning technology，SPT)来进行。举例而言，由图案线宽和限定于两相邻图案之间的空间所限定的间距，可以是最小线宽的二倍或更多倍。然而，该空间可以小于最小线宽。在该情况下，图案形成为具有最小线宽。间隙壁形成于图案的侧壁以限定小于最小线宽的空间。可以对小于最小线宽的空间进行蚀刻。在本发明中，虽然对小于最小线宽的空间进行蚀刻的工序是借助于SPT法来进行，但是并不仅限于该方法。
第一硅图案320之间的距离是G(0.5F＜G＜0.7F，F是最小线宽)。将第一绝缘膜324平坦化的工序可以借助于CMP法或回蚀法来进行。第二绝缘膜326包括氧化硅膜。氧化硅膜可以借助于CVD法或ALD法来形成。
参照图3e到3h，移除第二硬掩模图案316a以露出硅柱322的顶面。当第二硬掩模图案316a已移除时，可以蚀刻第一绝缘膜324和第二绝缘膜326，以降低第一绝缘膜324和第二绝缘膜326的高度。蚀刻硅柱322、第一硅图案320以及半导体基板310的一部分，以形成用于通道区的硅管330。在硅管330中形成第三绝缘膜328。第三绝缘膜328作为SOI结构中的嵌埋氧化膜。选择性地蚀刻第三绝缘膜328，以在硅管330的底部露出半导体基板310。
移除第二硬掩模图案316a的工序可以借助于包含HF的湿式蚀刻法来进行。可以通过对于第一间隙壁318具有蚀刻选择性的蚀刻方法来移除第二硬掩模图案316a。该蚀刻方法可以借助于包含CHF、O2、HCl、Ar、He或其组合的直接或远程等离子蚀刻方法来进行。可以适当选择CHF中的C、H、F比例。
第三绝缘膜328包括氧化硅膜。可以在O2、H2O、H2、O3或其组合的氛围下、在范围为约200℃到1000℃的温度下形成该氧化硅膜。由于硅管330可以有各种结晶的硅表面，因此第三绝缘膜328可以借助于自由基硅氧化法(radical silicon oxidation)来形成，以保持第三绝缘膜328的均匀厚度。第三绝缘膜328的厚度范围为约1纳米到100纳米。选择性地蚀刻第三绝缘膜328的工序可以借助于干式蚀刻法来进行。
参照图3i到3k，在硅管330、第一绝缘膜324、第二绝缘膜326和第一间隙壁318上形成第一传导层332，以填充硅管330。选择性地蚀刻第一传导层332以形成隔离的偏压电极340。选择性地蚀刻第一绝缘膜324，直到第一硅图案320露出为止，以露出硅管330的外侧。在第一硅图案320、硅管330和偏压电极340上形成栅极绝缘膜342。
在形成第一传导层332之前，先进行清洁半导体基板310表面的工序，从而使得偏压电极340与半导体基板310电连接。第一传导层332包括掺杂有p型杂质的多晶硅层。可以通过使用CVD法在形成多晶硅层的同时植入p型杂质而形成p型多晶硅层。可以进一步进行等离子氮化工序，以避免硼杂质扩散到第一传导层332中。可以进一步在第一传导层332上形成氮化硅膜。选择性地蚀刻第一传导层332的工序可以借助于回蚀法来进行。
选择性地蚀刻第一绝缘膜324的工序可以借助于干式或湿式回蚀法来进行。栅极绝缘膜342包括氧化硅膜。可以在O2、H2O、H2、O3或其组合的氛围下、在范围为约200℃到1,000℃的温度下形成该氧化硅膜。由于硅管330可有各种结晶的硅表面，因此栅极绝缘膜342可以借助于自由基硅氧化法来形成，以保持栅极绝缘膜342的均匀厚度。栅极绝缘膜342的厚度范围为约1纳米到100纳米。可以在形成栅极绝缘膜342之后使用等离子方法将栅极绝缘膜342氮化。
栅极绝缘膜342可以是氧化硅膜、氧化铪膜、氧化铝膜、氧化锆膜、氮氧化硅铪膜、氮化硅膜或其组合。栅极绝缘膜342的厚度范围为约1纳米到100纳米。
参照图3l到3n，在栅极绝缘膜342、第二绝缘膜326和第一间隙壁318上形成第二传导层344，以填充硅管330之间所限定的空间。选择性地蚀刻第二传导层344，以便于在硅管330的外侧上形成围绕型栅电极346。在围绕型栅电极346和第一间隙壁318上形成第四绝缘膜348，以填充围绕型栅电极346、偏压电极340和第一间隙壁318。
第二传导层344包括具有下传导层(未显示)和上传导层(未显示)的叠层结构。下传导层包括掺杂有杂质的多晶硅层。该掺杂有杂质的多晶硅层可以借助于CVD法来形成。可以在形成多晶硅层的同时植入包含磷(P)或硼(B)的杂质。上传导层可以是钨(W)层、铝(Al)层、铜(Cu)层、硅化钨(WSiX)层或其组合。
选择性地蚀刻第二传导层344的工序可以借助于回蚀法来进行。可以进一步进行包括湿式蚀刻法的清洁工序，从而使得第二传导层344不会留在第一间隙壁318的侧壁上。栅电极346的顶面可以形成为低于硅管330的顶面，以便于与偏压电极340电气隔离。第四绝缘膜348包括氧化硅膜。
参照图3o和3p，使用限定图1所示字线区域108的掩模，将第四绝缘膜348和栅电极346图案化，以形成与栅电极346分离的字线350。在字线350和第四绝缘膜348上形成第五绝缘膜352。选择性地蚀刻第五绝缘膜352和第四绝缘膜348，以露出第一间隙壁318。
第五绝缘膜352包括氧化硅膜。限定图1所示字线区域108的掩模形成线型。在本发明的一个实施例中，虽然形成字线350的图案化工序是借助于SPT蚀刻法来进行，但是并不仅限于该方法。相邻字线之间的距离是H(0.5F＜H＜0.7F)。选择性地蚀刻第四绝缘膜348和第五绝缘膜352的工序可以借助于CMP法来进行。
参照图3q到3s，移除第一间隙壁318以露出硅管330的顶面。在硅管330和第四绝缘膜348上形成第三传导层(未显示)。蚀刻第三传导层以露出第四绝缘膜348，从而形成位线接触插塞370。在位线接触插塞370和第四绝缘膜348上形成第四传导层372。使用限定图1所示位线区域110的掩模将第四传导层372图案化，以形成位线360。虽然可以在根据本发明实施例的半导体器件中得到4F2的单元面积，但是并不仅限于此。
移除第一间隙壁318的工序可以借助于包含磷酸的湿式蚀刻法来进行。可以使用HF在硅管330上进一步进行清洁工序。第三传导层和第四传导层372可以是n+多晶硅层、氮化钛(TiN)膜、钨(W)层、铝(Al)层、铜(Cu)层或其组合。在多晶硅层填充于其中移除第一间隙壁318的空间之后，在多晶硅层和第四绝缘膜348上形成第四传导层372，以降低界面电阻。限定位线区域的掩模形成线型。相邻位线360之间的距离是I(0.9F＜I＜1.1F)。
图4a到4d是示出根据本发明另一实施例的半导体器件制造方法的剖视图。在侧壁间隙壁形成于硅柱上之后，利用掩模蚀刻硅柱，以形成硅管。可以不在第一硬掩模图案上进行修整工序。
参照4a到4d，使用第一硬掩模图案416将第二硅层图案化，以形成硅柱422。在第一硅层412、硅柱422和第一硬掩模图案416上形成第六绝缘膜424，以填充硅柱422。将第六绝缘膜424平坦化，直到第一硬掩模图案416露出为止。使用限定图1所示源极线区域106的掩模蚀刻第六绝缘膜424、第一硅层412以及半导体基板410的一部分，以形成用于源极线的第一硅图案420。在第一硅图案420和第六绝缘膜424上形成第七绝缘膜426，以将第一硅图案420电气隔离。
第六绝缘膜424包括氧化硅膜。将第六绝缘膜424平坦化的工序可以借助于CMP法来进行。限定源极线区域的掩模形成线型。虽然蚀刻第一硅图案420的工序是借助于SPT蚀刻法来进行的，但是并不仅限于该方法。第一硅图案420之间的距离是G(0.5F＜G＜0.7F)。第七绝缘膜426包括氧化硅膜。该氧化硅膜可以借助于CVD法或ALD法来形成。
参照图4c和4d，移除第一硬掩模图案416以形成露出硅柱422的空间432。在空间432的侧壁上形成第二间隙壁434。使用第二间隙壁434作为蚀刻掩模来蚀刻硅柱422、第一硅图案420以及半导体基板410的一部分，以形成用于通道区的硅管430。
移除第一硬掩模图案416的工序可以借助于湿式蚀刻法来进行。由氮化硅膜所形成的第一硬掩模图案416可以借助于包含磷酸的湿式蚀刻法来移除。在硅柱422、第六绝缘膜424和第七绝缘膜426上形成第八绝缘膜(未显示)，以便于在空间432的侧壁上形成第二间隙壁434。可以借助于干式蚀刻法蚀刻第八绝缘膜，以形成第二间隙壁428。第八绝缘膜包括氮化硅膜。该氮化硅膜可以借助于CVD法或ALD法来形成。可以进行图3g到3s所示的工序以形成竖直浮体单元(FBC)。
FBC的数据可以在硅管中存储为电位。当对位线施加高电压以写入“1”状态数据时，便会发生冲击性离子化，并且空穴可以蓄积于硅管中。硅管中的电位改变为“1”状态。当对位线施加负电压以写入“0”状态数据时，便会从硅管中提取出空穴，并且硅管中的电位改变为“0”状态。
如上所述，根据本发明的实施例，可以获得竖直FBC，从而确保通道长度，即使单元面积缩减也如此。此外，可以在不使用SOI晶片的情况下得到FBC以减少成本。芯片包括微处理器和带有逻辑电路的存储器。此外，竖直FBC确保有足够的区域可以蓄积电荷，由此改进数据保持时间。与半导体基板连接的偏压电极形成于通道中以增加数据保持时间。使用通道的外侧作为通道区以确保有足够的电流，由此有效产生电荷并提高读/写的操作速度。每个晶体管中的通道是隔离的，由此抑制阈值电压随着相邻通道电位而改变的现象。结果可以得到优良的信噪比。
本发明的上述实施例是示例性而非限制性的。各种不同的替代物和等同物都是可行的。本发明并不受限于本文中所描述的光刻步骤。本发明也不限于任何特定类型的半导体器件。举例而言，本发明可应用于动态随机存取存储(DRAM)器件或非易失性存储器件。鉴于本发明的揭示内容，其它的增添、删减或修改都是显而易见的，这些内容都落入所附权利要求书的范围内。
Claims (21)
1.一种具有浮体单元结构的半导体器件，所述半导体器件包括：
管型通道，其形成于半导体基板上并与第一导线和第二导线连接；
偏压电极，其形成于所述管型通道中并与所述半导体基板连接；
绝缘膜，其位于所述管型通道和所述偏压电极之间；以及
围绕型栅电极，其形成于所述管型通道上。
2.根据权利要求1所述的半导体器件，其中，
所述第一导线与所述管型通道的底部连接。
3.根据权利要求1所述的半导体器件，其中，
所述第二导线与所述管型通道的顶部连接。
4.根据权利要求1所述的半导体器件，其中，
所述管型通道的顶面是圆形或多边形的。
5.一种制造半导体器件的方法，所述方法包括：
在半导体基板上形成传导柱；
蚀刻所述传导柱和所述半导体基板的一部分以形成传导管；
在所述传导管的内侧壁上形成绝缘膜；
形成与所述半导体基板连接的偏压电极以填充所述传导管；
在所述传导管的外表面上形成栅极绝缘膜；以及
在所述栅极绝缘膜上形成围绕型栅电极。
6.根据权利要求5所述的方法，其中，
形成所述传导柱的步骤包括：
在所述半导体基板上形成传导层；
在所述传导层上形成硬掩模层；
利用有源区掩模选择性地蚀刻所述硬掩模层，以形成硬掩模图案；
在所述硬掩模图案的侧壁上形成间隙壁；以及
使用所述硬掩模图案和所述间隙壁作为蚀刻掩模选择性地蚀刻所述传导层，以形成所述传导柱。
7.根据权利要求6所述的方法，其中，
所述传导层是由p型或未掺杂的硅层形成的，其厚度范围为约500
到5,000
8.根据权利要求6所述的方法，其中，
所述传导层中植入有硼。
9.根据权利要求6所述的方法，其中，
所述硬掩模层选自包括氧化膜、氮化硅膜及其组合的群组，其厚度范围为约500
到5,000
10.根据权利要求6所述的方法，其中，
所述间隙壁是由氮化硅膜形成的，其厚度范围为约100
到500
11.根据权利要求6所述的方法，其中，
所述有源区掩模的形状是圆形或多边形的。
12.根据权利要求6所述的方法，其中，
所述绝缘膜是由氧化硅膜形成的，其厚度范围为约1纳米到100纳米。
13.根据权利要求5所述的方法，其中，
所述偏压电极选自包括单晶硅层、多晶硅层、氮化钛膜、氮化钽膜、钨层及其组合的群组。
14.根据权利要求5所述的方法，其中，
所述栅极绝缘膜选自包括氧化硅膜、氧化铪膜、氧化铝膜、氧化锆膜、氮氧化硅铪膜、氮化硅膜及其组合的群组，其厚度范围为约1纳米到100纳米。
15.根据权利要求5所述的方法，其中，
所述栅电极选自包括多晶硅层、钛层、氮化钛膜、氮化钽膜、钨层、铝层、铜层、硅化钨(WSiX)层及其组合的群组。
16.根据权利要求5所述的方法，还包括：
形成与所述传导管的顶部连接的第二导线。
17.根据权利要求5所述的方法，还包括：
在所述半导体基板和所述传导管之间形成第一导线。
18.根据权利要求17所述的方法，其中，
所述第一导线是借助于硅生长法由单晶硅层所形成，其厚度范围为约100
到5,000
19.根据权利要求17所述的方法，其中，
所述第一导线中植入有PH3。
20.一种制造半导体器件的方法，所述方法包括：
在半导体基板上形成传导层；
在所述传导层上形成硬掩模层；
选择性地蚀刻所述硬掩模层以形成硬掩模图案；
在所述硬掩模图案的侧壁上形成间隙壁；
使用所述硬掩模图案和所述间隙壁作为蚀刻掩模选择性地蚀刻所述传导层，以形成传导柱；
蚀刻所述传导柱和所述半导体基板的一部分以形成传导管，第一导线形成于所述半导体基板和所述传导管之间；
在所述传导管的内侧壁上形成绝缘膜；
形成与所述半导体基板连接的偏压电极以填充所述传导管；
在所述传导管的外侧壁上形成栅极绝缘膜；以及
在所述栅极绝缘膜上形成围绕型栅电极。
21.根据权利要求20所述的方法，还包括：
形成与所述传导管的顶部连接的第二导线。
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| JP (1) | JP2009033103A (zh) |
| KR (1) | KR100881825B1 (zh) |
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| US10892016B1 (en) | 2019-04-08 | 2021-01-12 | Monolithic 3D Inc. | 3D memory semiconductor devices and structures |
| US11018156B2 (en) | 2019-04-08 | 2021-05-25 | Monolithic 3D Inc. | 3D memory semiconductor devices and structures |
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| JP2748072B2 (ja) * | 1992-07-03 | 1998-05-06 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
| JP3230846B2 (ja) * | 1992-07-30 | 2001-11-19 | 株式会社東芝 | 半導体装置および半導体集積回路装置 |
| JP3403231B2 (ja) * | 1993-05-12 | 2003-05-06 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
| JPH098290A (ja) * | 1995-06-20 | 1997-01-10 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
| US5637898A (en) * | 1995-12-22 | 1997-06-10 | North Carolina State University | Vertical field effect transistors having improved breakdown voltage capability and low on-state resistance |
| JP3371708B2 (ja) * | 1996-08-22 | 2003-01-27 | ソニー株式会社 | 縦型電界効果トランジスタの製造方法 |
| JPH1093083A (ja) * | 1996-09-18 | 1998-04-10 | Toshiba Corp | 半導体装置の製造方法 |
| US6667502B1 (en) * | 1999-08-31 | 2003-12-23 | Micron Technology, Inc. | Structurally-stabilized capacitors and method of making of same |
| JP3884266B2 (ja) * | 2001-02-19 | 2007-02-21 | 株式会社東芝 | 半導体メモリ装置及びその製造方法 |
| JP2003031693A (ja) * | 2001-07-19 | 2003-01-31 | Toshiba Corp | 半導体メモリ装置 |
| JP2005064031A (ja) * | 2003-08-12 | 2005-03-10 | Fujio Masuoka | 半導体装置 |
| JP2006073627A (ja) * | 2004-08-31 | 2006-03-16 | Toshiba Corp | 半導体集積装置 |
| JP4081071B2 (ja) * | 2004-11-26 | 2008-04-23 | 株式会社東芝 | 半導体記憶装置とその製造方法 |
| JP2006080549A (ja) * | 2005-10-18 | 2006-03-23 | Toshiba Corp | 半導体記憶装置及び半導体集積回路 |
| KR100699890B1 (ko) * | 2006-01-10 | 2007-03-28 | 삼성전자주식회사 | 반도체 메모리 소자 및 그 제조 방법 |
| TWI293207B (en) | 2006-01-11 | 2008-02-01 | Promos Technologies Inc | Dynamic random access memory structure and method for preparing the smae |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110520989A (zh) * | 2017-05-08 | 2019-11-29 | 美光科技公司 | 存储器阵列 |
| CN110520989B (zh) * | 2017-05-08 | 2023-09-29 | 美光科技公司 | 存储器阵列 |
| USRE49715E1 (en) | 2017-05-08 | 2023-10-24 | Micron Technology, Inc. | Memory arrays |
| US11631678B2 (en) | 2017-07-27 | 2023-04-18 | Micron Technology, Inc. | Memory arrays comprising memory cells |
| US11864386B2 (en) | 2018-11-29 | 2024-01-02 | Micron Technology, Inc. | Memory arrays |
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| TW200905886A (en) | 2009-02-01 |
| TWI353061B (en) | 2011-11-21 |
| KR100881825B1 (ko) | 2009-02-03 |
| US20100151635A1 (en) | 2010-06-17 |
| US7943444B2 (en) | 2011-05-17 |
| JP2009033103A (ja) | 2009-02-12 |
| US7663188B2 (en) | 2010-02-16 |
| US20090026541A1 (en) | 2009-01-29 |
| CN101355085B (zh) | 2010-12-01 |
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