CN101325167B - 制造具有均匀涂层厚度的半导体器件的方法及相关器件 - Google Patents

制造具有均匀涂层厚度的半导体器件的方法及相关器件 Download PDF

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CN101325167B
CN101325167B CN2008101446705A CN200810144670A CN101325167B CN 101325167 B CN101325167 B CN 101325167B CN 2008101446705 A CN2008101446705 A CN 2008101446705A CN 200810144670 A CN200810144670 A CN 200810144670A CN 101325167 B CN101325167 B CN 101325167B
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parts
layer
diffusion impervious
substrate
impervious layer
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CN101325167A (zh
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姜芸炳
权容焕
李忠善
权云星
张衡善
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

一种制造半导体器件的方法，包括：在衬底上形成扩散阻挡层，和在衬底上形成至少两个部件，从而扩散阻挡层分别设置在每个部件和衬底之间并接触所述至少两个部件。衬底的第一杂质区含有第一类型杂质，衬底的第二杂质区含有不同于第一类型的第二类型杂质，所述至少两个部件中的第一部件位于第一杂质区，所述至少两个部件中的第二部件位于第二杂质区，从而通过不同杂质区第二部件与第一部件电隔离。

Description

制造具有均匀涂层厚度的半导体器件的方法及相关器件
技术领域
本发明涉及一种制造半导体器件的方法，更具体地，涉及一种使用无电镀制造具有均匀涂层厚度的半导体器件的方法以及由此制造的器件。
背景技术
通常，电镀和无电镀可用于在衬底上沉积材料层，例如导电层。电镀通常包括将目标衬底暴露到含金属溶液，该含金属溶液中金属离子溶解在酸中，通过施加电势进行还原反应以将金属离子转变成衬底上的金属层。例如，衬底可以浸入到含金属溶液中，同时将其作为电路的阴极来连接。阴极可连接到电源的第一极，并将连接到电源相反极的阳极浸入到溶液中以完成电路。
与常规电镀不同，无电镀不依赖于施加外部电势来进行镀覆工艺。由于与电镀相比，相对简单的无电镀工艺可能需要更少的装置以及更低的成本，因此无电镀是电镀的理想替代。而且，无电镀可以在凸点的侧壁和顶部上形成金属层，而电镀只能在凸点顶部上形成金属层。
通常认为即使不导电的衬底也可以使用无电镀来镀覆，即对衬底的导电性无要求。但是在使用无电镀来镀覆被精细构图的部件(feature)时，在衬底上形成的相似部件之间的电势差会导致这些部件被不均匀地镀覆。因此在制造具有被精细构图的部件如凸点、布线图形等的半导体器件时，使用无电镀工艺会导致镀覆厚度发生变化，镀覆厚度的变化会降低半导体器件的可靠性。
发明内容
本发明涉及使用无电镀制造具有均匀涂层厚度的半导体器件的方法以及相关器件，其基本上克服了由于现有技术的限制和不足导致的一个或多个问题。
本发明提供了一种无电镀方法，其适合于镀覆位于衬底的含有不同类型杂质的区域中的部件。
本发明还提供了一种器件，其包括具有外部导电层的部件，该部件位于衬底的含有不同类型杂质的区域中。
上述和其他优点中的至少一个可以通过提供一种制造半导体器件的方法来实现，该方法包括在衬底上形成扩散阻挡层，和在衬底上形成至少两个部件，从而扩散阻挡层分别设置在每个部件和衬底之间并接触所述至少两个部件。衬底的第一杂质区含有第一类型杂质，衬底的第二杂质区含有与第一类型不同的第二类型杂质，所述至少两个部件中的第一部件可以位于第一杂质区中，所述至少两个部件中的第二部件可以位于第二杂质区中，从而通过所述不同杂质区第二部件与第一部件电隔离。
扩散阻挡层可以提供所述至少两个部件之间的电通路，该方法还可以包括在所述至少两个部件通过电通路连接的同时在所述至少两个部件上无电镀外部导电层，以及在无电镀之后处理扩散阻挡层以中断电通路。处理扩散阻挡层以中断电通路可包括从包围所述至少两个部件中的至少一个的区域去除扩散阻挡层。在中断电通路之后，扩散阻挡层可横向延伸到导电层的外边缘并被导电层暴露。
导电层可镀覆到包括铜或镍中的一种或多种的部件表面上，该导电层可包括镍、金、钯、锡或铟中的一种或多种，且扩散阻挡层可包括钛、铬或铝中的一种或多种。该导电层可包括每个部件表面上的钯层、每个钯层上的镍层以及每个钯层上的至少一个金层。
该方法还包括，在形成扩散阻挡层之后且在无电镀之前，在衬底上形成籽晶层，在籽晶层上选择性形成所述至少两个部件，以及从所述至少两个部件之间的区域选择性去除籽晶层。所述至少两个部件通过电镀或者无电镀形成。形成所述至少两个部件包括：在衬底上形成籽晶层；在衬底上形成光致抗蚀剂图形，该光致抗蚀剂图形具有对应于所述至少两个部件的开口，该开口暴露出籽晶层；使用电镀在光致抗蚀剂图形中的开口中沉积材料；平坦化所沉积材料以形成所述至少两个部件；去除该光致抗蚀剂图形；以及去除籽晶层的与所述至少两个部件相邻的在衬底上暴露的部分。该籽晶层可以是导电的。
提供电通路的扩散阻挡层的一部分可以在无电镀期间暴露。该方法还可以包括，在无电镀之前，对提供电通路的扩散阻挡层的暴露部分进行氧等离子体表面处理。
上述和其他优点中的至少一个也可通过提供一种半导体器件来实现，该半导体器件包括：衬底；衬底上的至少两个部件，所述至少两个部件的每个都包括外部导电层；以及分别设置在每个部件和衬底之间的扩散阻挡层，其中衬底的第一杂质区含有第一类型杂质，衬底的第二杂质区含有与第一类型不同的第二类型杂质，所述至少两个部件的第一部件处于第一杂质区中，所述至少两个部件的第二部件位于第二杂质区中，从而通过所述不同杂质区第二部件与第一部件电隔离，且每个相应扩散阻挡层可以横向延伸到相应导电层的外边缘，并可被相应的导电层暴露。
导电层可与扩散阻挡层的顶表面接触。每个部件可以包括有不同于导电层的组成的芯材。该芯材可包括铜或镍中的一种或多种。该导电层可包括镍、金、钯、锡或铟中的一种或多种。扩散阻挡层可包括钛、铬或铝中的一种或多种。扩散阻挡层可包括钛-氮化合物或钛-钨化合物中的一种或多种。
所述至少两个部件可以是凸点，该凸点被设置为在半导体器件和第二衬底之间提供电信号。所述至少两个部件可以是布线导线。
上述和其他优点中的至少一个也可通过提供一种显示装置来实现，该显示装置包括显示器和连接到该显示器的显示驱动集成电路(display driver integrated circuit)，其中显示器被设置为响应由显示驱动集成电路提供的信号来再现图像，显示驱动集成电路包括：衬底；衬底上的至少两个部件，所述至少两个部件的每个包括外部导电层；和分别设置在每个部件和衬底之间的扩散阻挡层，其中衬底的第一杂质区含有第一类型杂质，衬底的第二杂质区含有不同于第一类型的第二类型杂质，所述至少两个部件中的第一部件处于第一杂质区中，所述至少两个部件中的第二部件处于第二杂质区中，从而通过所述不同的杂质区第二部件与第一部件电隔离，且每个相应的扩散阻挡层可以横向延伸到相应导电层的外边缘并可被相应的导电层暴露。
上述和其他优点中的至少一个也可以通过提供一种制造半导体器件的方法来实现，该方法包括：在衬底上形成扩散阻挡层；在衬底上形成至少两个部件从而扩散阻挡层分别设置在每个部件和衬底之间，该扩散阻挡层电连接所述至少两个部件；在所述至少两个部件通过扩散阻挡层电连接的同时，在所述至少两个部件上无电镀外部导电层；以及选择性去除扩散阻挡层以中断电连接。
上述和其他优点中的至少一个还可通过提供一种半导体器件来实现，该半导体器件包括：衬底；在衬底上的第一部件和第二部件；在衬底和第一部件之间的第一扩散阻挡物；在第一部件上的第一导电层；在衬底和第二部件之间的第二扩散阻挡物；以及在第二部件上的第二导电层，其中第一导电层接触第一扩散阻挡物的顶表面，第二导电层接触第二扩散阻挡物的顶表面。
附图说明
通过参考附图详细描述其示意性实施例，上述和其他特征以及优点对于本领域技术人员将更加明显，其中：
图1示出了无电镀操作的示意图；
图2A-2I示出了根据第一实施例的制造半导体器件的方法中的步骤；
图3A示出了根据第二实施例的实例半导体器件的平面图；
图3B示出了沿着图3A的线A-A取得的图3A的半导体器件的截面图；
图4A-4G示出了沿着图3A的线B-B取得的图3A中所示制造半导体器件方法中步骤的横截面图；
图5示出了根据第三实施例的实例存储卡；
图6示出了根据第四实施例的实例电子系统；和
图7示出了根据第五实施例的实例显示器件。
具体实施方式
现在将参考附图在下面更充分地描述实施例，然而，它们不应被解释为仅限于此处所述的实施例。相反地，提供这些实施例是为了使本公开透彻和完整，并且将本发明的范围充分传达给本领域技术人员。
图中层和区域的尺寸可以被放大以更清楚的说明。还认为，当将一层或元件称作在另一层或衬底“上”时，其可直接位于该另一层或衬底上，或者还存在中间层。而且，认为当将一层称作在另一层“下”时，其可直接在其之下，也可以存在一个或多个中间层。此外，还认为，当将一层称作在两层“之间”时，其可以是该两层之间仅有的层，或者也可以存在一个或多个中间层。当将一元件描述为连接到第二元件时，该元件可直接连接到第二元件，或者可经由一个或多个其他元件间接连接到第二元件。而且，当将一元件描述为连接到第二元件时，认为该元件可以是电连接的，例如在晶体管、电容器、电源、节点等的情况下。在图中，为了清楚地示出，放大了区域的尺寸并省略了元件。贯穿全文，相同的附图标记表示相同的元件。
图1示出了无电镀操作的示意图。参考图1，所制造的半导体器件100可包括衬底102，例如具有部件116例如凸点116A和116B的半导体衬底102。部件116可以是用于向半导体器件100传入例如控制信号、数据、电源、地电势等信号或自其传出前述信号的导体。部件116例如可以是器件键合焊垫上的凸点。在一实施方式中，部件116例如可以是信号端子凸点116A和接地凸点116B。
半导体器件100还可以包括分别对应于凸点116A、116B的器件键合焊垫106。阱区124如掺杂杂质区可将凸点116A与衬底102隔离开。在一实施方式中，衬底102可掺杂有n型杂质，阱区124可掺杂有p型杂质。
半导体器件100还可包括设置在凸点116A和凸点116B之间的扩散阻挡层108。扩散阻挡层108电连接一个或多个凸点116A至一个或多个凸点116B。
扩散阻挡层108可用于使由阱区124隔离的凸点116A和未由阱区124隔离的凸点116B之间的电压电位一致(normalize)。在无电镀期间，扩散阻挡层108可降低或消除凸点116A和116B之间的电压电位。例如，当凸点116A是信号凸点、凸点116B是接地凸点时，通过允许电子经由扩散阻挡层108从接地凸点116B向信号凸点116A移动可使电压电位一致。
考虑到电子流经扩散阻挡层108，每个凸点116A和116B可具有相等或基本相等的电子供给，其能够使得无电镀反应在每个凸点116A和116B的表面上等同地发生，从而在每个凸点116A和116B上沉积等量的材料，如金属。因此，对于凸点116A和116B，无电镀工艺可产生具有基本一致厚度的镀层，与当不使凸点116A和116B之间电压电位一致时进行的无电镀工艺相比，这能改善半导体器件100的可靠性。
更特别地，当凸点116A和凸点116B之间不存在电连接时，凸点116A可能具有与凸点116B不同的电势。特别地，阱区124可将凸点116A与衬底102隔离，从而使衬底和凸点116A之间的电子流动不同于衬底102和凸点116B之间的电子流动。这可能导致凸点116A和凸点116B之间无电镀条件的变化。例如，同没有与衬底隔离的凸点116B相比，无电镀对凸点116A的效果更差。
图2A-2I示出了根据第一实施例制造半导体器件的方法中的步骤，包括在图1中所示的无电镀步骤之前和之后的步骤。在以后的描述中，将只描述凸点116A和116B中一个凸点的制造。然而，应当理解可以用相似方式进行凸点116A和116B中另一个的制造。因此，将不再重复凸点116A和116B中另一个的制造细节。
参考图2A，衬底102在其上可具有器件键合焊垫106。该键合焊垫106可处于衬底102的由杂质阱如上述的阱124隔离的区域内，或者可处于未被隔离的衬底102的区域内。如图2A所示，钝化层104可形成在衬底102上。钝化层104可部分地覆盖键合焊垫106。
参考图2B，扩散阻挡层108可形成在钝化层104上。扩散阻挡层108可包括钛、铬或铝中的一种或多种。在一实施方式中，扩散阻挡层108可包括钛-氮化合物或钛-钨化合物中的一种或多种。扩散阻挡层108可具有约3000
Figure G2008101446705D00051
的厚度。籽晶层110可形成在扩散阻挡层108上。籽晶层110可包括铜且可具有约2000
Figure G2008101446705D00052
的厚度。籽晶层110可用作在随后的操作中用于在键合焊垫106上形成部件116如凸点的籽晶金属层。例如，分别地，籽晶层110可包括Ni或Ni-Cu合金，稍后形成的部件116也可包括Ni或Ni-Cu合金。在一实施方式中(未示出)，在钛层用作扩散阻挡层108的情况下，籽晶层110可包括氮化钛层和在氮化钛层顶部上的铜层。
参考图2C，光致抗蚀剂层114可形成在衬底上，并被图形化以定义其中将形成部件116的区域。光致抗蚀剂层114可以用公知技术涂敷和构图，在此不再重复其细节。图形化的光致抗蚀剂层114可暴露出与键合焊垫106重叠的区域。
参考图2D，部件116可形成在由图形化的光致抗蚀剂层114定义的区域中。部件116可使用例如电镀或无电镀形成。部件116可以是镍、铜、铜-镍合金等。部件116可被形成为低于光致抗蚀剂层114的高度，或者可被形成为高于光致抗蚀剂层114的高度(未示出)。在任一种情况下，可进行平坦化工艺来平坦化部件116的上表面，如图2E所示。随后可去除光致抗蚀剂层114，如图2F所示。
参考图2G，籽晶层110的在去除光致抗蚀剂层114之后暴露出的部分可以例如采用蚀刻工艺等去除以暴露出其下的扩散阻挡层108。蚀刻工艺可以相对于扩散阻挡层108选择性地去除籽晶层110，从而扩散阻挡层108仍保留。选择性去除籽晶层110可留下籽晶层的在扩散阻挡层108和上方的部件116之间的部分110a。
在另一实施方式中，如上所述，籽晶层110可包括钛层，且扩散阻挡层108可包括氮化钛层和在氮化钛层顶部上的铜层。这种情况下，可去除铜顶层以暴露出氮化钛层，在该结构下可进行无电镀(以下将描述)。但是如果无电镀在氮化钛层上沉积材料，则氮化钛层也可被去除，无电镀可以对暴露出的钛层进行。
扩散阻挡层108可电连接部件116至相邻部件116。例如，再次参考图1，扩散阻挡层108可电连接设置在衬底102中阱区124内的凸点116A至设置在阱区124外的凸点116B。
在一实施方式中，可对扩散阻挡层108的暴露区域进行表面处理，以降低或消除在随后无电镀操作期间在其上的材料沉积。例如，可对扩散阻挡层108的暴露区域进行氧等离子体处理，例如达约60秒的持续时间，这将使暴露表面具有绝缘特性。氧等离子体处理可将扩散阻挡层108表面的薄层电阻增加约0.5％至约5％。以下的表1示出了示例氧等离子体除渣(de-scum)处理对3000
Figure G2008101446705D00061
厚度钛扩散阻挡层的薄层电阻率的影响：
表1
(作为扩散阻挡层的Ti(3000
Figure G2008101446705D00062
)的薄层电阻率(Ω/□))
  沉积态 除渣60秒*1次 除渣60秒*2次 除渣60秒*3次 4小时之后
平均 2.064  2.086  2.090  2.094  2.096
最大 2.137  2.161  2.166  2.169  2.172
最小 2.004  2.024  2.027  2.031  2.033
参考图2H，导电层122可形成在部件116表面上。导电层122可使用无电镀形成。无电镀可在部件116上以及在通过扩散阻挡层108电互连的一个或多个部件116上均匀地形成导电层122，。由此，在例如图1中示出的凸点116A和116B的情况下，无电镀可在设置于衬底102的阱区124中的凸点116A上以及阱区124之外的凸点116B上形成厚度基本均匀的导电层122。
导电层122可包括一层或多层的不同材料，或者可以是单层。例如，导电层122可包括：镍和金的双层，金的单层或多层，包括镍的多层，包括钯的多层，包括锡、锡合金、铟的单层或多层，等等。在一实施方式中，导电层122可包括镍层118和形成在镍层118上的金层120。在另一实施方式中，导电层122可包括钯层126、镍层118、第一金层120B和第二金层120A，如图2I所示。
例如，导电层122可包括作为最底部活性层的钯层126，厚度例如为约0.4μm的镍层118，通过置换反应工艺形成的厚度为约0.1μm的第一金层120B，和通过还原反应工艺形成的厚度为约0.3μm至约0.4μm的第二金层120A。详细地，可进行预清洗操作，之后使用例如催化剂处理可形成钯层126。随后，用作扩散阻挡层的镍层118可以使用例如约75℃至约90℃温度下的NiP镀覆形成。第一金层120B和第二金层120A可分别使用约65℃至约85℃温度下的金置换反应和金还原反应形成。每次操作之后，可使用去离子水进行清洗。在导电层122包括锡层的情况下，可在包括去离子水清洗之后使用过二硫酸钾(K2S2O8)软蚀刻的预清洗操作之后，使用无电镀在约60℃沉积锡。部件116的硬度可使用热处理操作来调整例如加热至约250℃的温度。
形成导电层122之后，扩散阻挡层108的暴露部分可以被去除，留下阻挡层的在钝化层104和籽晶层的上方的部分110a之间的部分108a。由于在形成导电层122之后去除扩散阻挡层108的暴露部分，因此导电层122可覆盖部件116并且可沿着部件116的侧面延伸，从而接触扩散阻挡层108的顶表面，如图2I所示。在一实施方式中，导电层122可直接接触扩散阻挡层108，且可直接接触在选择性去除暴露部分之后的扩散阻挡层的剩余部分108a。选择性去除扩散阻挡层108的暴露部分可留下具有与导电层122的外周基本对准的横向宽度的剩余部分108a。籽晶层的部分110a可被周围的导电层122、上面的部件116和扩散阻挡层的在其下面的部分108a完全封闭。去除扩散阻挡层108的暴露部分可以中断部件116之间的电通路。由此，扩散阻挡层108可用作扩散阻挡物并在无电镀期间提供电通路，在中断电通路之后可留下剩余部分108a，以用作所获器件中的扩散阻挡物。
现在结合图3A、3B和4A-4G描述第二实施例。在此实施例中，可将上述的部件116实施为半导体器件200上的布线图形，例如再分配图形(redistribution pattern)210。图3A示出了根据第二实施例的示例半导体器件的平面图。图3B示出了沿着图3A的线A-A取得的图3A的半导体器件的截面图。参考图3A，再分配图形210可再分配键合区域，从而例如外围键合焊垫206连接到相应的再分配键合焊垫212，该再分配键合焊垫212可形成在半导体器件200的内部区域中。
参考图3B，键合焊垫206可设置在衬底202上。钝化层204可设置在衬底202上并可部分地覆盖键合焊垫206。第一电介质层208可设置在衬底202上从而覆盖钝化层204并暴露出上覆键合焊垫206的区域。再分配图形210可设置成与钝化层204暴露出的区域中的键合焊垫206接触，并且可沿着第一电介质层208的表面向再分配键合焊垫212所在的区域延伸。第二电介质层228可覆盖第一电介质层208和再分配图形210，且可具有暴露再分配图形210的区域的开口以形成再分配键合焊垫212。焊料球214、凸点等可设置在再分配键合焊垫212上并且可提供与相邻衬底如印刷电路板等(未示出)的电接触。
可以以与上述部件116相似的方式形成再分配图形210。具体地，可以在通过扩散阻挡层216电连接多个再分配图形210的同时进行无电镀操作，以下将对此进行详细描述。由扩散阻挡层216提供的电连接可允许由此连接的再分配图形210的电位一致，这将改善形成在再分配图形210上的导电层的均匀性。
图4A-4G示出了制造以上结合图3A描述的、沿着图3A的线B-B取得的半导体器件200的方法各步骤的横截面图。参考图4A，钝化层204可形成在衬底202上。钝化层204可被图形化以暴露出部分键合焊垫206(见图3A和3B)。第一电介质层208可形成在衬底202上并可覆盖钝化层204。第一电介质层208可被图形化以暴露键合焊垫206。
扩散阻挡层216可形成在第一电介质层208和键合焊垫206的暴露部分上，且籽晶层218可形成在扩散阻挡层216上。在一实施方式中，扩散阻挡层216可包括Ti、Cr、Al、TiN和/或TiW，籽晶层218可包括Cu、Ni和/或Cu-Ni合金。在另一实施方式中，扩散阻挡层216和籽晶层218可包括Ti/TiN/Cu三层结构。
参考图4B，光致抗蚀剂层222可形成在籽晶层218上。光致抗蚀剂层222可被图形化以形成开口，该开口暴露出籽晶层218重叠在键合焊垫206上的部分，且其定义了其中将形成再分配图形210的沟槽。
参考图4C，形成再分配图形210(见图3A和3B)可包括在光致抗蚀剂层222的开口中电镀或无电镀材料以形成用于再分配图形210的芯图形(core pattern)224。该芯图形224可包括如Cu、Ni或Cu-Ni合金，并且可通过电镀或无电镀形成。在一实施方式中，可将铜镀到开口中达约3μm至5μm的厚度。所镀材料的厚度可大于或小于光致抗蚀剂层222的厚度，且所镀材料和光致抗蚀剂层222可以按以上结合图2E所述的相同方式被平坦化。之后可去除剩余的光致抗蚀剂层222，如图4D所示。
参考图4E，可使用例如蚀刻工艺从芯图形224周围选择性去除籽晶层218的因光致抗蚀剂层222的去除之后暴露出的部分，从而芯图形224以及籽晶层的剩余部分218a基本上有相同的边界。如以上结合第一实施例所述，相对于下面的扩散阻挡层216去除籽晶层218可以是选择性的，从而扩散阻挡层216保留并在示范性的再分配图形形成工艺中的此步骤中提供多个芯图形224之间的电通路。因此，可在芯图形224被电连接的同时进行在芯图形224上无电镀外部层的后续操作，同时电连接。由此，无电镀可用于制造具有镀于其上的厚度基本均匀的外部层的再分配图形210。
在一实施方式中，在进行无电镀之前可对扩散阻挡层216的表面进行氧等离子体处理，这可使扩散阻挡层216的薄层电阻增加例如约0.5％至约5％。
参考图4F，使用无电镀可以在芯图形224上镀覆外部导电层226。外部导电层226可具有例如约1μm至约3μm的厚度。如图4F所示，外部导电层226可以覆盖芯图形224的顶部和侧面，从而芯图形224不在再分配图形210中暴露。由于外部导电层226可防止芯图形224的氧化并且可防止铜扩散到相邻材料层中，所以这在例如铜芯图形224的情况下尤其有利。
导电层226可包括一层或多层的不同材料，或者可以是单层。例如，导电层226可包括镍和金的双层，金的单层或多层，包括镍的多层，包括钯的多层，包括锡、锡合金、铟的单层或多层，等等。在一实施方式中，导电层226可包括镍层和形成在镍层上的金层。在另一实施方式中，导电层226可包括钯层、镍层、第一金层和第二金层，与以上结合图2I所描述的结构相似。
例如，导电层226可包括作为最底部活性层(activation layer)的钯层，具有例如约0.4μm厚度的镍层，通过置换反应工艺形成的具有例如约0.1μm厚度的第一金层，和通过还原反应工艺形成的具有例如约0.3μm至约0.4μm厚度的第二金层。更详细地，可进行预清洗操作，之后可使用例如催化处理形成钯层。之后，例如在约75℃至约90℃温度下使用NiP镀覆形成用作扩散阻挡层的镍层。在约65℃至约85℃的温度下分别使用金置换反应和金还原反应形成第一和第二金层。在每一个操作之后，可使用去离子水进行清洗。这里，在导电层226中包括锡层的情况下，可在包括去离子水清洗之后使用过二硫酸钾(K2S2O8)的软蚀刻的预清洗操作之后，使用无电镀在约60℃沉积锡。部件的硬度可使用热处理操作来调整，例如加热到约250℃。
在无电镀之后，扩散阻挡层216的暴露部分被选择性去除，剩下扩散阻挡层的在第一电介质层208和籽晶层在其上的部分218a之间的部分216a。由此，以与上面结合图2A-2I所描述的第一实施例相似的方式，导电层226可覆盖铜芯图形224且可沿着铜芯图形224的侧面延伸以接触扩散阻挡层216的顶表面。在选择性去除暴露部分之后，导电层226可直接接触扩散阻挡层216，且可直接接触扩散阻挡层的剩余部分216a。选择性去除扩散阻挡层216的暴露部分会留下具有与导电层226外周基本对准的横向宽度的剩余部分216a。籽晶层的该部分218a可被周围的导电层226、上面的铜芯图形224和扩散阻挡层在其下面的部分216a完全封闭。去除扩散阻挡层216的暴露部分可以中断铜芯图形224之间的电通路。由此，扩散阻挡层216可用作扩散阻挡物并在无电镀期间提供电通路，和在中断电通路之后会保留剩余部分216a，以用作所获器件中的扩散阻挡物。
参考图4G，第二电介质层228可形成在衬底202上。第二电介质层228可被图形化以暴露出再分配图形210的外部导电层226的顶部，暴露部分对应于再分配键合焊垫212的位置(还是见图3B)。焊料球214、凸点等可设置在再分配键合焊垫212上从而能电连接到相邻的衬底或元件。
图5示出了根据第三实施例的示例存储卡系统700，如多媒体卡(MMC)或者安全数字(SD)卡。参考图5，卡700可包括控制器710和存储器720。存储器720可以是例如闪存、PRAM、DRAM等。提供接口用于在控制器710和存储器720之间交换数据和命令(指令)。提供另一个接口如标准MMC或SD接口用于与另一装置(未示出)交换信息。存储器720、控制器710和其间的接口可封装到一起作为多芯片封装(MCP)。
图6示出了根据第四实施例的示例电子系统800。参考图6，系统800可包括处理器810、存储器820、至少一个I/O(输入/输出)装置830、以及至少一条总线840。系统800例如可以是移动电话、MP3装置、导航系统、固态盘(SSD)、家用设备等。存储器820、处理器810、I/O装置830和总线840可封装到一起作为MCP。在一实施方式中，一个、一些或者所有部件(存储器820、处理器810和I/O装置840)可封装到一起，例如垂直堆叠到一起作为MCP。
图7示出了根据第五实施例的示例显示装置900。显示装置900可包括显示器90l和连接到该显示器的显示驱动集成电路902，例如使用各向异性导电膜903进行连接。显示器901可被设置为响应由显示驱动集成电路902提供的信号来再现图像。显示驱动集成电路902可包括衬底，例如半导体衬底，在其上具有至少两个部件916。衬底上的部件916可以是如上所述的具有外部导电层和分别设置在每个部件和衬底之间的扩散阻挡层的部件。衬底的第一杂质区含有第一类型杂质，衬底的第二杂质区含有不同于第一类型的第二类型的杂质。所述至少两个部件中的第一个部件处于第一杂质区中，所述至少两个部件中的第二部件处于第二杂质区中，从而通过所述不同杂质区第二部件与第一部件电隔离。每个相应的扩散阻挡层可横向延伸到相应导电层的外部边缘并且可被相应导电层暴露。
在此已经公开了示范性实施例，且尽管采用了具体术语，但是使用其且仅将其解释为一般的、描述性的含义，且并非为限制性目的。由此，尽管上面已经描述了具体实施例，由此使用无电镀方法镀覆了凸点和再分配图形，但是类似地，该方法可用于其它部件。而且，该方法可用于其中没有通过不同杂质区隔离的部件如凸点或布线图形的装置。例如，实施例可提供一种装置如在显示设备中的显示驱动集成电路，以及其制造方法，其中在衬底上形成扩散阻挡层，在衬底上形成至少两个部件从而扩散阻挡层分别设置在每个部件和衬底之间，扩散阻挡层电连接所述至少两个部件，外部导电层被无电镀到所述至少两个部件上，同时所述至少两个部件通过扩散阻挡层电连接，且扩散阻挡层被选择性去除以中断电连接。外部导电层可接触扩散阻挡层的顶表面，该方法包括，在形成所述至少两个部件之前，在对应于所述至少两个部件的区域中的扩散阻挡层上形成籽晶层，且对应于部件中一个的部分籽晶层通过外部导电层、部件和扩散阻挡层封闭。
因此，本领域技术人员将理解，在形式和细节上作出的各种变化不背离由下面的权利要求书所限定的本发明的精神和范围。
在此将2007年4月20日在韩国知识产权局提出的名为“用无电镀制造具有均匀涂层厚度的半导体器件的方法”的韩国专利申请10-2007-0038981通过引用的方式整体并入本文中。

Claims (24)

1.一种制造半导体器件的方法，包括：
在衬底上形成扩散阻挡层；和
在所述衬底上形成至少两个部件，从而所述扩散阻挡层分别设置在每个部件和所述衬底之间并接触所述至少两个部件，所述扩散阻挡层提供所述至少两个部件之间的电通路，
在所述至少两个部件通过所述电通路连接的同时，在所述至少两个部件上无电镀外部导电层；以及
在无电镀之后，处理所述扩散阻挡层从而中断所述电通路，
其中：
所述衬底的第一杂质区含有第一类型杂质，
所述衬底的第二杂质区含有不同于第一类型的第二类型杂质，
至少两个部件中的第一部件处于第一杂质区中，和
至少两个部件中的第二部件处于第二杂质区中，从而通过所述不同杂质区第二部件与第一部件电隔离。
2.如权利要求1所述的方法，其中处理所述扩散阻挡层从而中断所述电通路包括从包围所述至少两个部件中至少一个的区域去除所述扩散阻挡层。
3.如权利要求1所述的方法，其中，在中断所述电通路之后，所述扩散阻挡层横向延伸至所述导电层的外边缘并且被所述导电层暴露。
4.如权利要求1所述的方法，其中所述导电层镀覆在包括铜或镍中一种或多种的所述部件的表面上，
所述导电层包括镍、金、钯、锡或铟中的一种或多种，和
所述扩散阻挡层包括钛、铬或铝中的一种或多种。
5.如权利要求4所述的方法，其中所述导电层包括：
每个部件的表面上的钯层；
每个钯层上的镍层；和
每个钯层上的至少一个金层。
6.如权利要求1所述的方法，形成所述至少两个部件包括：
在形成所述扩散阻挡层之后和在无电镀之前，在所述衬底上形成籽晶层；
在所述籽晶层上选择性形成所述至少两个部件；和
从所述至少两个部件之间的区域选择性去除所述籽晶层。
7.如权利要求6所述的方法，其中所述至少两个部件通过电镀或无电镀形成。
8.如权利要求6所述的方法，其中选择性形成所述至少两个部件包括：
在所述衬底上形成光致抗蚀剂图形，该光致抗蚀剂图形具有对应于所述至少两个部件的开口，该开口暴露出所述籽晶层；
使用电镀在光致抗蚀剂图形中的开口中沉积材料；
平坦化所沉积材料以形成所述至少两个部件；
去除所述光致抗蚀剂图形；和
去除所述籽晶层的与至少两个部件相邻的在衬底上暴露出的部分。
9.如权利要求6所述的方法，其中所述籽晶层是导电的。
10.如权利要求1所述的方法，其中提供所述电通路的所述扩散阻挡层的一部分在无电镀期间是暴露的。
11.如权利要求10所述的方法，还包括，在无电镀之前，对提供所述电通路的所述扩散阻挡层的暴露部分进行氧等离子体表面处理。
12.如权利要求1所述的方法，还包括：
在所述至少两个部件的每个和所述衬底之间形成键合焊垫；
在所述衬底上形成钝化层，该钝化层覆盖所述键合焊垫的一部分并暴露出所述键合焊垫的一部分，其中所述扩散阻挡层接触由所述钝化层暴露出的所述键合焊垫的部分。
13.一种半导体器件，包括：
衬底；
在所述衬底上的至少两个部件，每个部件包括通过无电镀形成的外部导电层；和
扩散阻挡层，其分别设置在每个部件和所述衬底之间，其中：
所述衬底的第一杂质区含有第一类型杂质，
所述衬底的第二杂质区含有不同于所述第一类型的第二类型杂质，
所述至少两个部件中的第一部件处于所述第一杂质区中，
所述至少两个部件中的第二部件处于所述第二杂质区中，从而通过不同杂质区所述第二部件与所述第一部件电隔离，和
每个各自的扩散阻挡层都横向延伸到相应的外部导电层的外部边缘并且被相应的外部导电层暴露。
14.如权利要求13所述的半导体器件，其中所述外部导电层接触所述扩散阻挡层的顶表面。
15.如权利要求13所述的半导体器件，其中每个部件包括具有不同于所述外部导电层的组分的芯材。
16.如权利要求15所述的半导体器件，其中所述芯材包括铜或镍中的一种或多种。
17.如权利要求13所述的半导体器件，其中所述外部导电层包括镍、金、钯、锡或铟中的一种或多种。
18.如权利要求13所述的半导体器件，其中所述扩散阻挡层包括钛、铬或铝中的一种或多种。
19.如权利要求18所述的半导体器件，其中所述扩散阻挡层包括钛-氮化合物或钛-钨化合物中的一种或多种。
20.如权利要求13所述的半导体器件，其中所述至少两个部件是被构造为在所述半导体器件和第二衬底之间提供电信号的凸点。
21.如权利要求13所述的半导体器件，其中所述至少两个部件是布线导线。
22.一种显示装置，包括：
显示器和连接到该显示器的显示驱动集成电路，其中：
所述显示器被设置为响应显示驱动集成电路提供的信号来再现图像，和
显示驱动集成电路包括：
衬底；
在所述衬底上的至少两个部件，每个部件包括通过无电镀形成的外部导电层；知
分别设置在每个部件和所述衬底之间的扩散阻挡层，其中：
所述衬底的第一杂质区含有第一类型杂质，
所述衬底的第二杂质区含有不同于第一类型的第二类型杂质，
所述至少两个部件中的第一部件处于第一杂质区中，
所述至少两个部件中的第二部件处于第二杂质区中，从而通过所述不同杂质区所述第二部件与第一部件电隔离，和
每个相应扩散阻挡层都横向延伸到相应的外部导电层的外部边缘并被相应的外部导电层暴露。
23.一种制造半导体器件的方法，该方法包括：
在衬底上形成扩散阻挡层；
在所述衬底上形成至少两个部件从而扩散阻挡层分别设置在每个部件和所述衬底之间，扩散阻挡层电连接所述至少两个部件；
在所述至少两个部件被扩散阻挡层电连接的同时，在所述至少两个部件上无电镀外部导电层；和
选择性去除扩散阻挡层以中断电连接。
24.一种半导体器件，包括：
衬底；
在所述衬底上的第一部件和第二部件；
在所述衬底和所述第一部件之间的第一扩散阻挡物；
在所述第一部件上的通过无电镀形成的第一导电层；
在所述衬底和所述第二部件之间的第二扩散阻挡物；和
在所述第二部件上的通过无电镀形成的第二导电层，其中：
所述第一导电层接触所述第一扩散阻挡物的顶表面，和
所述第二导电层接触所述第二扩散阻挡物的顶表面。
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