CN100536101C - 半导体装置及其制造方法 - Google Patents
半导体装置及其制造方法 Download PDFInfo
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- CN100536101C CN100536101C CNB2004100619573A CN200410061957A CN100536101C CN 100536101 C CN100536101 C CN 100536101C CN B2004100619573 A CNB2004100619573 A CN B2004100619573A CN 200410061957 A CN200410061957 A CN 200410061957A CN 100536101 C CN100536101 C CN 100536101C
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- connecting portion
- basalis
- semiconductor device
- substrate
- resin bed
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Abstract
本发明提供一种相对于电路基板及电子机器,有效地缓和施加在配线层或外部端子上的应力的半导体装置及其制造方法。半导体装置包括:形成了集成电路(12)的半导体基板(10)、具有线路部(22)和与其连接的连接部(24)的配线层(20)、配线层(20)的基底层(30),而连接部(24)具有与基底层(30)接触而成的第1部分(26)和与基底层(30)未接触而成的第2部分(28)。
Description
技术领域
本发明涉及半导体装置及其制造方法。
背景技术
在将半导体装置面朝下地安装在基板上时,重要的是缓和施加在由焊锡等构成的外部端子上的应力。以往,采用在应力缓和层(树脂层)上形成外部端子的结构,无法得到充分的效果。特别是,期待着用以晶片为单位进行封装的晶片级CSP(Chip Size/Scale Package),来提高可靠性。
发明内容
本发明的目的在于,提供一种有效地缓和施加在配线层或外部端子上的应力的半导体装置及其制造方法。
(1)本发明的半导体装置,包括:形成了集成电路的半导体芯片;装载了所述半导体芯片的基板;具有位于所述基板上的线路部及与其连接并位于所述基板上的连接部,并形成于所述基板上的配线层;和所述配线层的基底层,
所述连接部具有与基底层接触而成的第1部分和与所述基底层未接触而成的第2部分。
根据本发明,连接部的第2部分与基底层未接触。即,连接部的第2部分的正下方没有形成基底层。因而,能够使连接部追从来自外部的应力,变形或工作,从而可以有效地缓和应力。
(2)本发明的半导体装置包括:形成了集成电路的半导体基板;形成于所述半导体芯片上的树脂层;具有位于所述树脂层上的线路部及与其连接并位于所述树脂层上的连接部,形成于所述树脂层上的配线层;和所述配线层的基底层,
所述连接部具有:与基底层接触而成的第1部分和与所述基底层未接触而成的第2部分。
根据本发明,连接部的第2部分与基底层未接触。即,连接部的第2部分的正下方没有形成基底层。因而,能够使连接部追从来自外部的应力,变形或工作,从而可以有效地缓和应力。
(3)在该半导体装置中,所述连接部的所述第2部分可以配置为从所述树脂层开始空出间隔。利用树脂层,可以缓和施加在连接部上的应力。
(4)在该半导体装置中,还可以包括在覆盖所述线路部的同时,具有露出所述连接部一部分的开口部的绝缘层。
(5)在该半导体装置中,可以在所述树脂层和所述连接部的所述第2部分的间隔中填充所述绝缘层。由此,在绝缘层比基底层还柔软时,可以更加提高连接部的自由度,以缓和应力。
(6)在该半导体装置中,所述连接部的所述第1部分的宽度,可以比从所述连接部的所述绝缘层露出的部分的宽度还小。由此,相对于施加在连接部的露出部的应力,更提高连接部的自由度,可以有效地缓和应力。
(7)在该半导体装置中,还可以包括在覆盖所述线路部的同时,具有露出所述连接部全部的开口部的绝缘层。
(8)在该半导体装置中,所述连接部可以在中央部具有所述第1部分,而在端部具有所述第2部分。由此,连接部能够以其平面形状的中心为轴倾斜并工作,且可以缓和施加在连接部上的应力。
(9)在该半导体装置中,所述连接部的所述第1部分的平面形状,可以是沿所述线路部的延伸方向形成为细长状。由此,例如可以容易地使连接部以线路部的延长线为轴倾斜并工作。因此,可以防止线路部及连接部的连接部的断线。
(10)在该半导体装置中,所述基底层可以只作为所述连接部的基底而形成。
(11)在该半导体装置中,所述基底层,可以作为所述线路部和所述连接部的基底而形成。
(12)在该半导体装置中,所述基底层的厚度可以比所述配线层的厚度还大。由此,因为可以扩大连接部的第2部分正下方的空间,故进一步提高连接部的自由度。
(13)在该半导体装置中还包括设置在所述连接部上的外部端子。由此,可以增加外部端子的自由度,且相对于施加在外部端子根部上的应力,更加提高连接部和外部端子的自由度,有效地缓和应力。
(14)本发明的半导体装置制造方法包括:
(a)在基板上形成导电层的工序;
(b)将具有位于所述基板上的线路部及与其连接并位于所述基板上的连接部的配线层形成在所述基板上,以便至少使所述连接部将所述导电层作为基底的工序;
(c)对所述导电层进行比所述连接部区域更大的过蚀刻,以形成基底层的工序;和
(d)将形成了集成电路的半导体芯片装载在所述基板上的工序,
所述连接部具有:与基底层接触而成的第1部分和与基底层未接触而成的第2部分。
根据本发明,连接部的第2部分与基底层未接触。即,在连接部的第2部分的正下方没有形成基底层。因而,可以使连接部追从来自外部的应力变形或工作,从而可以有效地缓和应力。
(15)本发明的半导体装置制造方法包括:
(a)在形成了集成电路的半导体基板上形成树脂层,在所述树脂层上形成导电层的工序;
(b)将具有位于所述树脂层上的线路部及与其连接并位于所述树脂层上的连接部的配线层形成在所述树脂层上,以便至少使所述连接部将所述导电层作为基底的工序;和
(c)对所述导电层进行比所述连接部区域更大的过蚀刻,以形成基底层的工序,
所述连接部具有:与基底层接触而成的第1部分和与基底层未接触而成的第2部分。
根据本发明,连接部的第2部分与基底层未接触。即,在连接部的第2部分的正下方没有形成基底层。因而,可以使连接部追从来自外部的应力变形或工作,从而可以有效地缓和应力。
(16)本发明的半导体装置制造方法包括:
(a)在基板上形成基底层的工序;
(b)避开所述基板的所述基底层而在其周边区域形成平整层的工序;
(c)将具有位于所述平整层上的线路部及与其连接并位于所述基底层及所述平整层上的连接部的配线层形成在所述基底层及所述平整层上,以便使所述连接部具有与基底层接触而成的第1部分和与基底层未接触而成的第2部分的工序;和
(d)将已形成集成电路的半导体芯片装配在所述基板上的工序。
根据本发明,连接部的第2部分与基底层未接触。即,没有在连接部的第2部分的正下方形成基底层。因而,可以使连接部追从来自外部的应力变形或工作,从而可以有效地缓和应力。
(17)本发明的半导体装置制造方法包括:
(a)在形成了集成电路的半导体基板上形成树脂层,在所述树脂层上形成基底层的工序;
(b)避开所述树脂层的所述基底层而在其周边区域形成平整层的工序;和
(c)将具有位于所述平整层上的线路部及与其连接并位于所述基底层及所述平整层上的连接部的配线层形成在所述基底层及所述平整层上,以便使所述连接部具有与基底层接触而成的第1部分和与基底层未接触而成的第2部分的工序。
根据本发明,连接部的第2部分与基底层未接触。即,没有在连接部的第2部分的正下方形成基底层。因而,可以使连接部追从来自外部的应力变形或工作,从而可以有效地缓和应力。
(18)在本发明的半导体装置制造方法中,还可以包括在所述(c)工序后除去所述平整层的工序。
附图说明
图1是表示本发明的第1实施方式的半导体装置的图。
图2是表示图1的II-II线剖面图。
图3是表示图1的III-III线剖面图。
图4是说明本发明的第1实施方式的半导体装置的图。
图5是说明本发明的第1实施方式的变形例的半导体装置的图。
图6是说明本发明的第1实施方式的变形例的半导体装置的图。
图7是说明本发明的第1实施方式的变形例的半导体装置的图。
图8是说明本发明的第1实施方式的变形例的半导体装置的图。
图9A~图9D是表示本发明的第1实施方式的半导体装置的制造方法的图。
图10A~图10D是表示本发明的第2实施方式的半导体装置的制造方法的图
图11A~图11D是表示本发明的第2实施方式的半导体装置的制造方法的图。
图12A及图12B是表示本发明的第2实施方式的变形例的半导体装置的制造方法的图。
图13是表示本发明的第3实施方式的半导体装置的图。
图14是表示本发明的第4实施方式的半导体装置的图。
图15是表示本发明的第5实施方式的半导体装置的图。
图16是表示本发明的第5实施方式的半导体装置的图。
图17是表示本发明的实施方式的电路基板的图。
图18是表示本发明的实施方式的电子机器的图。
图19是表示本发明的实施方式的电子机器的图。
具体实施方式
下面,参照附图,对本发明的实施方式进行说明。
(第1实施方式)
图1~图9D是表示本发明的第1实施方式的半导体装置及其制造方法的图。图1是省略了半导体装置的一部分(绝缘层34及覆盖层38等)的俯视图,图2是图1的II-II线剖面图,图3是图1的III-III线剖面图。图4是配线层及基底层的俯视图。
本实施方式的半导体装置具有半导体基板10。半导体基板10可以是图1所示的半导体芯片,或者可以是半导体晶片。如图2所示,在半导体基板10上形成集成电路12,并形成有与集成电路12电连接的多个电极(例如垫片pad)14。在半导体芯片上形成有一个集成电路12、一组的多个电极14。在半导体晶片上形成多个集成电路12、多组的多个电极14。如图1所示,多个电极14可以沿着半导体芯片(若为半导体晶片,则是在单片后成为半导体芯片的区域)的端部(例如相对的2边或4边)进行排列。在半导体基板10的表面(已形成电极14的面)上形成有钝化膜(例如SiN、SiO2、MgO)16。
在半导体装置10的形成电极14的面(例如钝化膜16上)上形成有至少由一层构成的树脂层18。树脂层18避开电极14而形成。如图1所示,树脂层18可以形成在由电极14包围的范围内。树脂层18可以形成为侧面倾斜的形状,以使其反面(底面)比上面还大。树脂层18可以具有应力缓和功能。树脂层18可以由聚酰亚胺树脂、硅改性聚酰亚胺树脂、环氧树脂、硅改性环氧树脂、苯并环丁烯(BCB;benzo cyclobutene)、聚苯并恶唑(polybenzoxazole)等树脂形成。
半导体装置具有配线层20。配线层20形成在半导体基板10的电极14侧。配线层20是导电层(例如铜(Cu)层),并形成为单层或多层。配线层20与电极14电连接。如图2所示配线层20可以重叠(over lap)在电极14上。配线层20延伸至树脂层18的上面。
如图1所示,配线层20具有线路部22及与线路部22连接的连接部24。线路部22和连接部24形成为一体。线路部22从电极14延伸至连接部24。连接部24是电连接部。连接部22可以呈直线状延伸,也可以弯曲。连接部24设于树脂层18上。可以在连接部24中设置外部端子32。连接部24的平面形状的宽度比线路部22的宽度还大。连接部24的平面形状多为圆形,但也不限于这一种形状。线路部22和连接部24的连接部的平面形状的宽度可以比线路部22的平面形状的宽度还大。
如图2所示,半导体装置包括配线层20的基底层30。基底层30成为配线层20的基底。基底层30形成于连接部24的一部分的正下方。基底层30也可以形成于线路部22的全部或一部分(例如,比线路部22还细的区域)的正下方。基底层30可以是导电层,并形成为单层或多层。基底层30可以包括阻挡层(barrier)。阻挡层防止配线层20或后述的晶种层(seed)扩散到树脂层18等。阻挡层可以由例如钛(Ti)、铬(Cr)、镍(Ni)、钛钨(TiW)等形成。用电镀方式形成配线层20时,基底层30可以包含晶种层。晶种层形成于阻挡层上。晶种层以与配线层20相同的材料(例如铜(Cu))形成。基底层30的厚度可以与配线层20的厚度同样或者比其还小。
半导体装置可以具有外部端子32。外部端子32与配线层20电连接。可以在连接部24上形成外部端子32。外部端子32是具有导电性的金属(例如合金),且使其熔化以用来达到电连接目的的物质(如焊锡)。外部端子32可以由软焊料(soft solder)或是硬焊料(hard solder)中任何一种形成。外部端子32可以形成为球状,例如可以是焊锡球。
在半导体基板10上形成有绝缘层(例如焊锡抗蚀剂层)34。绝缘层34覆盖配线层20的一部分。也可以用绝缘层34覆盖配线层20中、设置了外部端子32的部分以外的全部。由此,可以防止配线层20的氧化、腐蚀、电学的不良。绝缘层34可以不包括连接部24的一部分(例如中央部)而形成。即,绝缘层34可以具有露出连接部24的一部分(例如中央部)的开口部36。绝缘层34可以覆盖连接部24的端部。如图4所示,开口部36的平面形状(连接部24的露出部的平面形状)可以是连接部24的平面形状的相似形状(例如圆形)。外部端子32可以形成于开口部36内(连接部24的露出部)。绝缘层34可以覆盖线路部22及连接部24的连接部。由此,可以防止线路部22及连接部24的连接部的断线。
可以在绝缘层34上设置覆盖层38。覆盖层38具有绝缘层,例如可以由树脂形成。覆盖层38也覆盖外部端子32的根部(下端部)。覆盖层38具有形成于绝缘层34上的部分和从这个部分上升并覆盖外部端子32的根部的部分。由覆盖层38至少加固外部端子32的根部。在将半导体装置安装到电路基板之后,可以通过覆盖层38,缓和施加在外部端子32上的应力。
如图3所示,连接部24具有与基底层30接触而形成的第1部分26和与基底层30未接触而形成的第2部分28。即,第1部分26与基底层30重叠(overlap),而第2部分28未与基底层30重叠。由此,由于连接部24的第2部分28的正下方没有形成基底层30,故可以使连接部24追从应力变形或工作,从而能有效地缓和应力。可以将第1部分26配置在连接部24的中央部,将第2部分28配置在连接部24的端部。由此,连接部24能够将其平面形状的中心作为轴倾斜并工作,且可以缓和施加在连接部24上的应力。另外,在连接部24上设置了外部端子32的情况下,可以增加外部端子32的自由度,同时减少施加在外部端子32的根部上的应力。如图4所示,可以在除了线路部22和连接部24的连接部之外的第1部分26的整个周边配置第2部分28。此时,可以在第1部分26的整个周边上,具有大致一定的宽度地配置第2部分28(不包括线路部22和连接部24的连接部附近)。在隔着基底层30将连接部24形成于树脂层18上时,连接部24的第2部分28配置为从树脂层18空出间隔。如图3所示,可以在该间隔中填充绝缘层34。由此,在绝缘层34比基底层30还柔软的情况下,可以进一步提高连接部24的自由度,并缓和应力。
如图3或图4所示,第1部分26的平面形状的宽度(例如最大宽度)A和连接部24的露出部的平面形状(开口部36的平面形状)的宽度(例如最大宽度)B之间优选具有:
A<B
的关系。由此,通过在连接部24和外部端子32的接触部分的内侧配置基底层30,从而相对于施加在连接部24的露出部上的应力(施加在外部端子32的根部上的应力),可以进一步提高连接部24和外部端子32的自由度,并有效地缓和应力。第1部分26的平面形状可以是连接部24的平面形状的相似形状(例如圆形)。第1部分26的平面形状可以是开口部36的平面形状的相似形状(例如圆形)。
图5~图8是表示本实施方式的半导体装置的变形例的图,是配线层及基底层的俯视图。在下面的变形例中,省略了上述实施方式中已说明的内容。
如图5的变形例所示,连接部50的平面形状可以是方形(例如四角形)。此时,基底层30接触的第1部分26的平面形状可以是开口部36的平面形状的相似形状(如圆形)。
如图6的变形例所示,基底层52可以仅作为连接部24的基底而形成。基底层52可以仅形成于连接部24的一部分的正下方。在本变形例中,基底层52未形成于线路部22的正下方。基底层52的其他构成可应用基底层30的内容。在图6所示的例子中,在第1部分26的整个周边配置有第2部分28。
如图7及图8所示,第1部分54的平面形状沿线路部22的延伸方向细长地形成。例如,第1部分54的平面形状可以成为椭圆形或长方形。由此,可确保第2部分56的横向宽度(线路部22的宽度方向的宽度)比纵向宽度(线路部22的延伸方向的宽度)还大,连接部24将线路部22的延长线作为轴倾斜,容易工作。因此,可以防止配线层20(详细地说,是线路部22和连接部24的连接部)的断线。如图7所示,基底层58可以形成于线路部22的一部分的正下方。或者,如图8所示,基底层60可以仅形成于连接部24的一部分的正下方。
本实施方式的半导体装置具有如上所述的构成,并可以有效地缓和施加在配线层20或外部端子32上的应力。其详细的效果如同已经说明的那样。
接着,对本实施方式的半导体装置的制造方法进行说明。如图9A所示,在形成了集成电路(参照图2)、形成了钝化膜16的半导体基板10上形成导电层62。导电层62可以形成于半导体基板10上已形成电极(参照图2)的面侧。导电层62可以形成为与电极电连接(例如被电极重叠)。可以在半导体基板10(钝化膜16)上形成树脂层18,并在树脂层18及除此之外的钝化膜16的全部区域上形成导电层62。导电层62可以利用溅射、镀(电镀或无电解电镀)或它们的组合而形成。或者,可以采用喷墨方式或印刷方式形成导电层62。导电层62成为配线层20的基底层30(参照图9D)。
如图9B所示,形成配线层20。也可以应用光刻技术形成配线层20。例如,可以将抗蚀剂层64进行图案形成,使之具有开口部66,以在露出于开口部66内的导电层62的部分上形成配线层20。配线层20可以利用镀(例如电镀)的方法形成。可以将导电层62作为供电层进行电镀,从而形成配线层20。将配线层20进行图案形成,以便具有线路部(参照图2)和连接部24。也可以将线路部和连接部24两者(即配线层20的全部)形成为将导电层62作为基底。在进行电镀时,在连接部24整体的正下方配置导电层62。在形成了抗蚀剂层64时,之后如图9C所示,除去抗蚀剂层64。由此,可以在导电层62上形成配线层20。也可以与所述的不同,采用喷墨方式、印刷方式等形成配线层20。配线层20形成为:至少连接部24将导电层62作为基底。
如图9D所示,对导电层62进行比连接部24的还大区域的过蚀刻,以形成基底层30。即,对蚀刻量进行控制(例如通过时间),以使腐蚀剂进入到比连接部24区域还内侧。可以通过湿式蚀刻形成基底层30。如图9D所示,也可以在腐蚀剂(例如蚀刻液)中掺进表面活性剂(例如肥皂),以使腐蚀剂易于进入连接部24和树脂层18(或是钝化膜16)的间隔内。这样,可以形成具有接触基底层30而成的第1部分26和未接触基底层30而成的第2部分28的连接部24。如图9D所示,第1部分26可以配置在连接部24的中央部,第2部分28配置在连接部24的端部。而且,同样可以对导电层62的成为线路部的基底的部分进行过蚀刻,或者可以沿着线路部的区域对其进行适当蚀刻(just eching)。然后,可以根据需要,形成绝缘层34、外部端子32以及覆盖层38(参照图3)。
也可以对作为半导体晶片的半导体基板10,应用上述工序。此时,在完成上述工序之后,按每个集成回路12切断半导体装置10。由此,可以将具有半导体芯片的多个半导体装置形成单片。由此,由于以晶片为单位进行封装,故生产率高。另外,关于其他的事项,在本实施方式的半导体装置的制造方法中,与对上述半导体装置进行说明的内容相对应。
(第2实施方式)
图10A~图11D是表示本发明的第2实施方式的半导体装置的制造方法的图,图12A和图12B是表示半导体装置的制造方法的变形例的图。
首先,在半导体基本10上形成基底层30(参照图10C)。例如,如图10A所示,在半导体基板10的形成电极的面侧形成导电层70,如图10B所示,例如采用蚀刻(例如干式蚀刻或湿式蚀刻)除去导电层70的一部分。可以采用光刻技术,用抗蚀剂层72覆盖导电层70的一部分,再除去导电层70的剩下部分。之后,除去抗蚀剂层72,如图10C所示形成基底层30。另外,作为导电层70的形成方法,也可以采用第1实施方式中说明过的导电层62的形成方法。
接着,如图10D所示,避开基底层30,在其周边区域上形成平整层74。周边区域可以是包围基底层30的区域。平整层74可以与基底层30的外壁面密接。通过形成平整层74,从而可以消除(或是减少)基底层30和其周边区域间的高度差,使配线层90易于形成。
接着,形成配线层90(参照图11D)。首先,如图11A所示,形成第1导电层76。第1导电层76是用来通过电镀形成后述的第2导电层82的供电层,其详细说明可以采用第1实施方式中说明过的导电层62的内容。
如图11B所示,在第1导电层76上形成第2导电层82。例如,可以采用光刻技术对抗蚀剂层78进行图案形成,以便具有开口部80,并在露出于开口部80内的第1导电层76的部分上形成第2导电层82。第2导电层82的详细内容,可以采用第1实施方式中说明过的配线层20的内容。
然后,如图11C所示,除去抗蚀剂层78,并将第1导电层76的非必要部分,例如利用蚀刻而除去。可以对第1导电层76进行图案形成,以使其具有与在所述的工序中进行过图案形成的第2导电层82的平面形状相同的平面形状。
由此,如图11D所示,可以形成由第1及第2导电层82、84构成的多层配线层90。配线层90具有线路部和与其连接的连接部92。而且,连接部92具有与基底层30接触而成的第1部分86和与基底层30未接触而成的第2部分88。如图11D所示,可以除去平整层74。此时,也可以除去平面化层74中介于第2部分88和树脂层18之间的部分。也可以在第2部分88和树脂层18的间隔中形成其他材料(例如绝缘层34(参照图3))。作为变形例,可以不除去平整层74,而将其保留。也可以至少在第2部分88和树脂层18的间隔中保留平整层74。这种情况下,平整层74优选用比基底层30还柔软的材料形成。由此,利用平整层74,可以提高连接部92或设置在其上的外部端子的自由度,缓和应力。平整层74例如可以是树脂(例如与所述的树脂层18是同一材料),最好具有应力缓和功能。
如图12A和12B的变形例所示,避开基底层30,在其周边区域内形成平整层74(参照图10D)之后,形成配线层100。在本变形例中,通过实施无电解电镀(例如无电解铜镀),从而形成配线层100。如图12A所示,可以不形成抗蚀剂层(掩模),而是形成剖面为蘑菇状(mushroom)的配线层100。或者,可以形成抗蚀剂层(掩模),再沿着抗蚀剂层开口部的内壁,形成剖面为蘑菇状的配线层100。配线层100具有线路部和与其连接的连接部102,而连接部102具有与基底层30接触而成的第1部分94和与基底层30未接触而成的第2部分96。另外,如图12B所示,可以除去平整层74,或者也可以不除去而保留其。其他的详细内容,可以采用上述内容。
(第3实施方式)
图13是表示本发明的第3实施方式的半导体装置的图。在本实施方式中,取代基底层30,而形成基底层130。基底层130的厚度比配线层(例如连接部24)的厚度还大。基底层130可以利用无电解电镀(例如无电解镍电镀)形成。由此,与利用溅射而形成时相比,易于形成厚的层。或者,还可以在采用溅射而形成的薄膜上实施无电解电镀,再形成比配线层还厚的基底层130。根据本实施方式,由于可以扩大连接部24的第2部分28的正下方的空间(例如第2部分28及树脂层18的间隔),故可以提高连接部24或外部端子32的自由度,并有效地缓和应力。其他的详细内容,可以采用上述内容。
(第4实施方式)
图14是表示本发明的第4实施方式的半导体装置的图。在本实施方式中,取代绝缘层34,而形成有绝缘层134。绝缘层134形成为除去连接部24的全部。即,绝缘层134具有露出连接部24全部的开口部136。开口部136的平面形状可以是连接部24的平面形状的相似形状(例如圆形)。外部端子32是开口部136的内侧,可以设置为与连接部24的全部接触。由于在本实施方式中,在连接部24的第2部分28的正下方也没有形成基底层30,故可以有效地缓和应力。另外,在设置覆盖层38时,可以在第2部分28和树脂层18的间隔内填充覆盖层38。覆盖层38可以用比基底层30还柔软的材料形成。其他的详细情况,可采用上述内容。
(第5实施方式)
图15及图16是表示应用了本发明的第5实施方式的半导体装置的图。图15是图16所示的半导体装置的部分放大图。本实施方式的半导体装置包括:半导体芯片200、装载了半导体芯片200的基板210、形成于基板(例如插入物interposer)210的配线层220和配线层220的基底层230。
在半导体芯片200上,形成集成电路202,并形成有与集成电路202电连接的多个电极204。电极204可以包含垫片和其上的突出(bump)。半导体芯片200可以倒装焊接(facedown bonding)或是正面焊接(face upbonding)在基板210上。在倒装焊接时,可在半导体芯片200和基板210之间填充底层填料(多数情况下是树脂)206。可以在基板210的两个面上形成配线层220。此时,配线层220包含了用于和基板210的各面导通的通孔。装配半导体芯片200,配线层220与集成电路202电连接。
配线层220具有线路部222及与线路部222连接的连接部224。连接部224可以配置于基板210的与半导体芯片200相反的面侧。在配线层220(例如连接部224)上,可以设置有外部端子232。配线层220的基底层230可以形成在基板210的表面上。可以在基板210上形成导电层和其上的配线层220之后,对导电层进行比连接部224区域还大的过蚀刻,以形成基底层230(参照图9A~9D)。或者,可以在基板210上形成基底层230,并避开基底层230而在其周边区域形成平整层(图中未示出),再在基底层230及平整层上形成配线层220(参照图10A~12B)。平整层可以除去,也可以保留。另外,也可以在基板210上形成覆盖配线层220的一部分的绝缘层234。在图15所示的例子中,绝缘层234具有露出连接部224的一部分(例如中央部)的开口部236。配线层220、基底层230以及绝缘层234的详细情况,可以采用上述内容。
如图15所示,连接部224具有与基底层230接触而成的第1部分226和与基底层230未接触而成的第2部分228。由于在本实施方式中,在连接部224的第2部分228的正下方也没有形成基底层230,故连接部224可以追从应力进行变形或工作,从而可以有效地缓和应力。此外,其他的详细情况,可以应用上述内容(第1~第4实施方式所说明的内容(包括变形例))。
图17中展示了安装了本发明的实施方式的半导体装置1的电路基板1000。作为具有本发明的实施方式的半导体装置的电子机器,图18中展示了笔记本型个人计算机2000,而图19中展示了移动电话3000。
本发明并未限于上述实施方式,能够进行各种变形。例如,本发明包括与在实施方式中说明过的构成实质上相同的构成(例如,功能、方法以及结果相同的构成,或者目的和结果相同的构成)。另外,本发明包括对实施方式中说明过的构成中的非本质的部分进行了置换的构成。此外,本发明还包括可以达到与实施方式中所说明的构成同样的作用效果的构成,或可以达到同样目的的构成。再有,本发明包括在实施方式所说明的构成中附加了公知技术的构成。
Claims (18)
1.一种半导体装置,其特征在于,包括:
形成了集成电路的半导体芯片;
装载了所述半导体芯片的基板;
具有位于所述基板上的线路部及与其连接并位于所述基板上的连接部,并形成于所述基板上的配线层;和
所述配线层的基底层,
所述连接部具有与所述基底层接触而成的第1部分和与所述基底层未接触而成的第2部分。
2.一种半导体装置,其特征在于,包括:
形成了集成电路的半导体基板;
形成于所述半导体芯片的树脂层;
具有位于所述树脂层上的线路部及与其连接并位于所述树脂层上的连接部,并形成于所述树脂层上的配线层;和
所述配线层的基底层,
所述连接部具有:与所述基底层接触而成的第1部分和与所述基底层未接触而成的第2部分。
3.根据权利要求2所述的半导体装置,其特征在于,
所述连接部的所述第2部分配置为从所述树脂层开始空出间隔。
4.根据权利要求1~3中任一项所述的半导体装置,其特征在于,还包括在覆盖所述线路部的同时,具有露出所述连接部的一部分的开口部的绝缘层。
5.根据权利要求4所述的半导体装置,其特征在于,在所述树脂层和所述连接部的所述第2部分的间隔中填充所述绝缘层。
6.根据权利要求4所述的半导体装置,其特征在于,所述连接部的所述第1部分的宽度比从所述连接部的所述绝缘层露出的部分的宽度还小。
7.根据权利要求1~3中任一项所述的半导体装置,其特征在于,还包括在覆盖所述线路部的同时,具有露出所述连接部的全部的开口部的绝缘层。
8.根据权利要求1~3中任一项所述的半导体装置,其特征在于,所述连接部在中央部具有所述第1部分,而在端部具有所述第2部分。
9.根据权利要求1~3中任一项所述的半导体装置,其特征在于,所述连接部的所述第1部分的平面形状,沿所述线路部的延伸方向形成为细长状。
10.根据权利要求1~3中任一项所述的半导体装置,其特征在于,所述基底层只作为所述连接部的基底而形成。
11.根据权利要求1~3中任一项所述的半导体装置,其特征在于,所述基底层作为所述线路部及所述连接部的基底而形成。
12.根据权利要求1~3中任一项所述的半导体装置,其特征在于,所述基底层的厚度比所述配线层的厚度还大。
13.根据权利要求1~3中任一项所述的半导体装置,其特征在于,还包括设置在所述连接部上的外部端子。
14.一种半导体装置的制造方法,其特征在于,包括:
(a)在基板上形成导电层的工序;
(b)将具有位于所述基板上的线路部及与其连接并位于所述基板上的连接部的配线层形成在所述基板上,,以便至少使所述连接部将所述导电层作为基底的工序;
(c)对所述导电层进行比所述连接部区域更大的过蚀刻,以形成基底层的工序;和
(d)将形成了集成电路的半导体芯片装载在所述基板上的工序,
所述连接部具有:与所述基底层接触而成的第1部分和与所述基底层未接触而成的第2部分。
15.一种半导体装置的制造方法,其特征在于,包括:
(a)在形成了集成电路的半导体基板上形成树脂层,在所述树脂层上形成导电层的工序;
(b)将具有位于所述树脂层上的线路部及与其连接并位于所述树脂层上的连接部的配线层形成在所述树脂层上,以便至少使所述连接部将所述导电层作为基底的工序;和
(c)对所述导电层进行比所述连接部区域更大的过蚀刻,以形成基底层的工序,
所述连接部具有:与所述基底层接触而成的第1部分和与所述基底层未接触而成的第2部分。
16.一种半导体装置的制造方法,其特征在于,包括:
(a)在基板上形成基底层的工序;
(b)避开所述基板的基底层而在其周边区域形成平整层的工序;
(c)将具有位于所述平整层上的线路部及与其连接并所述所述基底层及所述平整层上的连接部的配线层形成在所述基底层及所述平整层上,以便使所述连接部具有与所述基底层接触而成的第1部分和与所述基底层未接触而成的第2部分的工序;和
(d)将已形成集成电路的半导体芯片装配在所述基板上的工序。
17.一种半导体装置的制造方法,其特征在于,包括:
(a)在形成了集成电路的半导体基板上形成树脂层,在所述树脂层上形成基底层的工序;
(b)避开所述树脂层的所述基底层而在其周边区域形成平整层的工序;和
(c)将具有位于所述平整层上的线路部及与其连接并位于所述基底层及所述平整层上的连接部的配线层形成在所述基底层及所述平整层上,以便使所述连接部具有与所述基底层接触而成的第1部分和与所述基底层未接触而成的第2部分的工序。
18.根据权利要求16或17所述的半导体装置的制造方法,其特征在于,还包括在所述(c)工序后除去所述平整层的工序。
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JP2003187455A JP3678239B2 (ja) | 2003-06-30 | 2003-06-30 | 半導体装置及びその製造方法、回路基板並びに電子機器 |
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US7218008B2 (en) | 2007-05-15 |
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