CN101233616B - 半导体元件和电气设备 - Google Patents

半导体元件和电气设备 Download PDF

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Publication number
CN101233616B
CN101233616B CN2006800274005A CN200680027400A CN101233616B CN 101233616 B CN101233616 B CN 101233616B CN 2006800274005 A CN2006800274005 A CN 2006800274005A CN 200680027400 A CN200680027400 A CN 200680027400A CN 101233616 B CN101233616 B CN 101233616B
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schottky
semiconductor element
electrode
diode
semiconductor
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CN101233616A (zh
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北畠真
楠本修
内田正雄
山下贤哉
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Abstract

本发明提供一种半导体元件和电气设备，该半导体元件(20)具有场效应晶体管(90)、肖特基电极(9a)和多个接合垫(12S、12G)，上述多个接合垫(12S、12G)中至少一个以位于上述肖特基电极(9a)的上方的方式配置。

Description

半导体元件和电气设备
技术领域
本发明涉及半导体元件，特别涉及对逆变(inverter)电路等进行控制的半导体功率开关元件。
背景技术
作为通常的半导体功率开关元件，例如可列举IGBT(Insulated GateBipolar Transistor：绝缘栅双极型晶体管)等。并且，作为半导体功率开关元件的应用例，存在使用于电力电子控制的控制电路，例如可列举控制三相电动机的逆变电路。
图9是表示现有的逆变电路的概要的电路图。如图9所示，现有的逆变电路(此处为三相用)具有相数量(此处为三个)的由开关功能部分(以下称为上臂)23H和开关功能部分(以下称为下臂)23L串联连接而成的电路(以下称为相开关电路)23，各个上臂23H和下臂23L由相互并联连接的开关元件21和二极管22构成。开关元件21例如由使用硅的IGBT构成。并且，上臂23H连接于高电位配线25，下臂23L连接于接地电位配线24。各臂23的中点26与作为负载的三相交流电动机的输入端子(以下称为电动机输入端子)27连接。然后，通过对上臂23H和下臂23L的导通、断开的定时(timing)进行调整，能够控制中点26的电位。即，中点26以及输入端子27的电位，在下臂23L导通、上臂23H断开的情况下，与接地电位24相等。另一方面，中点26以及输入端子27的电位，在上臂23H导通、下臂23L断开的情况下，与高电位25相等。这样，通过将电动机输入端子27的电位切换为接地电位24和高电位25，能够控制三相电动机28。
但是，因为开关元件21、二极管22的响应速度有限，即使对开关元件21、二极管22提供从导通状态切换为断开状态的信号，也不能立刻变成断开状态。因此，当同时进行上臂23H和下臂23L的导通、断开切换时，上臂23H和下臂23L有可能均成为导通状态。这样的状态是高电位25与接地电位24短路的状态，在逆变电路中会流动大电流。此外，因为该电流为损失电流，所以开关损失增加，电力利用效率下降。并且，因为在逆变电路中进行利用高速的开关的高效率逆变控制，所以一次的开关损失被累积计算开关次数次，整体的开关损失变大。因此，在现有技术中，考虑开关元件21、二极管22的响应速度以决定开关的定时。换言之，根据开关元件21、二极管22的响应速度的制约，决定逆变控制的频率。但是，在希望利用更高速的开关进行高效率逆变控制时，要求开关元件21和二极管22的开关进一步高速化。
但是，在使用IGBT作为开关元件的情况下，因为该IGBT是双极型器件，少数载流子(minority carrier)的寿命(lifetime)较长，反向恢复需要耗费时间，所以不能高速地进行由导通向断开的切换。因此，考虑使用作为单极型器件的MOSFET(金属-氧化物-半导体-场效应晶体管)作为开关元件。单极型器件因为不受少数载流子的影响，能够高速地进行由导通向断开的切换。但是，由硅构成的MOSFET的每单位面积的导通电阻Ron(Ωcm2)较大，因发热而产生的导通损失增加。
另一方面，在使二极管的开关高速化的器件中，有实施了载流子的寿命控制的快速恢复二极管(fast recovery diode)。但是，快速恢复二极管在数10kHz以上的高频下难以动作。此外，因为快速恢复二极管是双极型器件，由于少数载流子的扩散使得导通电阻变小，但是因为少数载流子的寿命较长，所以从导通向断开的切换需要时间。此外，在使二极管的开关更高速化的器件中，有以在半导体上形成肖特基(Schottky)结的方式设置有肖特基电极的肖特基二极管。肖特基二极管是单极型器件，因为不受少数载流子的影响，所以能够高速地进行从导通向断开的切换。但是，在由硅构成的肖特基二极管的情况下，耐压仅为100V左右，不能在需要600V以上的耐压的电力电子领域中利用。
此外，因为对由硅构成的IGBT、二极管被实施载流子的寿命控制，所以不能集成为单芯片(one chip)。
因此，提出由宽禁带半导体构成在逆变电路等中使用的开关元件和二极管的方案。
例如，关于二极管，由宽禁带半导体构成的肖特基二极管的耐压在600V以上，与由硅构成的情况相比，导通电阻也充分地小，并且能够高速地进行从导通向断开的切换。
另一方面，关于开关元件，由宽禁带半导体构成的MOSFET与由硅构成的IGBT相比，每单位面积的导通电阻充分地小，能够确保耐压，并且能够高速地进行从导通向断开的切换。
但是，即使是SiC-MISFET，通过由半导体装置内的p型区域与n型区域的PN结构成的寄生二极管，在从反向偏压时的寄生二极管的导通状态向SiC-MISFET的断开的切换中可能伴有反向恢复时间的延迟。
例如，在开关元件的断开时，作为由电感负载产生的反电动势的正电压施加于源电极的情况下，通过寄生二极管，作为少数载流子的空穴被注入至n型区域，从而导致二极管动作的反向恢复时间的延迟。
另一方面，由宽禁带半导体构成MOSFET，通过在该立式MOSFET的漂移区域以进行肖特基接合的方式配设肖特基电极，能够将肖特基二极管和作为开关元件的MOSFET集成为单芯片(参照专利文献1)。
专利文献1：日本特开2002-203967号公报
发明内容
但是，在将上述现有的半导体元件作为构成具体的逆变电源电路(例如，空调压缩机等三相电动机用的逆变电源电路)的开关元件加以使用的情况下，在这种开关元件的实用化中，显现出以下所述的问题。
肖特基结的金属电极(肖特基电极)的配置面积不会对半导体元件的高速开关动作带来大的障碍。但如果在存在于MOSFET内的寄生二极管和肖特基二极管上施加正方向电压，考虑在两者中流过电流的状况，则从确保适当的通电能力的观点出发，肖特基电极的配置面积成为重要的必须考虑的内容。
实际上，当在三相电动机用的逆变电源电路中应用专利文献1所记载的技术时，发现以基于开关元件断开时的电感负载的反电动势为触发，存在集中在肖特基电极上的电流引起元件的破坏的可能性。
此外，专利文献1的图2所示的肖特基电极，以在俯视时包围场效应晶体管区域的方式配置成由细配线连结成的正交格子状。因此，在半导体元件的制造过程中容易诱发细配线的断线，这成为半导体元件的制造成品率下降的主要原因。
本发明是鉴于上述情况提出的，目的在于提供一种半导体元件和电气设备，能够实现高速开关动作与能量损失降低的并存，并且基于由电气设备的电感负载等产生的反电动势的电流集中耐性优异，并且在进行引线接合(wire bonding)时能够抑制场效应晶体管的绝缘膜的劣化。
本发明的发明者们为了解决上述问题，锐意研究，结果查明：在专利文献1的结构中，因为配设有肖特基电极的区域的面积相对半导体元件整体的面积所占的比例较小，所以电流集中至肖特基电极，半导体元件被破坏。
此外，在高电压下对切换大电流的半导体元件进行接合(bonding)的情况下，为了承受大电流，对直径0.3nm以上的粗导线进行引线接合，与电极端子等结线。在该情况下，一边施加超声波一边将导线按压至配置在半导体元件上的接合垫(bonding pad)上进行引线接合，但当在接合垫之下配置有场效应晶体管时，由于超声波的施加可能会破坏场效应晶体管。于是，本发明者们发现：由于施加超声波，场效应晶体管的绝缘膜产生耐压劣化。
本发明的半导体元件包括：场效应晶体管，其具有：半导体层、在该半导体层上以包括该半导体层的上面的方式形成的第一导电型的第一源极/漏极区域、在上述半导体层上以包括上述上面和上述第一源极/漏极区域的方式形成的第二导电型区域、在上述半导体层上以包括上述上面和上述第二导电型区域的方式形成的第一导电型的漂移区域、以至少与上述第一源极/漏极区域的上述上面连接的方式设置的第一源/漏电极、以隔着栅极绝缘膜至少与上述第二导电型区域的上述上面相对的方式设置的栅电极、和欧姆连接于上述漂移区域的第二源/漏电极；在上述漂移区域的上述上面，以与该上面形成肖特基结的方式设置的肖特基电极；覆盖设置有上述第一源/漏电极、栅电极和肖特基电极的上述半导体层的上面的层间绝缘膜；和在上述层间绝缘膜之上配设的、与上述第一源/漏电极、栅电极和肖特基电极中的至少一个电连接的多个接合垫，其中，上述半导体层在俯视时通过假想的分界线分割成多个单元，以在上述多个单元中延展的方式形成有漂移区域和第二源/漏电极，上述多个单元由其中形成有上述场效应晶体管的晶体管单元，和其中形成有上述肖特基电极的二极管单元构成，上述接合垫位于上述二极管单元的上述肖特基电极的上方。
当采用这样的结构，在将导线接合至接合垫时，即使一边施加超声波一边将导线按压在接合垫上进行引线接合，因为在接合垫的下方配置有配设有肖特基电极的二极管单元，所以能够减少形成于晶体管单元的场效应晶体管的破坏、栅极绝缘膜的耐压劣化。此外，因为与存在于场效应晶体管的p/n势垒相比，具有较小能量势垒的肖特基结在半导体元件中存在，所以在向半导体元件施加电涌(surge)电压时，在肖特基结部分优先流过漏电流，于是，电涌电压被缓和，能够抑制半导体元件的破坏。此外，在将场效应晶体管的寄生二极管从导通切换到断开的情况下，来自场效应晶体管的寄生二极管的少数载流子被肖特基电极吸收，能够进行高速的开关。
当采用这样的结构时，因为能够使配设肖特基电极的区域的面积充分大，所以能够防止电流向肖特基电极的集中，抑制半导体元件的破坏。
上述第一源/漏电极也可以以与上述第一源极/漏极区域和第二导电型区域的上述上面连接的方式设置。
上述第一导电型可以是n型，上述第二导电型可以是p型。
上述半导体层可以由宽禁带半导体构成。
在俯视时，也可以在多个上述晶体管单元之间岛状地配置一个以上的上述二极管单元，使上述接合垫位于该岛状地配置的一个以上的二极管单元的上方。
上述多个接合垫也可以通过导线相互连接。
上述接合垫也可以具有边长为0.3mm以上的四边形的形状。
全部的上述晶体管单元的俯视时的面积相对上述半导体元件的俯视时的面积的比例优选为50％以上且99％以下。
上述肖特基电极的面积相对上述半导体元件的俯视时的面积的比例优选为1％以上且50％以下。
优选上述二极管单元的上述肖特基电极的面积比上述晶体管单元的上述第二导电型区域的俯视时的面积大。
此外，本发明能够用作构成交流驱动装置的逆变电源电路的半导体元件，例如，能够适用于上述半导体元件作为臂模块(ア一ムモジユ一ル)被插入的电气设备中。
根据这样的电气设备，因为半导体元件的导通损失对应于电流乘以电压的值(电流×电压)，所以与现有的PN结二极管的正方向电压相比，能够较低地保持肖特基二极管的正方向电压。因此，在电气设备的逆变电源电路中作为臂模块被插入的半导体元件的导通损失，相比于采用PN结二极管的现有的元件得到改善。
进一步，在电气设备的逆变电源电路中作为臂模块被插入的半导体元件的从导通状态向断开状态的切换速度变快，开关损失减少。
也可以构成为：基于由上述交流驱动装置内的电感负载产生的反电动势，而施加于上述场效应晶体管的寄生二极管，以及由所述漂移区域和与该漂移区域的上面形成肖特基结的肖特基电极构成的肖特基二极管的电压，比上述肖特基二极管的正方向的上升沿电压大，并且比上述寄生二极管的正方向的上升沿电压小。
上述交流驱动装置的一个例子是由上述逆变电源电路驱动的交流电动机，通过该交流电动机驱动例如空调的压缩机。
本发明的上述目的，其他目的，特征和优点，通过参照附图以及下述的优选的实施方式的详细说明而变得明确。
根据本发明，能够获得一种实现高速开关动作和能量损失降低的并存，并且基于由电气设备的电感负载等产生的反电动势的电流集中耐性优异，并且在进行引线接合时能够抑制场效应晶体管的绝缘膜的劣化的半导体元件和电气设备。
附图说明
图1是表示本发明的第一实施方式的半导体元件的结构的平面图。
图2是表示本发明的第一实施方式的半导体元件的结构的平面图。
图3是放大图1的半导体元件的结构的一部分的部分平面图。
图4是表示图1的半导体元件的截面视图的结构的部分截面图，是沿图3所示的IV-IV线截断的截面图。
图5是示意性地表示作为本发明的第二实施方式的半导体装置的臂模块的结构的平面图。
图6是表示本发明的第二实施方式的逆变电路的结构的电路图。
图7是表示本发明的第三实施方式的半导体元件的结构的平面图。
图8放大图7的半导体元件的结构的一部分的部分平面图。
图9是表示作为现有的半导体元件的应用例的三相电动机驱动用的逆变电路的概要的电路图。
图10是用于说明假想的分界线的概略图，(a)是表示特定假想的分界线的第一方法的图，(b)是表示特定假想的分界线的第二方法的图，(c)是表示特定假想的分界线的第三方法的图，(d)是表示特定假想的分界线的第四方法的图。
符合说明
1    漏电极
2    半导体基板
3    半导体层(SiC层)
3a   漂移区域
4    p型半导体区域(第二导电型区域)
4a   p型半导体区域外周部
4b   p型半导体区域中央部
5    源极区域
6    源电极
7    栅极绝缘膜
8    栅电极
9    二极管形成区域
9a、9b  肖特基电极
10   晶体管形成区域
11   护环(guard ring)(耐压部件)
12S  源极·肖特基用垫(ソ一ス·シヨツトキ一用パツド)
12G  栅极用垫
13S、13G  导线
14  半导体元件端部
15  漏电极端子
16  源电极端子
17  栅电极端子
18  密封树脂
20  半导体元件
21  开关元件
22  二极管
23  相开关电路
23H  上臂
23L  下臂
24  接地电位配线(接地电位)
25  高电位配线(高电位)
26  臂的中点
27  电动机输入端子
28  三相电动机
40  层间绝缘膜
50  假想的分界线
50a、50c  横分界线
50b、50d  竖分界线
50X  X部分假想线
50Y  Y部分假想线
51  Z形线(zigzag line)
70  肖特基二极管
80  二极管单元
90  场效应晶体管(MOSFET)
100  晶体管单元
200  单元
具体实施方式
以下参照附图说明本发明的实施方式。
(第一实施方式)
图1和图2是表示本发明的第一实施方式的半导体元件的结构的平面图。图3是放大图1的半导体元件的结构的一部分的部分平面图。图4是表示图1的半导体元件的截面视图的结构的部分截面图，是沿图3所示的IV-IV线截断的截面图。
本实施方式的半导体元件作为并联地连接有场效应晶体管(以下也有称之为MOSFET的情况)和肖特基二极管的电路发挥功能，由集成有构成这样的电路的多个场效应晶体管和多个肖特基二极管的一个IC芯片构成。并且，本实施方式的半导体元件例如在三相电动机驱动用的逆变电路(参照图6)中用作相开关电路23。被集成的场效应晶体管的数目由所希望的电流容量决定。
如图1和图2所示，本实施方式的半导体元件20具有晶体管形成区域10。此处，该晶体管形成区域10在俯视时是正方形。另外，单元形成区域201在俯视时不一定是正方形。该晶体管形成区域10在俯视时由格子状的假想的分界线50分割成被划分的多个单元200，换言之，被分割成由被行列状划分的区域构成的多个单元200。各个单元200在此处是正方形。该多个单元200由形成有后述的场效应晶体管90的晶体管单元100，和形成有配设有肖特基电极9a的肖特基二极管70的二极管单元80构成。并且，在本实施方式的半导体元件20中，在晶体管形成区域10中，岛状地形成配设有一个以上的二极管单元80的区域(以下称为二极管形成区域)9，以埋入该岛状的二极管形成区域9之间的方式形成有晶体管单元100。在本实施方式中，在晶体管形成区域10的共计9个位置配设有二极管形成区域9，但二极管形成区域9的数目并不限定于此。此外，在本实施方式中，一个二极管形成区域9以竖3×横3的共计9个二极管单元80聚集的方式构成，但二极管单元80的数目和其配置并不限定于此。
在晶体管形成区域10的外侧，在后述的半导体层3的表面上以包围晶体管形成区域10的方式形成有护环11。并且，以覆盖二极管形成区域9的方式配设有接合垫(源极·肖特基用垫)12S。并且，也可以使源极·肖特基用垫12S的面积比二极管形成区域9的面积小。并且，该源极·肖特基用垫12S彼此之间通过导线13S以架桥的方式连接。此外，在晶体管形成区域10的外周的端部配设有接合垫(栅极用垫)12G，该栅极用垫12G由导线13G连接。
接着，说明假想的分界线50。图10是用于说明假想的分界线的概略图，(a)是表示特定假想的分界线的第一方法的图，(b)是表示特定假想的分界线的第二方法的图，(c)是表示特定假想的分界线的第三方法的图，(d)是表示特定假想的分界线的第四方法的图。
在图1～图3中，双点划线所示的假想的分界线50是使得对发明的范围、说明书的内容的说明变得简单的线，并不实际存在于将本发明具体化的制品中。在晶体管单元100彼此之间相邻接的情况下，假想的分界线50是距各个晶体管单元100的中心为等距离的在竖方向或横方向延伸的假想线；在二极管单元80彼此之间相邻接的情况下，假想的分界线50是距各个二极管单元80的中心为等距离的在竖方向或横方向延伸的假想线；在晶体管单元100和二极管单元80相邻接的情况下，假想的分界线50是距晶体管单元100的中心和二极管单元80的中心为等距离的在竖方向或横方向延伸的假想线。假想的分界线50能够根据场效应晶体管90和肖特基二极管70的形状适当地进行变更。
此处，作为场效应晶体管90和肖特基二极管70的实际的排列，如图10所示，设想各种的配置图案。因此，参照图10，对特定与各个配置图案对应的假想的分界线50的方法进行说明。而且，以下将假想的分界线50分成横分界线50a、50c和竖分界线50b、50d以进行说明。为了简化说明，在图10中，将场效应晶体管90简记为元件“T”，将肖特基二极管70简记为元件“S”。此外，为了方便说明，使横分界线50a、50c的延伸方向为“X方向”，竖分界线50b、50d的延伸方向为“Y方向”。进而，使在X方向并列的元件S和元件T的排列为行方向排列，在Y方向并列的元件S和元件T的排列为列方向排列。
首先，参照图10(a)，对特定假想的分界线50的第一方法进行说明。
图10(a)例示配置为三行三列的矩阵状的元件T和元件S。元件T以包围配置有元件S的区域的方式配置。在图10(a)中表示元件T和元件S形成为正方形的例子。这样，为了容易进行说明，将肖特基电极9a的形状简化记载为正方形。
但是，这样的元件T和元件S的形状、排列，只不过是用于对假想的分界线50的特定的方法进行说明。因此，例如，元件T和元件S的具体的形状并非必须是正方形，只要适当确定其中心，也可以是圆形、三角形或五边形以上的多边形。
但是，在元件T为正方形、元件S为三角形这样的元件T与元件S的形状大不相同的情况下，在求取晶体管单元100或二极管单元80的面积相对半导体元件20整体的面积的比例时，必须根据适当的修正系数进行修正。
如图10(a)所示，因为存在于由三行和三列构成的各部位的元件T和元件S是正方形，所以这些元件的中心Pij(i＝1～3，j＝1～3)一致地定为正方形的对角线的交点。
此处，横分界线50a以距相互在列方向上邻接的一对元件T的各自的中心(P11和P21)为等距离，并且距相互在列方向上邻接的元件T和元件S的各自的中心(例如P12和P22)为等距离的方式形成。此外，横分界线50c以距相互在列方向上邻接的一对元件T的各自的中心(P21和P31)为等距离，并且距相互在列方向上邻接的一对元件S的各自的中心(例如P22和P32)为等距离的方式形成。
竖分界线50b以距相互在行方向上邻接的一对元件T的各自的中心(P11和P12)为等距离，并且距相互在行方向上邻接的元件T和元件S的各自的中心(例如P21和P22)为等距离的方式形成。此外，竖分界线50d以距相互在行方向上邻接的一对元件T的各自的中心(P12和P13)为等距离，并且距相互在行方向上邻接的一对元件S的各自的中心(例如P22和P23)为等距离的方式形成。
接着，参照图10(b)，对特定假想的分界线50的第二方法进行说明。
图10(b)例示正方形的元件T和正方形的元件S配置为千鸟状(Z字形(zigzag alignment))的情况。元件T以包围配置有元件S的区域的方式形成。构成第二行的排列的元件T和元件S相对于构成第一行和第三行的排列的元件T和元件S，向X方向偏移构成第一行和第三行的排列的元件T和元件S的间距的一半。因此，元件T和元件S的配置图案成为三行六列。由此，在由三行和六列构成的各部位中的一部分(例如2行×3列的部位)上没有配置元件T和元件S。
因为存在于由三行和六列构成的各部位的适当位置的元件T和元件S是正方形状，所以元件T和元件S的中心Pij(i＝1～3，j＝1～6，但是除去P12、P14、P16、P21、P23、P25、P32、P34、P36)一致地定为该正方形的对角线的交点。
横分界线50a(在图10(b)中以细双点划线图示)是以通过以下各中点的方式在X方向延伸的假想线：连接相互在倾斜方向上邻接的第一行×第一列的元件T的中心P11和第二行×第二列的元件T的中心P22的Z形线51上的中点(图10(b)所示的黑圆点，以下相同)；连接相互在倾斜方向上邻接的第二行×第二列的元件T的中心P22和第一行×第三列的元件T的中心P13的Z形线51上的中点；连接相互在倾斜方向上邻接的第一行×第三列的元件T的中心P13和第二行×第四列的元件S的中心P24的Z形线51上的中点；连接相互在倾斜方向上邻接的第二行×第四列的元件S的中心P24和第一行×第五列的元件T的中心P15的Z形线51上的中点；和连接相互在倾斜方向上邻接的第一行×第五列的元件T的中心P15和第二行×第六列的元件S的中心P26的Z形线51上的中点。
竖分界线50b(在图10(b)中以粗双点划线图示)是由以下各假想线构成的假想线：以距相互在行方向上邻接的一对元件T的各自的中心(P11和P13)为等距离的方式在Y方向延伸的Y部分假想线50Y；以距相互在行方向上邻接的元件T的中心P22和元件S的中心P24为等距离的方式在Y方向延伸的Y部分假想线50Y；以距相互在行方向上邻接的元件T的中心P31和元件S的中心P33为等距离的方式在Y方向延伸的Y部分假想线50Y；和连接这三个Y部分假想线50Y的端部之间，并在X方向延伸的两个X部分假想线50X。
接着，参照图10(c)，对特定假想的分界线50的第三方法进行说明。
图10(c)例示在X方向配置的三个长方形的元件T，和配置在其中的一对元件T之间(第三列)的一个长方形的元件S。元件T和元件S形成为在Y方向上不断开的相连的条纹状。
因为元件T和元件S是长方形，所以这些元件的中心Pij(i＝1，j＝1～4)一致地定为该长方形的对角线的交点。
竖分界线50b是以距相互在行方向上邻接的元件T的各自的中心P11、P12为等距离的方式在Y方向延伸的假想线。另外，竖分界线50d是以距相互在行方向上邻接的元件T的中心P12和元件S的中心P13为等距离的方式在Y方向延伸的假想线。
在图10(c)中，不存在相互在列方向上邻接的元件T和元件S。因此，作为横分界线50a，选择在Y方向上距在行方向上邻接并列的四个元件的各自的中心为等距离的一对假想线。此处，作为该假想线的例子，显示通过元件T和元件S的两端面的一对横分界线50a。
接着，参照图10(d)，对特定假想的分界线50的第四方法进行说明。
图10(d)例示配置为矩阵状的正方形的元件T，和被配置有该元件T的区域包围的元件S。一个元件S形成为由四个单元200构成的大致正方形。图10(d)所示的元件T和元件S的配置图案的形成，除了元件S以在多个单元200中延展的方式与横分界线50c和竖分界线50d交叉的要点之外，与图10(a)所示的元件T和元件S的配置相同。因此，在此省略对与元件S交叉的横分界线50c和竖分界线50d以外的假想的分界线50的说明。
如图10(d)所示，与元件S交叉的横分界线50c是以距相互在列方向上邻接的元件T的各自的中心(P21、P31)为等距离的方式在行方向延伸的假想线的延长线。另外，与元件S交叉的竖分界线50d是以距相互在行方向上邻接的元件T的各自的中心(P12、P13)为等距离的方式在列方向延伸的假想线的延长线。
接着详细说明采用平面型的半导体元件20的结构。
如图4所示，半导体元件20具有半导体基板2。该半导体基板2由SiC构成，掺杂为n+型(高杂质浓度的n型)。在半导体基板2的下面的整个面上形成有漏电极(第二源/漏电极)1。漏电极1由导电性材料，例如Ni、Al、Ti、Mo等金属构成。此外，在半导体基板2的上面的整个面上形成有半导体层3。如上所述，半导体基板2和半导体层3虽然由碳化硅(SiC)构成，但是也可以由其他的宽禁带半导体构成。具体而言，能够使用GaN、AlN等IIIA族氮化物，金刚石等。此处，所谓宽禁带半导体是指作为传导带的下端和价电子带的上端的能量差的能隙为2.0eV以上的半导体。该半导体层3和半导体基板2构成半导体元件20的半导体，该半导体被分割成上述的多个单元200。
在半导体层3的晶体管单元100，以包括其上面的方式形成有n+型的源极区域(第一源极/漏极区域)5。源极区域5在俯视时形成为矩形的环状，并且以其中心与晶体管单元100的中心大致一致的方式形成。并且，在半导体层3，以包括其上面并且包括源极区域5的方式形成有p型半导体区域(第二导电型区域)4。具体而言，p型半导体区域4在半导体层3上，以包括其上面的、源极区域5的内侧部分和包围源极区域5的矩形的环状部分，并且到达比源极区域5的下端更深的位置的方式形成。并且，半导体层3的源极区域5和p型半导体区域4以外的区域由n-型(低杂质浓度的n型)的漂移区域3a构成。因此，漏电极1通过n+型的半导体基板2与漂移区域3a欧姆连接。并且，在晶体管单元100中，以覆盖从半导体层3的上面的源极区域5的中间到晶体管单元100的外周的部分的方式形成有栅极绝缘膜7。换言之，在源极区域5的外周部、p型半导体区域4的源极区域5与漂移区域3a之间的部分(以下称为p型半导体区域外周部)4a、漂移区域3a的位于p型半导体区域外周部4a的附近的部分之上，形成栅极绝缘膜7。栅极绝缘膜7由氧化膜(SiO2)构成。以正好与栅极绝缘膜7重叠的方式，在该栅极绝缘膜7上形成有栅电极8。因此，p型半导体区域外周部4a形成沟道区域。栅电极8由导电性材料，例如Ni、Ti、Al、Mo等金属、多晶硅等构成。并且，在晶体管单元100中，从半导体层3的上面的源极区域5的中间到位于内侧的部分之上形成有源电极(第一源/漏电极)6。换言之，在源极区域5的内周部和p型半导体区域4的位于源极区域5的内侧的部分(以下称为p型半导体区域中央部)4b之上，形成源电极6。源电极6通过n+型源极区域5、p型半导体区域4，和半导体层3欧姆连接。源电极6由导电性材料，例如Ni、Ti、Al、Mo等金属等构成。
另一方面，在半导体层3的二极管单元80，以与二极管单元80的外周之间具有若干间隙的方式，在其上面的大致整个面上形成有肖特基电极9a。在二极管单元80，因为半导体层3的全部区域由n-型的漂移区域3a构成，所以肖特基电极9a与半导体层3肖特基接合。为了防止由电场集中导致破坏，如图2和图3所示，优选肖特基电极9a的角部为带有圆形的形状。肖特基电极9a由导电性材料，例如Ni、Ti、Al、Mo等金属构成。
此处，优选肖特基电极9a的面积比p型半导体区域4的俯视时的面积大。这是因为，肖特基电极9a和漂移区域3a之间的肖特基垫垒比p型半导体区域4和漂移区域3a之间的p/n结的垫垒小，在向半导体元件20施加电涌电压时，通过肖特基电极9a缓和该电涌电压，当采用这样的结构时，该效果会更大。
根据以上的结构，在晶体管单元100形成有一个n沟道型的立式场效应晶体管90，在二极管单元80形成有一个肖特基二极管70。此外，漂移区域3a、半导体基板2和漏电极1以遍及全部的单元200的方式设置。并且，因为栅极绝缘层7和栅电极8以在邻接的晶体管单元100之间连续的方式形成，并且在多个晶体管单元100之间岛状地形成有二极管单元80，所以在半导体层3的整个表面上分别存在一个格子状的栅极绝缘层7和栅电极8，在该格子状的栅极绝缘层7的开口内存在源电极6或肖特基电极9a。
如图1和图2所示，在半导体层3的上面，进一步形成有护环11。在晶体管形成区域10和半导体层3的端(芯片的端)14之间，在俯视时形成有两层矩形环状的护环11。此处，护环11并不限定于在俯视时形成矩形的环状，只要包围单元形成区域201的外周即可。并且，护环11并不限定于形成两层，也可以形成为一层、三层等几层。护环11由与漂移区域3a相反的导电型的p型半导体区域构成。
并且，以覆盖形成有源电极6、栅电极8和肖特基电极9a的半导体层3的表面的方式，设置有层间绝缘膜40。在该层间绝缘膜40的上面，以位于二极管形成区域9的上方的方式设置有源极·肖特基用垫12S。源极·肖特基用垫12S由Al等金属构成。这里，源极·肖特基用垫12S具有边长为0.6mm以上的正方形的形状。并且，源极·肖特基用垫12S的形状不限定于正方形。在俯视时的晶体管形成区域10中，配设有竖3×横3的共计9个源极·肖特基用垫12S。源极·肖特基用垫12S与源电极6和肖特基电极9a电连接。此外，在俯视时的晶体管形成区域10的外周的端部，配设有一个与栅电极8电连接的栅极用垫12G。在层间绝缘膜40上，以贯通它并分别与栅电极8、源电极6、肖特基电极9a连接的方式设置有多个由导电体构成的插头(plug)(未图示)。此外，在层间绝缘膜40的上面，配设有连接各插头和与其对应的接合垫的配线(未图示)。因此，源极·肖特基用垫12S和源电极6通过相应的插头和配线(源极配线)连接，源极·肖特基用垫12S和肖特基电极9a通过相应的插头和配线(肖特基配线)连接，栅极用垫12G和栅电极8通过相应的插头和配线(栅极配线)连接。在本实施方式的半导体元件20中，虽然配设有9个源极·肖特基用垫12S，但是源极·肖特基用垫12S的个数并不限定于此。在源极·肖特基用垫12S的全体上，并联连接有晶体管单元100的个数的场效应晶体管90，且并联连接有二极管单元80的个数的肖特基电极9a。此外，在本实施方式的半导体元件20中，虽然配设有一个栅极用垫12G，但是栅极用垫12G的个数并不限定于此。即，也能够配设多个栅极用垫12G。在该情况下，与上述源极·肖特基用垫12S的情况同样，也可以以相对多个栅极用垫12G进行架桥的方式，由导线13G进行连接。
在一个方向并列的三个源极·肖特基用垫12S通过导线13S以架桥的方式连接。导线13S由Al、Au等金属构成。通过一边施加超声波一边将导线13S按压在源极·肖特基用垫12S上，源极·肖特基用垫12S与导线13S进行连接。在本实施方式的半导体元件20中，虽然使用直径0.3mm的导线作为导线13S，但是为了承受大电流，优选使用直径更大的导线。在本实施方式的半导体元件20中，虽然使用三根导线13S，但是导线13S的根数并不限定于此。
此外，为了进行接合(bonding)，源极/肖特基用垫12S的一边的长度优选比导线13S的直径大。在本实施方式中，因为使用0.3mm直径的导线作为导线13S，所以使源极·肖特基用垫12S的一边的长度在0.3mm以上即可。此处，为了容易接合，优选如本实施方式那样，使源极·肖特基用垫12S的一边的长度为0.6mm以上。并且，为了使接合更加容易，优选使源极·肖特基用垫12S的一边的长度为0.9mm以上。
另一方面，栅极用垫12G通过导线13G连接。此处，导线13G由Al、Au等金属构成。通过一边施加超声波一边将导线13G按压在栅极用垫12G上，栅极用垫12G与导线13G进行连接。在本实施方式的半导体元件20中，使用直径0.3mm的导线作为连接源极·肖特基用垫12S的导线13S，但因为在栅电极8中流过的电流并不那样大，所以优选使用直径更细的导线作为连接栅极用垫12G的导线13G。
接着，参照图1～图4，对以上结构的半导体元件20的制造方法进行说明。并且，因为制造方法本身是由众所周知的工序构成的，所以简单地进行说明。
但是此处省略各制造工序过程中的图示。因此，在对本制造方法进行说明时，为了说明的方便，制造工序过程中的各个构成部分的参照符号使用图1～图4所示的完成品的符号代替。
首先，准备以使氮浓度为3×1018cm-3的方式掺杂有氮的n+型的具有4H-SiC(0001)Si面的[11-20]方向8度斜切(offcut)面的半导体基板2。
接着，在清洗该半导体基板2之后，在上述斜切面上，将作为调整至1.3×1016cm-3浓度的掺杂氮的n-型的外延成长层的SiC层(半导体层)3，通过CVD法调整厚度到10μm地进行成膜。
然后，配置在SiC层3的表面的适当位置开口的掩模(未图示)，朝向SiC层3的表面，适当地选择30～700keV范围内的多级离子能量，以2×1014cm-2浓度的剂量(dose)通过开口注入铝离子。通过该离子注入，在SiC层3的表层，岛状地形成深度0.8μm左右的p型半导体区域4。并且，还同时形成护环11。
之后，使用在p型半导体区域4的表面的适当位置开口的其他掩模(未图示)，相对p型半导体区域4以30～180keV的能量，以1.4×1015cm-2浓度的剂量注入氮离子，形成n+型的源极区域5。
接着，将该半导体基板2暴露在Ar气氛中，保持在1700℃的温度，实施约一个小时的热处理，使上述离子注入区域活化。
接着，将该半导体基板2在氧化处理炉内保持在1100℃的温度，实施3个小时的湿氧化。通过该氧化处理，在SiC层3的整个表面区域上形成厚度40nm的氧化硅膜。
在该氧化硅膜上，使用光刻技术和蚀刻技术图案形成(patterning)源电极用的第一开口和肖特基电极用的第二开口。由此，该氧化硅膜成为栅极绝缘膜7。
然后，在露出于第一开口内的SiC层3的表面上选择性地形成由Ni构成的电极，在该第一开口内形成的电极成为源电极6。
接着，在半导体基板2的背面设置由Ni构成的漏电极1。
然后，在堆积这些Ni层之后，实施适当的热处理，上述电极6、1和半导体之间被欧姆连接。
进一步，在露出于上述第二开口内的SiC层3的表面上选择性地形成由Ni构成的电极，在该第二开口内形成的电极成为肖特基电极9a。
之后，在栅极绝缘膜7的表面上形成由Al构成的栅电极8。
之后，在源电极6、栅电极8和肖特基电极9a的表面上形成层间绝缘膜40，相对该层间绝缘膜40，适当地形成插头、配线、接合垫12S、12G。
接着，通过导线13S、13G适当地连接接合垫12S、12G。
这样，就得到了本实施方式的半导体元件20。
接着，对以沟槽型形成半导体元件20的场效应晶体管90的情况，和以平面型形成的情况的比较进行说明。
作为场效应晶体管的结构，有在半导体层上平面状地形成有p层和n层的平面型，和制造细而深的槽并埋入栅电极和栅极绝缘膜的沟槽型。本实施方式的半导体元件20的场效应晶体管90，考虑如以下所述的与肖特基二极管70的关联性等各种理由，采用平面型。
例如，在日本专利特表2005-501408号公报(以下称为先行例)中，公开有相对沟槽型的MOSFET一体化肖特基二极管的结构。在该先行例中，在沟槽(掘出的槽或孔)的底面形成半导体和金属的肖特基结部分，构成肖特基二极管。上述先行例的沟槽部分本来是构成晶体管单位元件部分的间隙的部分，与晶体管单位元件(如本实施方式那样，基于假想的分界线50划分的四边形的多个单元200)不同。
与此相对，形成有本实施方式的肖特基二极管70的部分占据基于假想的分界线50划分的四边形的多个单元200中的一部分的单元200的大致整个区域。因此，形成有本实施方式的肖特基二极管70的部分，与在上述先行例的间隙(的沟槽部分)中埋入肖特基电极的结构完全不同。
如本实施方式的半导体元件20那样的平面型的MOSFET90与肖特基二极管70的组合，具有在基于假想的分界线50划分的四边形的多个单元200上，能够任意选择是设置MOSFET90或是设置肖特基二极管70的结构上的自由度，相比于先行例那样的采用沟槽型的MOSFET的情况，具有优异性。通过该结构上的自由度，能够任意设定配置有MOSFET90和肖特基二极管70的部分相对半导体元件20整体的面积比，这个本发明的特征中的一个首次得到实现。
此外，在先行例中，必须在沟槽的壁面上隔着栅极绝缘膜形成栅电极，再进一步由层间绝缘膜确保绝缘，并在其上形成肖特基电极。这样，在沟槽壁面上形成有多层的绝缘膜和电极的情况下，在由多层的绝缘膜的部分覆盖的沟槽的底面部分上，不能形成大面积的肖特基电极。因此，只有沟槽的底面的一部分作为肖特基二极管起作用。因此，肖特基二极管的形成面积被限制得较小。在如本实施方式的半导体元件20那样的MOSFET90为平面型的情况下，没有上述的面积制约。
进一步，当如先行例那样在沟槽底面上形成肖特基电极时，成为在接近背面的漏电极的位置上存在肖特基电极的结构，在肖特基电极上引起电场集中，残存对耐压性的担心。另一方面，在采用平面型的MOSFET的情况下，因为肖特基电极9a形成于半导体层3的表面，并且与肖特基电极9a邻接的MOSFET90的P型半导体区域4形成得很深，所以不会在肖特基电极9a引起电场集中，确保耐压性。
如上所述，在采用本实施方式的半导体元件20那样的平面型的MOSFET90的情况下，能够任意设定MOSFET90和肖特基二极管70相对半导体元件20整体的面积比。并且，因为平面型的MOSFET90能够确保耐压性，形成工艺也简单，所以相比于采用先行例所示的沟槽型的MOSFET的情况，效果明显。
而且，在上述中，以在肖特基电极9a的材料中使用镍(Ni)为例进行了说明，但肖特基电极9a的材料并不限定于此，如上所述，在使用钛(Ti)、铝(Al)、钼(Mo)等的情况下也是同样的。
接着，对采用以上结构的半导体元件20的作用效果进行说明。
本实施方式的半导体元件20作为具有600V的耐压的功率器件(3mm方形(3mm×3mm的四边形)，额定电流值为20A)起作用。并且，在本实施方式的半导体元件20中，因为源极·肖特基用垫12S以位于肖特基电极9a的上方的方式配设，所以在将导线13S接合至源极·肖特基用垫12S时，即使一边施加超声波一边将导线13S按压在源极·肖特基用垫12S接合垫上进行引线接合，因为在源极·肖特基用垫12S的下方配置有配设有肖特基电极9a的二极管单元80，所以也能够防止在晶体管单元100上形成的场效应晶体管90的破坏和栅极绝缘膜7的耐压劣化。
此外，在本实施方式的半导体元件20中，因为源电极6与p型半导体区域中央部4b接触，p型半导体区域4的下方的n-型的漂移区域3a通过半导体基板2与漏电极1连接，所以在源电极6和漏电极1之间存在由漂移区域3a和p型半导体区域4构成的寄生二极管。此外，在本实施方式的半导体元件20中，因为源电极6以其与漂移区域3a形成肖特基结的方式设置，所以在源电极6和漏电极1之间存在由肖特基电极9a和漂移区域3a构成的肖特基二极管70。
并且，本实施方式的半导体元件20在使用时，在源电极6和漏电极1之间施加使漏电极1相对源电极6为更高电位的电压。并且，在该状态下，当向栅电极8施加阈值以上的电压(相对源电极6的电压)时，在位于栅电极8的下方的p型半导体区域4的上层部形成n沟道。并且，电子从源电极6经过源极区域、n沟道、漂移区域3a和半导体基板2向漏电极1移动，于是，电流从漏电极1流向源电极6。
另一方面，在负载具有感应性时，通过负载的电感，在场效应晶体管90从导通切换到断开的情况下，在源电极6和漏电极1之间，暂时施加使源电极6相对漏电极1为更高电位的电压。由此，二极管单元80的肖特基二极管70为导通，电流从源电极6流向漏电极1。此外，当源电极6的正的电压进一步上升时，场效应晶体管90的寄生二极管为导通，少数载流子(空穴)注入漂移区域3a。但是，通过将肖特基电极9a的面积设计得充分大，能够使肖特基二极管70的导通电阻比寄生二极管的导通电阻小，于是，在该情况下，电流优先流向肖特基二极管70。结果，注入至漂移区域3a的少数载流子的数目减少。此外，在此之后，当在源电极6和漏电极1之间施加使源电极6相对漏电极1为低电位的电压时，该注入的少数载流子瞬时被肖特基电极9a吸收。因此，与现有例相比，半导体元件20能够高速地进行从导通向断开的切换。此外，因为能够使配设肖特基电极9a的区域的面积充分大，所以能够防止向肖特基电极9a的电流集中，抑制半导体元件20的破坏。
此外，因为在本实施方式的半导体元件20中，在晶体管形成区域10的内部配设有二极管形成区域9，所以具有比存在于场效应晶体管90中的p/n垫垒小的能量垫垒的肖特基结存在于半导体元件20中，在半导体元件20上施加电涌电压的情况下，漏电流优先流过肖特基结部分，于是，电涌电压被缓和，能够抑制半导体元件20的破坏。
进一步，关于电涌电压，因为肖特基二极管70与寄生二极管(PN结二极管)是并联连接的结构，所以在一定程度的电流值(对应正方向电压Vf的低的区域的电流值)以下，肖特基二极管70高速地流过电流，当为更大的电流值(对应正方向电压Vf的高的区域的电流值)时，寄生二极管流过电流。因此，也能够防止由向肖特基二极管70的电流集中引起的破坏。
因此，本发明的半导体元件20具有相对电涌电压和电涌电流的高耐性。
此外，在寄生二极管为导通时，即使少数载流子被分别注入至p型半导体区域4、源极区域5，当施加反向偏压时，少数载流子被吸入肖特基电极9a，能够迅速地使寄生二极管成为断开状态。因此，在本发明的半导体元件20中，能够抑制所谓的闩锁(latch up)状态，即在仅具有现有的PN结二极管的半导体元件中所担心的不能快速成为断开状态的情况。
此外，构成本实施方式的半导体元件20的肖特基二极管70使用由Ni构成的肖特基电极9a作为阳极(anode)，使用宽禁带半导体(在本实施方式中是SiC)作为阴极(cathode)(半导体层3)。因为该肖特基二极管70不容易由通常使用的通电动作在半导体层3和肖特基电极9a的界面上形成硅化物层，所以从高电流耐性和高电压耐性的观点出发是合适的。
在假设以Ni作为阳极(肖特基电极9a)，使用Si(硅)作为阴极(半导体层3)构成肖特基二极管的情况下，难以在该肖特基二极管中流过大电流。即，在使用Si作为阴极的肖特基二极管中，容易在Si和Ni的界面上形成硅化物层，其结果是，Si和Ni被欧姆连接，存在无法发挥作为二极管的功能的情况。如果是这样，有可能会违反通过优先在肖特基二极管70中流动由电涌电压导致的漏电流，防止半导体元件20的绝缘破坏的这个本发明的问题解决原理。
因此，在本实施方式中，阴极的结构的差异(是以SiC还是以Si构成半导体层3的差异)，并不仅仅是本领域的从业者的设计事项类的问题，而是与上述问题解决原理直接相关的事项。
进一步，使用宽禁带半导体SiC作为阴极(半导体层3)的肖特基二极管70，与使用Si作为阴极(半导体层3)的肖特基二极管相比，在被施加电涌电压的情况下的耐压特性更优异。
其中，PN结二极管一般具有优异的高电流耐性和高电压耐性，但当使用宽禁带半导体SiC构成PN结二极管时，会由正方向电压Vf的上升的量引起导通损失。
概括以上事项，在本实施方式的半导体元件20中，优选在半导体层3使用宽禁带半导体(SiC)以构成肖特基二极管70。
接着，对本实施方式的实施例加以说明。
[实施例]
作为本实施例，制作多个本实施方式的半导体元件20，对栅极绝缘膜7的漏电流进行测定，在5％的半导体元件20中确认有1μA的漏电流，成品率是95％。另一方面，作为比较例，不配设二极管形成区域9，在场效应晶体管90的表面上直接覆盖源极·肖特基用垫12S，制作多个已引线接合的半导体元件，对栅极绝缘膜7的漏电流进行测定，在30％的半导体元件中确认有1μA的漏电流，成品率是70％。即，在本实施方式的半导体元件20中，以覆盖二极管形成区域9的表面的方式配设有源极·肖特基用垫12S，在二极管形成区域9没有形成栅极绝缘膜7。此外，位于源极·肖特基用垫12S的下方的肖特基二极管70相比于场效应晶体管90，承受超声波的强度更大。因此，即使一边施加超声波一边将导线13S按压在源极·肖特基用垫12S上进行接合，也能够减少由此引起的栅极绝缘膜7的损伤，并且能够抑制场效应晶体管90被破坏。
(第二实施方式)
本发明的第二实施方式例示插入有使用第一实施方式的半导体元件20的臂模块(半导体装置)的逆变电路。
[臂模块]
图5是示意性地表示作为本发明的第二实施方式的半导体装置的臂模块的结构的平面图。在图5中，对与图1～图4相同或相当的部分付给同一符号，省略其说明。
如图5所示，本实施方式的臂模块包括第一实施方式的半导体元件20，和具有漏电极端子15、源电极端子16、栅电极端子17的封装体(package)。
半导体元件20，以其下面的漏电极1连接在漏电极端子15的上面的方式，配设在漏电极端子1之上。并且，半导体元件20的源极·肖特基用垫12S通过导线13S与源电极端子16连接，半导体元件20的栅极用垫12G通过导线13G与栅电极端子17连接。半导体元件20的漏电极1和漏电极端子15通过芯片接合(die bonding)进行连接。此外，导线13S、13G的端部与源电极端子16或栅电极端子17通过接合(bonding)而连接。
并且，这样相互连接的半导体元件20和各电极端子15、16、17通过密封树脂18被密封(成型)。此处，上述密封树脂18能够使用常用的密封树脂。
[逆变电路]
图6是表示本发明的第二实施方式的逆变电路的结构的电路图。在图6中，对与图9相同或相当的部分付给同一符号，省略其说明。
本实施方式的逆变电路为三相交流电动机驱动用，具有相数量(这里是三个)的由上臂23H和下臂23L串联连接而成的相开关电路23，上臂23H和下臂23L分别由相互并联连接的开关元件21和二极管22构成。并且，上臂23H和下臂23L分别由本实施方式的臂模块构成。此外，各臂23H、23L的开关元件21由第一实施方式的半导体元件20中的场效应晶体管90构成。另一方面，二极管22是与开关元件21并联连接的反馈二极管，由第一实施方式的半导体元件20中的肖特基二极管70构成。关于除此之外的要点，由于在背景技术栏中已进行了说明，在此省略其说明。
在本实施方式中，使用该逆变电路对第一实施方式的半导体元件20的结构进行了研究
参照图2～图4，在半导体元件20中，肖特基电极9a的面积相对半导体元件20的俯视时的面积的比例优选为1％以上且50％以下。进而，肖特基电极9a的面积相对半导体元件20的俯视时的面积的比例更加优选为10％以上且50％以下。
首先，对肖特基电极9a的面积相对半导体元件20的俯视时的面积的比例为1％的情况进行说明。对使用这样的半导体元件20作为本实施方式的臂模块的情况下的开关损失进行测定，可知能够实现2％的开关损失的降低。此处，半导体元件20的二极管形成区域9的单位面积换算的导通电阻为1mΩcm2左右。并且，在肖特基电极9a的面积相对半导体元件20的俯视时的面积的比例为1％的情况下，电流在肖特基二极管70的正方向流动时的正方向电压Vf加上肖特基垫垒的正方向的上升沿电压(1V)如是3V左右(电阻部分由电流引起的正方向电压Vf上升是2V)，则以元件整体的电流密度换算，能够流过20A/cm2(半导体元件为2A)左右的电流。这里，所谓正方向电压为3V是指，在存在于本发明的半导体元件20中的寄生二极管中流动正方向的电流时的最低的正方向电压。这是因为使用SiC作为半导体材料。因此，在肖特基电极9a流过正方向的电流时，如果能够将正方向电压Vf保持在3V以下，则与不配设肖特基电极9a的现有的半导体元件相比，能够降低开关损失。
此时，晶体管形成区域10的平均的单位面积换算的导通电阻为比二极管形成区域9的单位面积换算的导通电阻大一位数的值。具体而言，晶体管形成区域10的平均的单位面积换算的导通电阻为10mΩcm2。因此，场效应晶体管90导通时的电流密度(以下称为导通电流密度)，在正方向电压Vf上升为2V时，能够估算为200A/cm2。其中，场效应晶体管90导通时的电流(以下称为导通电流)，与在肖特基二极管70中流动的电流的流向为相反方向。
因此，在使电流密度成为场效应晶体管90的导通电流密度的约1/10的电流值，以与导通电流相反的方向在肖特基二极管70中流动的情况下，使肖特基电极9a的面积相对半导体元件20的俯视时的面积的比例为1％是合适的。
另一方面，在上臂23H和下臂23L的连续动作实验中，存在上臂23H和下臂23L由于发热导致动作不稳定的情况。推定这是因为在肖特基二极管70中流动的电流值超过了上述容许电流值(20A/cm2)。因此，优选以使容许电流值比在肖特基二极管70中流动的电流值高的方式设计肖特基电极9a的面积的比例。
接着，制作肖特基电极9a的面积相对半导体元件20的俯视时的面积的比例为10％的半导体元件20，在使用该半导体元件20作为臂模块的情况下，能够实现5％的开关损失的降低。此外，在该情况下，以元件整体的电流密度换算，在肖特基二极管70中流动的电流的容许值是200A/cm2(半导体元件为20A)。此处，因为容许电流值200A/cm2是充分高的电流值，所以在肖特基二极管70中流动的电流值不会超过容许电流值，上臂23H和下臂23L稳定地进行动作。
如上所述，因为晶体管形成区域10的平均的单位面积换算的导通电阻为10mΩcm2，所以在使电流密度与场效应晶体管90的导通电流密度相同的电流值，以与导通电流相反的方向在肖特基二极管70中流动的情况下，使肖特基电极9a的面积相对半导体元件20的俯视时的面积的比例为10％是合适的。
另外，制作肖特基电极9a的面积相对半导体元件20的俯视时的面积的比例为50％的半导体元件20，在使用该半导体元件20作为臂模块的情况下，能够实现1％的开关损失的降低。
如上所述，虽然晶体管形成区域10的平均的单位面积换算的导通电阻为10mΩcm2，但是认为将来，通过降低沟道电阻等，能够使晶体管形成区域10的单位面积换算的导通电阻降低。结果，晶体管形成区域10的单位面积换算的导通电阻接近二极管形成区域9的单位面积换算的导通电阻(1mΩcm2)。此处，虽然晶体管形成区域10的导通电阻不会比肖特基二极管形成区域9的导通电阻小，但是存在两者的导通电阻为同程度的值的情况。在该情况下，当在场效应晶体管90中流动的导通电流的电流密度与在肖特基二极管70中流动的导通电流的电流密度相同时，使肖特基电极9a的面积相对半导体元件20的俯视时的面积的比例为50％是合适的。
在使肖特基电极9a的面积相对半导体元件20的俯视时的面积的比例为10％以上的情况下，半导体元件20的发热也能够被抑制，逆变电路稳定地进行动作。
但是，在使肖特基电极9a的面积相对半导体元件20的俯视时的面积的比例超过50％的情况下，因为晶体管单元100在半导体元件20整体中所占的比例下降，所以场效应晶体管90的导通电阻增大，开关损失也增加。
此外，因为如果在肖特基二极管70中流动的电流以元件整体的电流密度换算为200～600A/cm2，就能够期待半导体元件20的稳定动作，所以更加优选使肖特基电极9a的面积相对半导体元件20的俯视时的面积的比例为10％以上且30％以下。
如上所述，当使在肖特基二极管70中流动的电流值与在场效应晶体管90中流动的电流值相同(但是，流动方向相反)时，在二极管形成区域9的导通电阻为晶体管形成区域10的导通电阻的1/10的情况下，使肖特基电极9a的面积相对半导体元件20的俯视时的面积的比例为10％即可。此外，在二极管形成区域9的导通电阻为晶体管形成区域10的导通电阻的1/3的情况下，使肖特基电极9a的面积相对半导体元件20的俯视时的面积的比例为30％即可。
对以上的研究结果进行总结，在第一实施方式的半导体元件20中，为了充分发挥本来的作为开关元件的功能，优选使全部的晶体管单元100的俯视时的面积相对半导体元件20的俯视时的面积的比例为50％以上且99％以下。进而，为了半导体元件20的稳定动作，更加优选使全部的晶体管单元100的俯视时的面积相对半导体元件20的俯视时的面积的比例为70％以上且90％以下。
(第三实施方式)
图7是表示本发明的第三实施方式的半导体元件的结构的平面图。图8是放大图7的半导体元件的结构的一部分的部分平面图。在图7和图8中，对与图1～图3相同或相当的部分付给同一符号，省略其说明。
如图7和图8所示，在本实施方式的半导体元件20中，通过将肖特基电极9b岛状地配设在晶体管形成区域10的内部，构成二极管形成区域9，该肖特基电极9b覆盖在俯视时由格子状的假想的分界线50划分的单元200中的多个二极管单元80的上面。其他的要点与第一实施方式相同。
肖特基电极9b配设于晶体管形成区域10的内部的共计9个位置。而且，肖特基电极9b的配设个数并不限定于此。即，遍及多个单元200地配设肖特基电极9b、一体化形成肖特基电极9b的全体或者一部分，从而变更其个数也可以。采用这样的结构也能够获得与上述第一实施方式同样的效果。此外，当采用这样的结构时，构成部件的个数变少，半导体元件20的制造变得容易，成品率提高。
因为在本实施方式的半导体元件20中也能够防止因电场的集中导致的破坏，所以如图7和图8所示，优选肖特基电极9b的角部为带有圆形的形状。
其中，本实施方式的半导体元件20也与第一实施方式的半导体元件20同样，能够使用于第二实施方式的臂模块和逆变电路，能够取得与使用第一实施方式的半导体元件20时同样的效果。此外，全部的晶体管单元100的俯视时的面积相对本实施方式的半导体元件20的俯视时的面积的比例优选为50％以上且99％以下。
其中，在第一～第三实施方式中，说明了场效应晶体管90为n沟道型时的情况，但本发明也能够应用于场效应晶体管90为p沟道型的情况。但是，在该情况下，各半导体区域的导电型相反，源极区域和源电极相反于漏极区域和漏电极。
根据上述说明，本领域的技术人员能够明确本发明的很多改良和其他实施方式。因此，上述说明仅应该被理解为例示，是以向本领域的从业者指导实施本发明的最佳方式为目的而提供的。只要不脱离本发明的精神，能够实质上变更其结构和/或功能的细节。
产业上的可利用性
本发明的半导体元件实现高速开关动作和能量损失减少的并存，并且基于由电气设备的电感负载等引起的反电动势的电流集中耐性优异，同时能够抑制引线接合时的场效应晶体管的绝缘膜的劣化，例如，能够应用在电气设备的高速逆变电源电路的用途中。

Claims (12)

1.一种半导体元件，其特征在于，包括：
场效应晶体管，该场效应晶体管具有：半导体层、在该半导体层上以包括该半导体层的上面的方式形成的第一导电型的第一源极/漏极区域、在所述半导体层上以包括所述上面和所述第一源极/漏极区域的方式形成的第二导电型区域、在所述半导体层上以包括所述上面和所述第二导电型区域的方式形成的第一导电型的漂移区域、以至少与所述第一源极/漏极区域的所述上面连接的方式设置的第一源/漏电极、以隔着栅极绝缘膜至少与所述第二导电型区域的所述上面相对的方式设置的栅电极、和欧姆连接于所述漂移区域的第二源/漏电极；
在所述漂移区域的所述上面，以与该上面形成肖特基结的方式设置的肖特基电极；
覆盖设置有所述第一源/漏电极、栅电极和肖特基电极的所述半导体层的上面的层间绝缘膜；和
在所述层间绝缘膜之上配设的、与所述第一源/漏电极、栅电极和肖特基电极中的至少一个电连接的多个接合垫，
所述半导体层在俯视时通过假想的分界线分割成多个单元，
以在所述多个单元中延展的方式形成有所述漂移区域和第二源/漏电极，
所述多个单元由其中形成有所述场效应晶体管的晶体管单元，和其中形成有所述肖特基电极的二极管单元构成，
在俯视时，由所述晶体管单元包围的一个以上的所述二极管单元岛状地配置，所述接合垫位于该岛状地配置的一个以上的所述二极管单元的所述肖特基电极的上方。
2.如权利要求1所述的半导体元件，其特征在于：
所述第一源/漏电极以与所述第一源极/漏极区域和第二导电型区域的所述上面连接的方式设置。
3.如权利要求1所述的半导体元件，其特征在于：
所述第一导电型是n型，所述第二导电型是p型。
4.如权利要求1所述的半导体元件，其特征在于：
所述半导体层由宽禁带半导体构成。
5.如权利要求1所述的半导体元件，其特征在于：
所述多个接合垫通过导线相互连接。
6.如权利要求1所述的半导体元件，其特征在于：
所述接合垫具有边长为0.3mm以上的四边形的形状。
7.如权利要求1所述的半导体元件，其特征在于：
全部的所述晶体管单元的俯视时的面积相对所述半导体元件的俯视时的面积的比例为50％以上且99％以下。
8.如权利要求1所述的半导体元件，其特征在于：
所述肖特基电极的面积相对所述半导体元件的俯视时的面积的比例为1％以上且50％以下。
9.如权利要求1所述的半导体元件，其特征在于：
所述二极管单元的所述肖特基电极的面积比所述晶体管单元的所述第二导电型区域的俯视时的面积大。
10.一种电气设备，其特征在于，包括：
交流驱动装置；和构成该交流驱动装置的逆变电源电路的权利要求1～9中任一项所述的半导体元件，
所述半导体元件作为臂模块被插入。
11.如权利要求10所述的电气设备，其特征在于：
基于由所述交流驱动装置内的电感负载产生的反电动势，而施加于所述场效应晶体管的寄生二极管，以及由所述漂移区域和与该漂移区域的上面形成肖特基结的肖特基电极构成的肖特基二极管的电压，比所述肖特基二极管的正方向的上升沿电压大，并且比所述寄生二极管的正方向的上升沿电压小。
12.如权利要求10所述的电气设备，其特征在于：
所述交流驱动装置是由所述逆变电源电路驱动的交流电动机。
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