CN109346508B - 具有电流路径方向控制功能的半导体结构 - Google Patents

具有电流路径方向控制功能的半导体结构 Download PDF

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CN109346508B
CN109346508B CN201810990282.2A CN201810990282A CN109346508B CN 109346508 B CN109346508 B CN 109346508B CN 201810990282 A CN201810990282 A CN 201810990282A CN 109346508 B CN109346508 B CN 109346508B
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江启文
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Abstract

本发明公开了一种具有电流路径方向控制功能的半导体结构，包含有基板及其上具有磊晶层，其具有第一导电型，第一掺杂区位于基板上及磊晶层一侧，第一掺杂区具有第一或第二导电型，第二掺杂区包覆在磊晶层中，第二掺杂区具有第二导电型，第三掺杂区位于磊晶层且位于第一、第二掺杂区间，藉由磊晶层分隔第一、第二、第三掺杂区，第三掺杂区具有第二导电型，第四掺杂区包覆于第三掺杂区中，第四掺杂区具有第一导电型，第五掺杂区包覆于第一掺杂区中，第五掺杂区与第一掺杂区相反型态，当基板接收电流可选择性自磊晶层、第一、第二、第三、第四、第五掺杂区传输并控制电流流向。

Description

具有电流路径方向控制功能的半导体结构
技术领域
本发明关于一种半导体结构，特别关于一种具有电流路径方向控制功能的半导体结构。
背景技术
现有的半导体装置，例如功率装置，为了要降低操作时所产生的正向偏压，及减少电流拥挤效应，可以降低电力耗损或提高半导体电子元件应在效率。但在平面式接口的半导体装置，例如高压的硅半导体元件无法进一步改善此些特性，必须通过更精细的结构设计或是创新半导体装置设计。
然而，现有的创新半导体装置设计或结构设计，例如，通过缩短漂移区的长度、降低漂移区的电阻、增加电流分散效应等，以用于减少电流拥挤效应，及可以用于降低顺向操作电压。并且，可以在结构上维持主动区的高崩溃电压，以降低漏电流并增加元件的可靠性，例如藉由抗静电放电及高温应用等方式。
即便利用结构的改良，例如形成台面式接口终止延伸结构，虽可以改善上述现有的平面式接口的半导体装置缺失，但上述的结构及改变漂移区长度的技术特征，无法有效控制电流的流向，容易使电流流经此一半导体结构时，往其它掺杂区域流失，造成通过半导体装置的电流不稳。
因此，本发明为了在半导体装置中能够有效控制电流传输路径，提出一种具有电流路径方向控制功能的半导体结构，作为各个电子元件连接时，避免电流在结构中传输时，不会从边缘流散。
发明内容
本发明的主要目的在于提供一种具有电流路径方向控制功能的半导体结构，利用各掺杂区相同或不相同的半导体型态，以控制整体结构的电流传导路径方向，以避免在设计时，因无法有效控制电流路径而导致电流过多的消耗。
本发明的另一目的在于提供一种具有电流路径方向控制功能的半导体结构，可以应用在各种电子装置，例如内存、微处理器等产品，并且可以提升这些产品效能。
因此，为了实现上述的目的，本发明提供一种具有电流路径方向控制功能的半导体结构，包含有一基板，及其上具有一磊晶层，磊晶层具有第一导电型，第一掺杂区位于基板上并位于磊晶层一侧，第一掺杂区具有第一导电型或第二导电型，第二掺杂区位于磊晶层以被磊晶层包覆，第二掺杂区的顶部露出在磊晶层的顶部，第二掺杂区具有第二导电型，第三掺杂区位于磊晶层且位于第二掺杂区及第一掺杂区间，藉由磊晶层分隔第三掺杂区、第一掺杂区及第二掺杂区，第三掺杂区的顶部露出在磊晶层的顶部，第三掺杂区具有第二导电型，第四掺杂区位于第三掺杂区中以被第三掺杂区包覆，第四掺杂区的顶部露出在第三掺杂区的顶部，第四掺杂区具有第一导电型，第五掺杂区位于第一掺杂区中以被第一掺杂区包覆，第五掺杂区的顶部露出在第一掺杂区的顶部，第五掺杂区与第一掺杂区相反型态，当基板接收一电流可选择性自磊晶层、第一、第二、第三、第四、第五掺杂区传输，并可控制电流的流向。
在本发明中，第一导电型为n型，第二导电型为p型；或，第一导电型为p型，第二导电型为n型。
在本发明中，基板可为第一或第二导电型。
在本发明中，磊晶层、第二、第四、第五掺杂区的顶部，各自更可选择性设有一连接元件，其可选择性将磊晶层、第二、第四、第五掺杂区电性连接。
在本发明中，连接元件可为p-n二极管、肖特基二极管、快速恢复二极管、晶体管、晶体闸流管、金属氧化物半导体场效晶体管或绝缘栅双极晶体管。
在本发明中，第一、第二、第三掺杂区周围还可环设一隔离区，以避免电流往第一掺杂区、第二掺杂区、第三掺杂区外部偏离。隔离区可为介电质、多晶硅或非晶硅；隔离区可藉由反应离子蚀刻形成；而隔离区的侧壁角度可为55°～125°。
下面通过具体实施例详加说明，当更容易了解本发明的目的、技术内容、特点及其所达成的功效。底下藉由具体实施例配合所附的图式详加说明，当更容易了解本发明的目的、技术内容、特点及其所达成的功效。
附图说明
图1为本发明第一实施例的结构示意图。
图2为本发明第二实施例的结构示意图。
图3为本发明第三实施例的结构示意图。
图4为本发明第四实施例的结构示意图。
图5为本发明第五实施例导入电流的示意图。
图6为本发明第六实施例的结构示意图。
图7a～图7d为本发明制作磊晶层与掺杂区的步骤的结构示意图。
图8a～图8g为利用本发明制作阻隔区的应用实施例的示意图。
附图标记说明：10、10’-半导体结构；12-基板；14-磊晶层；16-第一掺杂区；18、18’-第二掺杂区；20-第三掺杂区；22、22’-第四掺杂区；24-第五掺杂区；26、28、30、32、26’、28’、30’、32’-连接元件；34、34’-金属元件；36-金属层；38-隔离区；40-基板；42-磊晶层；44-二氧化硅；46-缺口；48-第一掺杂区；I-电流。
具体实施方式
随着半导体的出现，其重要性相当巨大，现今大部分的电子产品，如计算机、智能型手机或是数字电子装置中的核心单元，皆与半导体有着极为密切的关联，许多不同的现有半导体装置，对于其结构的改良，以用于提升电子产品的效能，而本发明更能有效控制电流路径方向，以避免电流在结构中传输时会造成多余的相互干扰。
首先，请参照本发明图1所示，一种具有电流路径方向控制功能的半导体结构10包含有一基板12，基板上12具有一磊晶(EPI)层14，第一掺杂区16位于基板12上，并位于磊晶层14的一侧；第二掺杂区18位于磊晶层14中，以被磊晶层14所包覆，第二掺杂区18的顶部露出于磊晶层14的顶部；第三掺杂区20亦位于磊晶层14中，且同时位于第一掺杂区16及第二掺杂区18间，磊晶层14藉由第三掺杂区20分隔第一掺杂区16及第二掺杂区18，第三掺杂区20的顶部露出于磊晶层14的顶部；第四掺杂区22位于第三掺杂区20中，以被第三掺杂区20包覆，第四掺杂区22的顶部露出于第三掺杂区20的顶部；第五掺杂区24位于第一掺杂区16中，以被第一掺杂区16包覆，第五掺杂区24的顶部露出于第一掺杂区16的顶部。在本发明中，不限制各掺杂区的形状、深度或是浓度，也不限制掺杂区所露出的高度，本实施例主要先明确揭露各掺杂区的位置关系，本发明不以此为限制。
承接上段，磊晶层14具有第一导电型，而第一掺杂区16则可以具有第一导电型或第二导电型，第二掺杂区18则具有第二导电型，第三掺杂区20具有第二导电型，第四掺杂区22具有第一导电型，第五掺杂区24则与第一掺杂区16的导电型态相反，当第一掺杂区16为第一导电型则第五掺杂区24为第二导电型，反之亦然。在本发明中，第一导电型为n型时，第二导电型为p型，或是，当第一导电型为p型时，第二导电型为n型。另外，本发明中的基板12可以是第一导电型或是第二导电型，则不一定要与上述相同。
例如，当本案的磊晶层14为第一导电型n型时，基板12可以与磊晶层相同型态或是相异型态，可以是第一导电型n型或是第二导电型p型，本发明就不多做限制，可依照使用者设计而定。而磊晶层14上的第二掺杂区18、第三掺杂区20则需要与磊晶层14成为相反的导电型态，此时第二掺杂区18及第三掺杂区20必须为第二导电型p型。然而，磊晶层14一侧的第一掺杂区16则可以是第一导电型n型或是第二导电型p型，在此可以第二导电型p型为例说明，则第五掺杂区24必须为第一导电型p型。上述仅为本发明的实施例说明，不以此些n型或p型为限制，主要是以上述第一掺杂区16、第二掺杂区18、第三掺杂区20、第四掺杂区22、第五掺杂区24与磊晶层14的导电型态关系为限制。
另外，请参照本发明图2所示，在磊晶层14、第二掺杂区18、第四掺杂区22、第五掺杂区24的顶部，还能选择性设有一连接元件26、28、30、32，这些连接元件26、28、30、32也可以选择相连接或是连接至外部的结构，例如连接元件28可以藉由一金属元件34连接至外部，或是请参照本发明图3所示，连接元件28也可藉由金属元件34电性连接至连接元件30，本实施例不以此为发明的限制，使用者可依照需求自行设定连接关系。或是，请参照本发明图4所示，当二个以上的半导体结构相连接时，在此以二个半导体结构10、10’为例说明，这些半导体结构中的连接元件26、28、30、32、26’、28’、30’、32’也可以彼此选择性电性连接，例如连接元件30可以藉由金属元件34电性连接至连接元件28’。本实施例中的连接元件26、28、30、32、26’、28’、30’、32’可为p-n二极管、肖特基(Schottky)二极管、快速恢复二极管(FRD)、晶体管(Transistor)、晶体闸流管(Thyrister)、金属氧化物半导体场效晶体管(MOSFET)或绝缘栅双极晶体管(IGBT)，本发明不限制是否需设置连接元件或连接元件应为何，可依照使用者的需求或制程而定。
底下以一实施例为例，说明本发明控制电流路径方向的方式，请参照本发明图5所示，基板12可以连接外部的金属层36，以自外部金属层36接收电流I，并可选择性自磊晶层14、第一掺杂区16、第二掺杂区18、第三掺杂区20、第四掺杂区22、第五掺杂区24传输，例如当第二掺杂区18中设有一连接元件26，藉由金属元件34电性连接至外部半导体结构10’的第四掺杂区22’的连接元件26’时，会利用各掺杂区的导电型态及结构以控制电流的流向，如此时电流I会因为第一掺杂区16的阻隔而不往外部流动，以使电流I藉由第二掺杂区18流向连接元件26，并自金属元件34传输至第四掺杂区22’的连接元件26’，电流I可以再从第四掺杂区22’流向另一金属元件34’以传输至第五掺杂区24’中。使用者可以自行依照制程设定，而任意进行电性连接，本发明主要利用各掺杂区与磊晶层的导电型态，以进行电流路径流向的限制。
除了上述的结构外，请参照本发明图6所示，在第一掺杂区16、第二掺杂区18、第三掺杂区20的周围可以环设一隔离区38，其为一沟槽式(trench)，在本实施例中，隔离区38可为介电质(Dielectrics)、多晶硅(Poly Si)或非晶硅(Amorphous Si)，隔离区38藉由反应离子蚀刻(Reactive-Ion Etching，RIE)形成在第一掺杂区16、第二掺杂区18、第三掺杂区20周围，隔离区38设置时的侧壁角度可为55°～125°，本实施例以90°为例说明，本发明不限制隔离区38的材质、深度或设置角度，还可利用隔离区38隔离电流的流向，更可避免电流往第一掺杂区16、第二掺杂区18、第三掺杂区20的外部偏离。
一般而言，半导体结构可应用蚀刻的方式对待蚀刻物进行向下或二侧的侵蚀，以形成用户想要的结构，接着，请参照本发明图7a～图7d所示，本发明可以利用下列方式形成磊晶层及掺杂区，首先如图7a所示，可以先在一基板40上形成一磊晶层42，并利用二氧化硅44的光罩形成一植入(implant)缺口46，接着如图7b所示，此时可以在缺口46中植入与磊晶层42相同或不同的导电型态的第一掺杂区48。接着，将二氧化硅44移除，并对磊晶层42及第一掺杂区48进行沉积(deposit)，沉积后如图7c所示，再形成二氧化硅44光罩于第一掺杂区48上，并可形成缺口46，并在缺口46中植入与第一掺杂区48，藉此反复进行如图7c的动作后，可以依使用者需求调整次数，以形成如图7d所示，较厚的第一掺杂区48。本发明可以依上述的制程方法形成磊晶层与各掺杂区，并可以完成本发明具有电流路径方向控制功能的半导体结构，并且，也可以利用上述的制程方法，于半导体结构中形成阻隔区，以形成如图8a、图8b、图8c、图8d、图8e、图8f及图8g所示的结构，并且用此结构对电流I进行路径方向的控制。
有鉴于一般电子装置的设计复杂，本发明不限制连接元件应如何连接，或是可以组合多少组半导体结构，主要是揭露此一特殊的各掺杂区与磊晶层的结构关系，利用各掺杂区与磊晶层的导电型态，避免电流传输时，会容易往其它路径偏移，此一半导体结构应用在各种电子装置时，可以避免电流传输时产生相互干扰，以提升电子装置的效能。
以上所述的实施例，仅为说明本发明的技术思想及特点，目的在使熟习此项技艺的人士足以了解本发明的内容，并据以实施，当不能以之限定本发明的保护范围，即大凡依本发明所揭示的精神所作的均等变化或修饰，仍应涵盖在本发明的保护范围。

Claims (9)

1.一种具有电流路径方向控制功能的半导体结构，其特征在于，包含：
一基板；
一磊晶层，其位于该基板上，该磊晶层具有第一导电型；
一第一掺杂区，其位于该基板上，并位于该磊晶层的一侧，该第一掺杂区具有该第一导电型或一第二导电型；
一第二掺杂区，其位于该磊晶层，以被该磊晶层包覆，该第二掺杂区的顶部露出于该磊晶层的顶部，该第二掺杂区具有该第二导电型；
一第三掺杂区，其位于该磊晶层，且位于该第二掺杂区及该第一掺杂区间，藉由该磊晶层分隔该第三掺杂区、该第一掺杂区及该第二掺杂区，该第三掺杂区的顶部露出于该磊晶层的该顶部，该第三掺杂区具有该第二导电型；
一第四掺杂区，其位于该第三掺杂区中，以被该第三掺杂区包覆，该第四掺杂区的顶部露出于该第三掺杂区的该顶部，该第四掺杂区具有该第一导电型；以及
一第五掺杂区，其位于该第一掺杂区中，以被该第一掺杂区包覆，该第五掺杂区的顶部露出于该第一掺杂区的顶部，该第五掺杂区具有与该第一掺杂区相反的型态，当该基板接收一电流，可选择性自该磊晶层、该第一掺杂区、该第二掺杂区、该第三掺杂区、该第四掺杂区、该第五掺杂区传输，并可控制该电流的流向；其中
该第一掺杂区、该第二掺杂区、该第三掺杂区的周围进一步环设一隔离区，以避免该电流往该第一掺杂区、该第二掺杂区、该第三掺杂区的外部偏离。
2.如权利要求1所述的具有电流路径方向控制功能的半导体结构，其特征在于，该第一导电型为n型，该第二导电型为p型。
3.如权利要求1所述的具有电流路径方向控制功能的半导体结构，其特征在于，该第一导电型为p型，该第二导电型为n型。
4.如权利要求1所述的具有电流路径方向控制功能的半导体结构，其特征在于，该基板为该第一导电型或该第二导电型。
5.如权利要求1所述的具有电流路径方向控制功能的半导体结构，其特征在于，该磊晶层、该第二掺杂区、该第四掺杂区、该第五掺杂区的顶部分别设有一连接元件，多个连接元件将该磊晶层、该第二掺杂区、该第四掺杂区、该第五掺杂区电性连接。
6.如权利要求5所述的具有电流路径方向控制功能的半导体结构，其特征在于，该多个连接元件为二极管或晶体管。
7.如权利要求1所述的具有电流路径方向控制功能的半导体结构，其特征在于，该隔离区为介电质、多晶硅或非晶硅。
8.如权利要求7所述的具有电流路径方向控制功能的半导体结构，其特征在于，该隔离区通过反应离子蚀刻形成。
9.如权利要求7所述的具有电流路径方向控制功能的半导体结构，其特征在于，该隔离区的侧壁角度为55゜~125゜。
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