CN101183683B - 用于减小mosfet器件中的浮体效应的方法和结构 - Google Patents

用于减小mosfet器件中的浮体效应的方法和结构 Download PDF

Info

Publication number
CN101183683B
CN101183683B CN2007101613953A CN200710161395A CN101183683B CN 101183683 B CN101183683 B CN 101183683B CN 2007101613953 A CN2007101613953 A CN 2007101613953A CN 200710161395 A CN200710161395 A CN 200710161395A CN 101183683 B CN101183683 B CN 101183683B
Authority
CN
China
Prior art keywords
region
source region
forms
chamber
soi layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN2007101613953A
Other languages
English (en)
Other versions
CN101183683A (zh
Inventor
朱慧珑
梁擎擎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Core Usa Second LLC
GlobalFoundries Inc
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of CN101183683A publication Critical patent/CN101183683A/zh
Application granted granted Critical
Publication of CN101183683B publication Critical patent/CN101183683B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743—Making of internal connections, substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78612—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Thin Film Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

一种场效应晶体管(FET)器件包括：体衬底，在所述体衬底之上形成的栅极绝缘层，在与所述体衬底相关联的有源器件区域中形成的源极和漏极区域，每个所述源极和漏极区域相对于所述有源器件区域的体区域限定了p/n结，以及在限定在所述源极区域中的腔内形成的跨过所述源极区域的所述p/n结并进入到所述体区域中的导电插塞，其中所述导电插塞有助于所述体区域与所述源极区域之间的放电通路。

Description

用于减小MOSFET器件中的浮体效应的方法和结构
技术领域
本发明通常涉及半导体器件处理技术和，更具体而言，涉及一种用于减小包括绝缘体上硅(SOI)器件的金属氧化物半导体场效应晶体管(MOSFET)器件中的浮体效应的方法和结构。
背景技术
对于集成电路增加的性能、功能性和制造经济的要求已导致了极大的集成密度以便减小信号传输时间并增加抗噪声度，同时也增加了单个的工艺序列在芯片或晶片上可以形成的电路与器件的数目。将器件按比例缩小至这样小的尺寸限制了操作裕度并使增加芯片上所形成的半导体器件电特性的均匀性成为必需。
为满足后者的标准，使用绝缘体上硅(SOI)晶片以利用在体硅“处理”衬底之上的绝缘体上形成的通过其有源层的单晶硅的改善的质量。可以在其它类型的半导体材料及其合金的相似结构中开发相似的特性。有源SOI层的半导体材料的改善的质量允许晶体管和其它器件在具有良好电性能均匀性的情况下按比例缩小至极小的尺寸。
不幸地，由于支持半导体材料的改善的质量的发展的绝缘层(也称为掩埋氧化物层或BOX)的存在还产生了在本领域称为晶体管结构中的“浮体效应”的问题。浮体效应是在具有绝缘层的衬底上形成的晶体管所特有的。具体而言，在晶体管导电沟道和浮体端处形成相对极的二极管结的源极/漏极扩展和晕区域电隔离中性浮体，同时栅极电极通过介质与导电沟道绝缘。衬底中的绝缘层完成了导电沟道的绝缘并因此防止了在浮体中产生的任何的电荷放电。当晶体管不导通时，根据源极和漏极二极管特性，电荷注入到中性体中在导电沟道中产生电压。
在强场梯度漏极区域附近的热电子产生的过剩载流子引起了浮体效应，导致了SOI器件的体电势升高。其引起了阈值电压的减小，导致了输出特性的扭折(Kink)。由晶体管导电沟道中的电荷收集产生的电压具有改变晶体管的开关阈值的效应。该效应回过头来改变了信号同步和信号传输速度，因为即使当跨越给定电路的阈值电压的均匀性并不好时，任何晶体管也将具有有限的非瞬态信号的转换速率和上升和下降时间。SOI开关电路，具体而言，受到严重的动态浮体效应如滞后和历史效应的损害。SOI开关电路中扭折效应的产生极依赖于工作频率，并产生类Lorentzian噪声过冲和谐波失真。在SOI MOSFET中软误差问题同样更为严重。
为限制在浮体中构建的电荷，体接触并入到器件中。然而，该方法不利地影响了器件的密度。可选地，设计源极和漏极的二极管特性。例如，通过减小源极/漏极与体结之间的势垒减少浮体电荷，例如通过在p/n结处产生注入缺陷，其是频率无关的方法。不幸地，与开关器件中的源极二极管泄漏相反，漏极二极管泄漏增加了电路耗散的热功率并降低了实际的开关电流，导致较低的速度。
因此，希望能够以不导致增加的漏极泄漏电流、减小的集成电路密度、增加的热功率和电路速度降低的方式减小(在SOI器件和体硅器件中的)浮体效应。
发明内容
通过一种场效应晶体管(FET)器件克服或减轻了现有技术的前述缺陷和不足，其包括体衬底，在所述体衬底之上形成的栅极绝缘层，在与所述体衬底相关联的有源器件区域中形成的源极和漏极区域，每个所述源极和漏极区域相对于所述有源器件区域的体区域限定了p/n结，以及在限定在所述源极区域中的腔内形成的跨过所述源极区域的p/n结并进入到所述体区域中的导电插塞，其中所述导电插塞有助于所述体区域与所述源极区域之间的放电通路。
在另一实施例中，一种用于形成场效应晶体管(FET)器件的方法包括：在体衬底之上形成栅极绝缘层；在与所述体衬底相关联的有源器件区域中形成源极和漏极区域，每个所述源极和漏极区域相对于所述有源器件区域的体区域限定了p/n结；以及形成在限定在所述源极区域中的腔内形成的跨过所述源极区域的所述p/n结并进入到所述体区域中的导电插塞；其中所述导电插塞有助于所述体区域与所述源极区域之间的放电通路。
在又一实施例中，一种用于减小绝缘体上硅(SOI)场效应晶体管(FET)器件中的浮体效应的方法包括：在体衬底之上形成掩埋绝缘层；在所述掩埋绝缘层之上形成绝缘体上硅(SOI)层；在所述SOI层之上形成栅极绝缘层；在所述SOI层内形成源极和漏极区域，每个所述源极和漏极区域相对于所述SOI层内的有源器件区域的体区域限定了p/n结；以及形成在限定在所述源极区域中的腔内形成的跨过所述源极区域的所述p/n结并进入到所述体区域中的导电插塞，其中所述腔和所述插塞沿朝向所述漏极的方向横向延伸跨过所述源极区域，并跨过所述源极区域的所述p/n结进入到所述掩埋绝缘层之上的所述体区域中；其中所述导电插塞有助于所述体区域与所述源极区域之间的放电通路。
附图说明
参考示例性的附图，其中在附图中相似的元素采用相同的标号：
图1(a)至1(k)是根据所述发明的实施例的一种用于减小绝缘体上硅(SOI)晶体管器件中的浮体效应的方法和结构的一系列截面视图；以及
图2(a)至2(i)是根据所述发明的可选的实施例的一种用于减小体硅晶体管器件中的浮体效应的方法和结构的一系列截面视图。
具体实施方式
在此公开了一种用于减小包括绝缘体上硅(SOI)类型器件的MOSFET器件中的浮体效应而没有结泄漏的方法和结构。简要声明，在此公开的实施例提供了通过晶体管器件源极区域形成的金属插塞，以便该插塞延伸到晶体管的体中并提供了源极与体积之间的短路。
起始参照图1(a)至1(k)，其示出了根据本发明的实施例的一种用于减小绝缘体上硅(SOI)晶体管器件中的浮体效应的方法和结构的一系列截面视图。如图1(a)所示，体硅层102具有在其上形成的掩埋绝缘物(例如氧化物)层(BOX)104。接着在BOX层104之上形成晶体硅层106；因此，术语绝缘体上硅(SOI)同样用来描述层106，其中有源晶体管器件在其中形成。在示例性的实施例中，SOI层106(例如，对于N型器件)为相对低掺杂浓度(例如，约1×1017atoms/cm3)的P型层。如同样在图1(a)中所示出的，形成浅沟槽隔离(STI)区域108以电隔离在SOI层106中所随后形成的晶体管与其它器件。
在图1(b)中，在SOI层106之上形成热氧化物层110(例如约1-5nm量级的厚度)，并使用其作为栅极绝缘体材料。然而，还可以使用其它栅极绝缘材料。然后，在栅极氧化物110之上形成多晶硅层112(例如约100-200nm量级的厚度)，随后是构图的光致抗蚀剂材料114，其限定了栅极电极结构。接下来，如在图1(c)中所示，将光致抗蚀剂图形转移到多晶硅层112中以形成栅极电极116，如本领域所公知，在其之后在栅极侧壁上形成氧化物侧壁间隔物118。
参考图1(d)，然后使器件经受锗(Ge)或其它适宜的中性种(species)的注入，产生具有相对于硅的蚀刻选择性的区域。将在此后更加详细地描述中性注入的目的。然后，使用高温退火修复硅的注入损伤，得到如图1(e)所示的SiGe区域120。继续到图1(f)，根据FET源极/漏极形成技术进行晕(有角度的箭头)和扩展(垂直箭头)注入。
然后如图1(g)所示，如本领域所公知，邻近间隔物118形成第二组侧壁间隔物122(例如，氮化物)，以便形成深源极/漏极注入。然后进行另一次退火以激活源极和漏极的掺杂剂，接着在源极/漏极区域与体106之间限定p/n结124，如图1(h)所示。前进到图1(i)，然后在栅极116以及源极和漏极区域之上以本领域公知的方法形成硅化物接触126。例如，在该结构之上形成硅化物形成金属例如镍，接着退火(例如，约300℃到约500℃)以形成NiSi。之后，通过湿法蚀刻去除绝缘区域之上的未反应的镍。然而，在硅化之后，接着在器件之上形成光致抗蚀剂层128，并以如图1(i)中所进一步示出的暴露器件的源极区域的方式构图。可选地，可以在硅化之后形成薄氮化物层(未示出)以保护NiSi接触和器件免受湿气和活动离子的影响。该薄氮化物层还在常规接触孔蚀刻中充当蚀刻停止层(stopper)。然而，可选的氮化物层基本上与本发明的实施例不相关。
参考图1(j)，使用多步蚀刻首先去除源极侧NiSi，接着去除源极区域中的掺杂的硅，之后去除源极侧SiGe区域120。具体而言，以各向同性的方式选择性蚀刻SiGe区域以沿横向蚀刻材料，产生腔130。应该注意，腔130(初始形成的SiGe区域)延伸跨过源极侧的p/n结并进入到SOI体106中。同样应该注意，在器件的漏极侧和栅极116中的SiGe区域120不受蚀刻的影响并保留在器件中。可选地，在图1(d)中的Ge注入之前，构图器件以便保护栅极和漏极区域。
在任一实例中，然后在去除光致抗蚀剂128之后，在腔130中形成金属插塞132，如图1(k)所示。在示例性的实施例中，以与半导体器件的上布线层中的金属过孔形成相似的方法实现插塞形成。例如，在源极侧腔130中保形淀积薄钛氮化物(TiN)衬里层134，接着通过金属插塞材料136例如钨(W)的淀积和回蚀刻完成插塞132。如此配置，插塞132提供了将过剩体电荷传导到源极端子(对于NFET器件其被典型地连接到地)的源极到体接触。在形成插塞132之后，继续常规处理以完成器件(例如，层间介质层形成、过孔/线路形成和其它后段制程)。
由于相对于源极和漏极区域的SOI层106的较浅的深度，使用Ge掺杂的层120产生横向蚀刻分布以便插塞132能够沿器件沟道的方向横向延伸并由此跨过p/n结124并进入到体区域中。然而，由于体硅器件不具有掩埋绝缘层，同样形成源极到体的插塞以减小浮体效应。另外，在无BOX层存在的情况下，插塞形成方法因为不需要横向蚀刻分布所以变得更简单，因为可沿向下的方向形成插塞以桥接源极侧p/n结。
因此，图2(a)到2(i)是根据本发明的可选的实施例的一种用于减小在体硅晶体管器件中的浮体效应的方法和结构的一系列截面视图。简单起见，使用与图1中的实施例相同的参考标号表示相似元素。如图2(a)中所示，体硅层102(无掩埋绝缘层)具有在其中形成的STI区域108以便将在衬底102的体区域106中随后形成的晶体管与其它器件电隔离。
与图1(b)相似，图2(b)示出了在体衬底102之上形成用作栅极绝缘层材料的热氧化物层110(例如约1-5nm量级的厚度)。然而，再一次，同样可以使用其它栅极绝缘材料。然后，在栅极氧化物110上形成多晶硅层112(例如约100-200nm量级的厚度)，接着是构图的光致抗蚀剂材料114，其限定了栅极电极的结构。如接下来在图2(c)中所示出的，将光致抗蚀剂图形转移到多晶硅层112中以形成栅极电极116，在其之后，如本领域所公知，在栅极侧壁上形成氧化物侧壁间隔物118。
然而尽管图1(d)的SOI实施例实现了中性种(Ge)注入的使用，图2(d)的体硅实施例直接进行根据FET源极/漏极形成技术的晕(有角度的箭头)和扩展(垂直箭头)注入。然后，如图2(e)所示，如本领域所公知，邻近间隔物118形成第二组侧壁间隔物122(例如，氮化物)，以便形成深源极/漏极注入。然后进行另一次退火以激活源极和漏极掺杂剂，然后在源极/漏极区域与体106之间限定p/n结124，如图2(f)中所示。
前进到图2(g)，然后以本领域公知的方法在栅极116以及源极和漏极区域之上形成硅化物接触126。例如，在该结构之上形成硅化物形成金属例如镍，接着退火(例如，约300℃到约500℃)以形成NiSi。之后，通过湿法蚀刻去除绝缘区域之上的未反应的镍。如在SOI实施例中的情况，在硅化之后，接着在器件之上形成光致抗蚀剂层128，并以如图2(g)中所进一步示出的暴露器件的源极区域的方式构图。可选地，可以在硅化之后形成薄氮化物层(未示出)以保护NiSi接触免受源极构图的影响。
参考图2(h)，使用多步蚀刻首先去除源极侧NiSi，接着去除源极区域中的掺杂的硅。尽管图1(j)中的SOI实施例利用在源极侧的通过SiGe区域的横向蚀刻，图2(h)的实施例延伸了源极侧掺杂的硅的垂直蚀刻向下通过源极区域底，跨过在源极侧的p/n结124并进入到体硅102中，由此产生腔230。
最终，在图2(i)中，然后在去除光致抗蚀剂128之后在腔230中形成金属插塞232。例如，在源极侧腔230中保形淀积薄钛氮化物(TiN)衬里层234，接着通过金属插塞材料236例如钨(W)的淀积和回蚀刻完成插塞232。如此配置，插塞232提供了将过剩体电荷传导到源极端子(对于NFET器件其被典型地连接到地)的源极到体接触。因为没有氧化物层，在源极区域之下存在足够的空间以允许形成与体硅102/体区域106充分电接触的腔(由此的插塞232)。在形成插塞232之后，继续常规处理以完成器件(例如，层间介质层形成，过孔/线路形成和其它后段制程)。
虽然通过参考优选的实施例或多个实施例描述了本发明，但本领域人员应该理解在不背离本发明范围的情况下可以实施各种改变并且其元素可被等效物替代。另外，根据本发明的教导可实施许多修改以适应具体情况或材料而不背离其基本范围。因此，旨在本发明不受限于公开作为用于实施本发明所构思的最佳模式的具体实施例，而是本发明将包括落入所附权利要求范围内的所有实施例。

Claims (13)

1.一种场效应晶体管FET器件，包括：
体衬底；
掩埋绝缘层，其在所述体衬底之上形成；
绝缘体上硅SOI层，其在所述掩埋绝缘层之上形成；
栅极绝缘层，其在所述SOI层之上形成；
源极和漏极区域，其在与所述SOI层相关联的有源器件区域中形成，每个所述源极和漏极区域相对于所述有源器件区域的体区域限定了p/n结；以及
导电插塞，形成在所述SOI层中的腔内，所述导电插塞和所述腔包括垂直部分和水平部分，所述垂直部分位于所述源极区域中并向下延伸穿过所述源极区域，所述水平部分在所述源极区域之下，并且所述水平部分朝向所述漏极的方向横向延伸并跨过所述源极区域的p/n结而进入到所述体区域中；
其中所述导电插塞形成了所述体区域与所述源极区域之间的放电通路。
2.根据权利要求1的FET器件，其中所述导电插塞还包括在所述腔内形成的衬里材料和在所述衬里材料之上形成的金属填充材料。
3.根据权利要求2的FET器件，其中所述衬里材料包括氮化钛(TiN)。
4.根据权利要求2的FET器件，其中所述金属填充材料包括钨(W)。
5.根据权利要求1的FET器件，其中所述腔延伸通过在所述源极区域的顶表面上形成的硅化物接触。
6.一种用于形成场效应晶体管FET器件的方法，所述方法包括以下步骤：
在体衬底上形成掩埋绝缘层；
在所述掩埋绝缘层之上形成绝缘体上硅SOI层；
在所述SOI层之上形成栅极绝缘层；
在所述SOI层内形成源极和漏极区域，每个所述源极和漏极区域相对于所述SOI层内的有源器件区域的体区域限定了p/n结；以及
在所述SOI层内形成腔，所述腔包括垂直部分和水平部分，所述垂直部分位于所述源极区域中并向下延伸穿过所述源极区域，所述水平部分在所述源极区域之下，并且所述水平部分朝向所述漏极的方向横向延伸并跨过所述源极区域的所述p/n结而进入到所述体区域中；以及
在所述腔内形成导电插塞；
其中所述导电插塞形成了所述体区域与所述源极区域之间的放电通路。
7.根据权利要求6的方法，其中所述导电插塞还包括在所述腔内形成的衬里材料和在所述衬里材料之上形成的金属填充材料。
8.根据权利要求7的方法，其中所述衬里材料包括氮化钛(TiN)。
9.根据权利要求7的方法，其中所述金属填充材料包括钨(W)。
10.根据权利要求6的方法，其中所述腔延伸通过在所述源极区域的顶表面上形成的硅化物接触。
11.权利要求6的方法，还包括在所述器件的至少源极侧中注入中性掺杂剂种，配置所述中性掺杂剂种以产生相对于所述SOI层的蚀刻选择性的区域，其中所述蚀刻选择性的区域在所述腔的形成中有助于其各向同性、横向蚀刻。
12.根据权利要求11的方法，其中所述中性掺杂剂种包括锗(Ge)。
13.根据权利要求11的方法，其中在所述栅极绝缘层上形成栅极电极之后，并且在源极/漏极晕和扩展区域的注入之前，并且在所述源极和漏极区域的注入之前注入所述中性掺杂剂种。
CN2007101613953A 2006-11-16 2007-09-30 用于减小mosfet器件中的浮体效应的方法和结构 Expired - Fee Related CN101183683B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/560,412 US7670896B2 (en) 2006-11-16 2006-11-16 Method and structure for reducing floating body effects in MOSFET devices
US11/560,412 2006-11-16

Publications (2)

Publication Number Publication Date
CN101183683A CN101183683A (zh) 2008-05-21
CN101183683B true CN101183683B (zh) 2010-06-16

Family

ID=39416083

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2007101613953A Expired - Fee Related CN101183683B (zh) 2006-11-16 2007-09-30 用于减小mosfet器件中的浮体效应的方法和结构

Country Status (3)

Country Link
US (1) US7670896B2 (zh)
JP (1) JP5285260B2 (zh)
CN (1) CN101183683B (zh)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9412758B2 (en) * 2007-12-10 2016-08-09 Newport Fab, Llc Semiconductor on insulator (SOI) structure with more predictable junction capacitance and method for fabrication
KR100967017B1 (ko) * 2008-05-28 2010-06-30 주식회사 하이닉스반도체 반도체 소자의 제조 방법
CN102315271B (zh) * 2010-07-07 2013-04-24 中国科学院微电子研究所 半导体器件及其制作方法
US8409989B2 (en) 2010-11-11 2013-04-02 International Business Machines Corporation Structure and method to fabricate a body contact
US8518764B2 (en) * 2011-10-24 2013-08-27 Freescale Semiconductor, Inc. Semiconductor structure having a through substrate via (TSV) and method for forming
KR101801077B1 (ko) 2012-01-10 2017-11-27 삼성전자주식회사 매립 배선을 갖는 반도체 소자 형성 방법 및 관련된 소자
US10084063B2 (en) * 2014-06-23 2018-09-25 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof
CN106229290B (zh) * 2016-07-27 2019-03-26 上海华虹宏力半导体制造有限公司 Soi器件结构及其制造方法
CN106098562A (zh) * 2016-08-03 2016-11-09 上海华虹宏力半导体制造有限公司 半导体结构及其形成方法
US11610843B2 (en) * 2021-03-08 2023-03-21 Globalfoundries U.S. Inc. Well tap for an integrated circuit product and methods of forming such a well tap
JP7464554B2 (ja) 2021-03-12 2024-04-09 株式会社東芝 高周波トランジスタ
CN117690794A (zh) * 2022-08-25 2024-03-12 长鑫存储技术有限公司 一种半导体结构的制作方法及其结构

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5965917A (en) * 1999-01-04 1999-10-12 Advanced Micro Devices, Inc. Structure and method of formation of body contacts in SOI MOSFETS to elimate floating body effects
US6441435B1 (en) * 2001-01-31 2002-08-27 Advanced Micro Devices, Inc. SOI device with wrap-around contact to underside of body, and method of making

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL8800847A (nl) * 1988-04-05 1989-11-01 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting met een soi-struktuur.
JPH02290059A (ja) * 1989-02-16 1990-11-29 Mitsubishi Electric Corp 半導体集積回路装置
JPH0783127B2 (ja) * 1989-04-20 1995-09-06 三菱電機株式会社 半導体装置
US5160989A (en) 1989-06-13 1992-11-03 Texas Instruments Incorporated Extended body contact for semiconductor over insulator transistor
JPH04150038A (ja) * 1990-10-15 1992-05-22 Seiko Epson Corp 半導体装置
US5245208A (en) * 1991-04-22 1993-09-14 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and manufacturing method thereof
JPH07302908A (ja) * 1994-05-02 1995-11-14 Fujitsu Ltd 半導体装置及びその製造方法
US5405795A (en) 1994-06-29 1995-04-11 International Business Machines Corporation Method of forming a SOI transistor having a self-aligned body contact
JPH08111529A (ja) * 1994-10-11 1996-04-30 Sony Corp 電界効果型半導体装置
JP2702427B2 (ja) * 1994-12-26 1998-01-21 日本電気アイシーマイコンシステム株式会社 半導体集積回路装置およびその製造方法
KR0179898B1 (ko) 1996-02-28 1999-04-15 문정환 반도체소자의 바디-콘택 구조
US5882981A (en) * 1996-07-30 1999-03-16 Texas Instruments Incorporated Mesa isolation Refill Process for Silicon on Insulator Technology Using Flowage Oxides as the Refill Material
JP2959514B2 (ja) * 1997-03-26 1999-10-06 日本電気株式会社 半導体装置及び半導体装置の製造方法
JP2870635B2 (ja) 1997-04-17 1999-03-17 日本電気株式会社 半導体装置
US5935766A (en) * 1997-08-07 1999-08-10 Advanced Micro Devices, Inc. Method of forming a conductive plug in an interlevel dielectric
US5963817A (en) * 1997-10-16 1999-10-05 International Business Machines Corporation Bulk and strained silicon on insulator using local selective oxidation
US6387739B1 (en) 1998-08-07 2002-05-14 International Business Machines Corporation Method and improved SOI body contact structure for transistors
JP3381646B2 (ja) * 1998-11-19 2003-03-04 日本電気株式会社 半導体装置およびその製造方法
US6441434B1 (en) 2000-03-31 2002-08-27 Advanced Micro Devices, Inc. Semiconductor-on-insulator body-source contact and method
JP2002064206A (ja) * 2000-06-09 2002-02-28 Toshiba Corp 半導体装置及びその製造方法
JP2002184975A (ja) * 2000-12-14 2002-06-28 Toshiba Corp パワーｍｏｓｆｅｔ及びその製造方法
US6620656B2 (en) 2001-12-19 2003-09-16 Motorola, Inc. Method of forming body-tied silicon on insulator semiconductor device
FR2838237B1 (fr) * 2002-04-03 2005-02-25 St Microelectronics Sa Procede de fabrication d'un transistor a effet de champ a grille isolee a canal contraint et circuit integre comprenant un tel transistor
US6784076B2 (en) * 2002-04-08 2004-08-31 Micron Technology, Inc. Process for making a silicon-on-insulator ledge by implanting ions from silicon source
EP1650796A3 (fr) * 2004-10-20 2010-12-08 STMicroelectronics (Crolles 2) SAS Procédé de prise de contact sur une région d'un circuit intégré, en particulier sur les électrodes d'un transistor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5965917A (en) * 1999-01-04 1999-10-12 Advanced Micro Devices, Inc. Structure and method of formation of body contacts in SOI MOSFETS to elimate floating body effects
US6441435B1 (en) * 2001-01-31 2002-08-27 Advanced Micro Devices, Inc. SOI device with wrap-around contact to underside of body, and method of making

Also Published As

Publication number Publication date
JP2008131038A (ja) 2008-06-05
US20080116514A1 (en) 2008-05-22
CN101183683A (zh) 2008-05-21
US7670896B2 (en) 2010-03-02
JP5285260B2 (ja) 2013-09-11

Similar Documents

Publication Publication Date Title
CN101183683B (zh) 用于减小mosfet器件中的浮体效应的方法和结构
CN102668093B (zh) 用于鳍式fet和三栅极器件的环绕式接触
TWI497571B (zh) 不對稱磊晶及其應用方法
CN100557786C (zh) 半导体器件及其制造方法
KR100442881B1 (ko) 고전압 종형 디모스 트랜지스터 및 그 제조방법
KR20050048675A (ko) 전계 효과 트랜지스터 및 전계 효과 트랜지스터 제조 방법
JP2014523133A (ja) ゲート抵抗器とダイオード接続ｍｏｓｆｅｔが統合されたパワーｍｏｓｆｅｔ
US20020098667A1 (en) Technique to produce isolated junctions by forming an insulation layer
JP4234586B2 (ja) 深い注入接合を有する出力ｍｏｓｆｅｔ
CN105336779B (zh) Ldmos器件及其形成方法
US6649964B2 (en) Body-to-substrate contact structure for SOI device and method for fabricating same
CN103441131A (zh) 部分耗尽绝缘体上硅器件结构
CN103545356A (zh) 新型金属/多晶硅栅极沟槽功率mosfet
US6495887B1 (en) Argon implantation after silicidation for improved floating-body effects
CN104240762A (zh) 反熔丝结构及编程方法
KR101128903B1 (ko) 수직형 반도체 장치 및 그 제조 방법
KR20110001893A (ko) 우물 영역을 포함하는 전자 장치
KR101259895B1 (ko) 횡형 절연 게이트 바이폴라 트랜지스터 및 그 제조 방법
CN109979993A (zh) 高压mos器件及其制作方法、电子装置
KR100796502B1 (ko) 반도체 소자의 제조 방법
KR20010048974A (ko) 반도체소자의 모스 트랜지스터 형성방법 및 그에 의해제조된 모스 트랜지스터
KR100492981B1 (ko) 래터럴 이중확산 모스 트랜지스터 및 그 제조방법
CN103426828A (zh) 一种基于绝缘体上硅材料的双极型高压cmos单多晶硅填充深沟道器件隔离工艺
KR100605908B1 (ko) 반도체 소자 및 그 제조 방법
CN110875396B (zh) 沟槽式栅极金氧半场效晶体管及其制造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
TR01 Transfer of patent right

Effective date of registration: 20171101

Address after: Grand Cayman, Cayman Islands

Patentee after: GLOBALFOUNDRIES INC.

Address before: American New York

Patentee before: Core USA second LLC

Effective date of registration: 20171101

Address after: American New York

Patentee after: Core USA second LLC

Address before: American New York

Patentee before: International Business Machines Corp.

TR01 Transfer of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20100616

Termination date: 20180930

CF01 Termination of patent right due to non-payment of annual fee