CN101136430A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN101136430A
CN101136430A CNA2007101417746A CN200710141774A CN101136430A CN 101136430 A CN101136430 A CN 101136430A CN A2007101417746 A CNA2007101417746 A CN A2007101417746A CN 200710141774 A CN200710141774 A CN 200710141774A CN 101136430 A CN101136430 A CN 101136430A
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China
Prior art keywords
metal layer
electrode
interarea
semiconductor
semiconductor substrate
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CNA2007101417746A
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CN101136430B (zh
Inventor
吉田哲哉
小林充幸
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Sanyo Electric Co Ltd
System Solutions Co Ltd
On Semiconductor Niigata Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Sanyo Semiconductor Co Ltd
Sanyo Semiconductor Manufacturing Co Ltd
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Publication of CN101136430A publication Critical patent/CN101136430A/zh
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Abstract

一种半导体装置，在分立半导体的芯片中，已知在半导体衬底的第一主面侧设置电流经路上的第一电极及第二电极，且可进行倒装片安装。但是，由于在衬底内的水平方向也流过电流，故存在电阻成分增加的问题。在第一主面侧设置与元件区域连接的第一电极及第二电极，在第二主面侧设置具有耐腐蚀性、耐氧化性的低电阻的厚膜金属层。由此降低衬底水平方向流过的电流的电阻成分。另外，通过适宜选择厚膜金属层的厚度，可抑制成本的增大，降低装置的电阻值。另外，由于厚膜金属层采用Au，从而可防止随经过时间引起的厚膜金属层的变色等不良。

Description

半导体装置
技术领域
本发明涉及半导体装置，特别是涉及降低装置的电阻实现高可靠性化的半导体装置。
背景技术
分立半导体的半导体装置(半导体芯片)多将分别与输入端子和输出端子连接的电极分别设于芯片的两主面(表面和背面)，但也知有将两电极设于芯片的一主面上，可进行倒装片安装等的类型。
参照图12，以MOSFET为例说明可进行现有的倒装片安装的类型的半导体装置。
在n+性半导体衬底133的上面设置n-型外延层，设定漏极区域134，并设置p型沟道层135。制作从沟道层135表面到达漏极区域134的槽136，将槽136的内壁由栅极氧化膜137覆盖，在槽136内设置栅极电极138，形成各晶格132。在与槽136邻接的沟道层135表面形成n+型源极区域139及p型体区140。槽136上由层间绝缘膜141覆盖。
源极电极142通过Al等喷溅而设置，且与各晶格132的源极区域139连接设置。栅极焊盘电极148是由与源极电极142相同的工序形成的电极，使栅极电极延伸进行接触。漏极焊盘电极114是由与源极电极142相同的工序形成的电极，其设于半导体芯片外周的外环115上。
源极补片电极111是与源极电极142接触的焊锡补片。在源极电极142上，在氮化膜156上设置接触孔，且设置成为焊锡底层的底层电极110，形成焊锡补片。栅极补片电极112及漏极补片电极113也为与源极补片电极111同样设置的焊锡补片。
金属板116将比Cu、Fe、Al等芯片尺寸小的金属片与晶片上的芯片配置的坐标一致地粘贴在半导体芯片的背面。利用该金属片116可降低漏极电阻。
这样，通过在半导体衬底(半导体芯片)的第一主面侧设置与输入端子及输出端子连接的电极(源极电极及漏极电极)、及根据情况设置与控制端子连接的电极(栅极电极)等与全部端子连接的电极，可倒装片安装该芯片。专利文献1；特开2002-368218号公报
图13是表示分立半导体的MOSFET中与输入端子IN连接的电极(例如源极电极S)及与输出端子OUT连接的电极(例如漏极电极D)的配置和形成于衬底上的电流经路的电阻成分的概略的图。
图13(A)是将源极电极S及漏极电极D分别设于第一主面Sf1及第二主面Sf2上的情况，图13(B)是将源极电极S及漏极电极D都设于第一主面Sf1上的情况。
衬底上，在高浓度半导体衬底HS上层叠低浓度半导体层LS，在低浓度半导体层LS表面设置MOSFET的元件区域e。
在图13(A)的情况中，如箭头所示，形成从第一主面Sf1侧的源极电极s通过低浓度半导体层LS、高浓度半导体衬底HS到达第二主面Sf2侧的漏极电极D的电流经路。因此，该情况下，作为从MOSFET的源极电极S向漏极电极D的电阻成分，主要为衬底的深度(垂直)方向的电阻Ra。
在这样现有的功率MOSFET中，由于漏极电极D从半导体芯片的背面(第二主面Sf2)取出，故电路经路沿衬底的深度(垂直)方向形成。因此，该情况下，为进一步降低漏极电阻，而使背面的漏极电极D的厚度尽可能薄地形成。
例如，在将使粘接性提高的Ti、防止焊锡向Si侧扩散的Ni分别形成为
Figure A20071014177400061
的膜厚后，将Au形成为
Figure A20071014177400062
的膜厚。
在例如将该半导体芯片倒装片安装时，需要将漏极电极D设于与源极电极S相同的平面上。该情况下，电流经路在源极一衬底一漏极上形成，但如图13(A)所示，在背面的金属层(漏极电极D)的膜厚薄的状态下，电阻值增大。
另一方面，图13(B)表示适于倒装片安装的结构，例如是图12所示的现有结构的情况。这样，在芯片的第一主面Sf1侧设置源极电极s及漏极电极D的结构中，如箭头所示，形成从第一主面Sf1侧的源极电极S到达低浓度半导体层LS、高浓度半导体衬底HS、且再次从低浓度半导体层LS到达漏极电极D的电流经路。因此，该情况下，从MOSFET的源极电极S朝漏极电极D的电阻成分成为衬底在垂直方向的电阻Ra、Rc及衬底在水平方向的电阻Rb的合成电阻。因此，在与图13(A)进行比较的情况下，衬底水平方向的电阻Rb也给予器件整体的电阻大幅度的影响。
因此，为降低电阻Rb，而在衬底的第二主面Sf2(背面)设置低电阻的金属板116(参照图12)。它们例如是Cu、Fe、Al或Ag等。
Cu、Fe、Al、Ag其金属板116自身的电阻值低且廉价，故采用之。但是，它们的耐氧化性及耐腐蚀性都低，存在例如长期间保管会使金属板氧化、变色的情况。金属板的变色不仅给予该金属板的电阻值不良影响，而且使组装作业工序中与切割片的密封不良，从而成为切割作业时引起芯片飞散(飛び)等不良的大的主要原因。
发明内容
本发明是鉴于这样的课题而构成的，第一，提供一种半导体装置，其具备：具有第一主面及第二主面的半导体衬底；设于所述半导体衬底上的分立半导体的元件区域；设于所述第一主面侧且分别与所述元件区域连接的第一电极及第二电极；在所述第二主面侧露出且具有耐腐蚀性及耐氧化性的第一金属层；设于所述第一金属层和所述半导体衬底的所述第二主面之间的第二金属层；从所述第一电极通过所述半导体衬底的内部到达所述第二电极的电流经路，将所述第一金属层设为膜厚比所述第二金属层厚的厚膜金属层。
第二，一种半导体装置，其具备：具有第一主面及第二主面的半导体衬底；设于所述半导体衬底上的分立半导体的元件区域；设于所述第一主面侧且分别与所述元件区域连接的第一电极及第二电极；在所述第二主面侧露出且具有耐腐蚀性及耐氧化性的第一金属层；设于所述第一金属层和所述半导体衬底的所述第二主面之间的第二金属层；设于该第二金属层和所述第一金属层之间的第三金属层；从所述第一电极通过所述半导体衬底的内部到达所述第二电极的电流经路，将所述第三金属层设为膜厚比所述第一金属层厚的厚膜金属层。
第三，一种半导体装置，在具有第一主面及第二主面的半导体衬底上设有分立半导体的元件区域，其中，所述元件区域具有将所述半导体衬底的局部设为公共的漏极区域的第一绝缘栅型半导体元件区域及第二绝缘栅型半导体元件区域，具备：设于所述第一主面侧且分别与第一绝缘栅型半导体元件区域及第二绝缘栅型半导体元件区域连接的第一源极电极及第二源极电极；在所述第二主面侧露出的具有耐腐蚀性及耐氧化性的第一金属层；设于所述第一金属层和所述半导体衬底的所述第二主面之间的第二金属层；从所述第一源极电极通过所述半导体衬底的内部到达所述第二源极电极的电流经路，将所述第一金属层设为膜厚比所述第二金属层厚的厚膜金属层。
第四，一种半导体装置，在具有第一主面及第二主面的半导体衬底上设有分立半导体的元件区域，其中，所述元件区域具有将所述半导体衬底的局部设为公共的漏极区域的第一绝缘栅型半导体元件区域及第二绝缘栅型半导体元件区域，具备：设于所述第一主面侧且分别与第一绝缘栅型半导体元件区域及第二绝缘栅型半导体元件区域连接的第一源极电极及第二源极电极；在所述第二主面侧露出的具有耐腐蚀性及耐氧化性的第一金属层；设于所述第一金属层和所述半导体衬底的所述第二主面之间的第二金属层；设于该第二金属层和所述第一金属层之间的第三金属层；从所述第一源极电极通过所述半导体衬底的内部到达所述第二源极电极的电流经路，将所述第三金属层设为膜厚比所述第一金属层厚的厚膜金属层。
根据本发明，第一，在第一主面设置第一电极及第二电极，且形成从第一电极经由衬底到达第二电极的电流经路的半导体装置中，通过在第二主面侧设置厚膜金属层，可降低衬底在水平方向的电阻成分。
第二，通过在第二主面的最表面露出的第一金属层采用耐氧化性及耐腐蚀性高的Au，并将第一金属层设为厚膜金属层，由此，可抑制背面(第二主面)的金属的变色、腐蚀等。特别是在进行倒装片安装时，由于第一金属层暴露于外界气体中，故存在第一金属层的电阻值有变动的问题。
另外，由于金属层的变色，从而也存在在切割时会产生芯片飞散等不良等的作业上的问题。
但是，在本实施例中，可不由保护膜覆盖第一金属层表面，而可抑制变色及腐蚀等。
第三，厚膜金属层的膜厚，在该厚膜金属层的厚度和装置整体的电阻值(接通电阻)的关系的基础上，设为电阻值饱和的下限附近的膜厚。由此，可提供抑制成本且可靠性高的半导体装置。
第四，设于第二主面侧的第三金属层采用铜，将该第三金属层设为厚膜金属层，并采用金作为第二主面的最表面露出的第一金属层，由此可提供进一步抑制成本且可靠性高的半导体装置。
附图说明
图1是说明本发明半导体装置的平面图；
图2是说明本发明半导体装置的剖面图；
图3是说明本发明半导体装置的剖面图；
图4是说明本发明半导体装置的侧面图；
图5是说明本发明半导体装置的侧面图；
图6是说明本发明半导体装置的电路图；
图7是说明本发明半导体装置的平面图；
图8是说明本发明半导体装置的剖面图；
图9是说明本发明半导体装置的侧面图；
图10是说明本发明半导体装置的侧面图；
图11是说明本发明半导体装置的特性图；
图12是说明现有半导体装置的剖面图；
图13A、13B是说明现有半导体装置的剖面图。
符号说明
1n+型硅半导体衬底
2n-型半导体层
4沟道层
7槽
10半导体衬底(半导体芯片)
11栅极绝缘膜
13栅极电极
13c连接部
14体区
15源极区域
16层间绝缘膜
17、17a、17b源极电极
18漏极电极
19p、19pa、19pb栅极焊盘电极
20、20a、20b元件区域
22、22’高浓度杂质区域
23氮化膜
24 UBM
25抗焊料剂
27源极补片电极
28漏极补片电极
29栅极补片电极
31第一金属层
32第二金属层
33第三金属层
40其它金属层
TM厚膜金属层
Sf1第一主面
Sf2第二主面
200开关元件
100、100a、100b  MOSFET
S、S1、S2源极端子(电极)
G、G1、G2栅极端子(电极)
D漏极端子(电极)
具体实施方式
参照图1～图11详细说明本发明实施例。
本发明的半导体装置由半导体衬底、元件区域、第一电极、第二电极、第一金属层及第二金属层构成，是在半导体衬底的第一主面上设置第一电极和第二电极，并形成从第一电极通过半导体衬底的内部到达第二电极的电流经路的装置。
在元件区域形成分立半导体的元件。分立半导体也被称作个别半导体，是单功能的半导体元件的总称。作为之一例，有MOSFET(Metal OxideSemiconductor Field Effect Transistor)、IGBT(Insulated Gate BipolarTransistor)、以接合型FET为代表的场效应型晶体管(FET)、双极晶体管、二极管、晶闸管等。
参照图1～图4，作为第一实施例，对第一金属层是厚膜金属层的情况进行说明。另外，在第一实施例中，以在元件区域形成MOSFET的情况为例进行表示。
图1是表示本实施例的MOSFET100的平面图。该图表示MOSFET100的各电极和外部连接电极。
在半导体衬底1O的表面设置与元件区域20(虚线)连接的源极电极17及漏极电极18、栅极焊盘电极19p。在源极电极17及漏极电极18、栅极焊盘电极19p上分别设置如圆圈所示的成为外部连接电极的源极补片电极27、漏极补片电极28、栅极补片电极29。各补片电极27、28、29的直径例如约为250μm。半导体衬底10作为之一例，是尺寸为1.4mm×1.4mm的半导体芯片，各补片电极27～29的节距为0.5mm～1.0mm程度。
需要说明的是，图1中表示合计四个的补片电极27、28、29，但其数量及配置不限于图示。另外，各补片电极27、28、29的数量也不限于图示。
图2是表示第一实施例的MOSFET100的截面的图，是图1的a-a线的剖面图。半导体衬底10具有第一主面Sf1及第二主面S工，其设置MSFET100的元件区域20。
即，半导体衬底10中，在n+型硅半导体衬底1上设置n-型半导体层(例如n-型外延层)2，构成漏极区域。在成为第一主面Sf1的n-型半导体层2表面设置作为p型杂质区域的沟道层4。
槽7贯通沟道层4到达n-型半导体层2。槽7通常是在第一主面sf1的平面图案上构图为格子状或条纹状。
在槽7的内壁设置栅极氧化膜11。栅极氧化膜1l的膜厚根据MSOFET的驱动电压而设为数百
Figure A20071014177400111
左右。另外，在槽7的内部埋设导电材料，设置栅极电极13。导电材料例如为多晶硅，在该多晶硅上，为实现低电阻化而导入了例如n型杂质。
源极区域15是在与槽7邻接的沟道层4表面注入了n型杂质的n+型杂质区域。另外，在邻接的源极区域15间的沟道层4表面设置p+型杂质的扩散区域即体区14，使衬底的电位稳定化。由此，由邻接的槽7围成的部分成为MOS晶体管的一个晶格，将其汇集多个，构成MOSFET的元件区域20。
需要说明的是，在本实施例中，为了便于说明，最外周的MOS晶体管的晶格配置区域都作为元件区域20进行说明。在元件区域20的外周设置高浓度的p型杂质区域即保护环21。
栅极电极13由层间绝缘膜16覆盖，源极电极l7是通过喷溅铝(Al)等而构图为所希望的形状的金属电极。源极电极17覆盖在元件区域20上，设于半导体衬底10的第一主面Sf1侧，经由层间绝缘膜16间的接触孔与源极区域15及体区14连接。
栅极电极13通过连接部13c引出到衬底上，并延伸到包围半导体衬底周围的栅极连接电极l9处，与栅极焊盘电极(这里未图示)连接。
源极电极17上设置氮化膜23，将氮化膜23的规定区域开口，设置UBM(Under Bump Metal)24。UBM24是例如通过无电解镀敷按顺序从下层层叠镍(Ni：厚度2.4μm)、金(Au：厚度
Figure A20071014177400121
)的金属层。另外，在氮化膜23上设置UBM24露出的抗焊料剂25，通过进行以UBM24为底层电极的网板印刷设置源极补片电极27。源极补片电极27的直径约为250μm。需要说明的是，图2中为了便于说明，表示了将源极电极17配置在元件区域20端部的情况，但实际上按照在元件区域20上均匀地施加源极电位的方式配置。
如图2所示，漏极电极18设于半导体衬底10的第一主面Sf1侧。漏极电极18通过与源极电极17相同(例如Al)的金属层构图为所希望的形状，与源极电极17分开配置。在漏极电极18上，也与源极补片电极27相同，设置漏极补片电极28。
在漏极电极18的下方，为降低漏极电阻，而设置n型高浓度杂质区域(n+型杂质区域)22、及浓度比n+型杂质区域22高的n+型杂质区域22’。N+型杂质区域22从n-型半导体层2表面到达n+型硅半导体衬底1上。即，漏极电极18经由n+型杂质区域22与元件区域20的漏极区域(n-型半导体层2及n+型硅半导体衬底1)连接。
这样，在本实施例中，将源极电极17及漏极电极18都设置在第一主面Sfl侧。由此，在MOSFET1000动作时，形成从与输入端子连接的源极补片电极27及源极电极17起，经由元件区域20、n-型半导体层2、n+型硅半导体衬底1、n+型杂质区域22(22’)到达与输出端子连接的漏极电极18、漏极补片电极28的电流经路。
图3也表示第一实施例的MSOFET100的剖面的图，是图1的b-b线剖面图。
栅极补片电极19p设于保护二极管Di上，与其一端连接。保护二极管Di的另一端与源极电极17连接。栅极补片电极19p如图2所示，经由栅极连接电极19及连接部13c与栅极电极13连接。在栅极补片电极19p上，与源极补片电极27相同，也设置栅极补片电极29，由此，在栅极电极13上施加栅极电压。
参照图2及图3，在半导体衬底10的第二主面Sf2侧，使具有耐腐蚀性及耐氧化性的第一金属层31在整个面上露出。另外，在第一金属层31和半导体衬底10之间设置第二金属层32。
第一金属层3l是具有耐腐蚀性及耐氧化性的金属层，例如是金(Au)。另外，第一金属层31是膜厚比第二金属层32厚的厚膜金属层Tm。厚膜金属层TM的厚度W在厚膜金属层TM的厚度W和上述电流经路中电阻值的相关关系上是电阻值饱和的下限附近的膜厚。该相关关系后述，作为之一例，在本实施例中，厚膜金属层TM的厚度采用
Figure A20071014177400131
在厚膜金属层31的表面没有设置任何保护膜，厚膜金属层31在半导体衬底10的第二主面Sf2侧露出。
第二金属层32设于第二主面Sf2表面，是提高与硅的粘接性的金属层(例如钛(Ti))。该情况下的第二金属层32的膜厚例如为
Figure A20071014177400132
在第一金属层31(厚膜金属层TM)和第二金属层32之间也可以设置图2及图3中其它的金属层(例如镍(Ni))40。即，第二主面Sf2侧的多层金属结构从半导体衬底10侧起，是Ti-Ni-Au，其它金属层(Ni)40的膜厚例如为
Figure A20071014177400133
另外，图示省略，作为其它金属层40，还可以设置铜(Cu)，第二主面Sf2侧的底层金属结构从半导体衬底10侧起，为Ti
Figure A20071014177400134
这样，第一实施例的第二主面Sf2侧的金属层结构为至少含有第二金属层32和第一金属层31(厚膜金属层TM)的多层金属结构，它们在各补片电极形成之前通过金属蒸镀设于第二主面Sf2上。
图4中，作为上述半导体衬底(半导体芯片)1O的安装例，表示在印刷线路板等上倒装片安装的侧面图。需要说明的是，半导体衬底10的元件区域20等的图示省略。
在设有规定的导电图案52的印刷线路板51上，面朝下配置半导体芯片10，进行源极补片电极27、漏极补片电极28、栅极补片电极(这里未图示)和对应的导电图案52的对位，使用采用热的焊锡回流或加压状态下的超声波震动进行焊接、连接。
如上所述，在本实施例中，与输入端子连接的源极电极(源极补片电极27)、和与输出端子连接的漏极电极(漏极补片电极28)设于第一面Sf1侧。因此，在MOSFET100动作时，如图4中箭头所示，形成主要从源极电极(源极补片电极27)通过半导体衬底10到达漏极电极(漏极补片电极28)的电流经路。而且，该电路经路中的电阻为半导体衬底的垂直方向的电阻Ra、Rc和水平方向的电阻Rb(参照图13(B))。
即，在本实施例的结构中，由于衬底水平方向的电阻成分即电阻Rb产生，故优选尽可能地减小该电阻Rb。因此，在第二主面Sf2侧配置厚度
Figure A20071014177400141
的厚膜金属层TM。由于厚膜金属层TM采用金(Au)，其电阻值低且其厚度厚，故可减小衬底水平方向的电阻Rb。
另外，Au与例如银(Ag)或铜(Cu)相比，其耐腐蚀性及耐氧化性高。因此，由于在第二主面Sf2的最表面露出的第一金属层31采用Au，从而即使在半导体芯片(或晶片的状态下)长期间保存的情况下，也能够大幅度抑制厚膜金属层TM的变色、腐蚀等不良的产生。
例如当在晶片状态下第一金属层31变色时，组装作业工序中与切割片的密封不良，在切割时成为引起芯片飞溅等故障的大的主要原因。
另外，若即使在切割后，厚膜金属层TM即第一金属层31自身的电阻值因变色等而增加，则存在不能充分实现衬底水平方向的电阻降低的问题。但是，在本实施例中，由于第二主面Sf2的成为最表面的第一金属层31(厚膜金属层TM)采用耐腐蚀性及耐氧化性高的Au，从而也不需要追加设置用于对其进行保护的保护膜等，可得到高的可靠性。
图5是表示本发明第二实施例的图，与图4相同，作为半导体衬底(半导体芯片)10的实施例，表示在印刷线路板等上倒装片安装的侧面图。第二实施例中，第二主面Sf2侧的多层金属层的结构是不同的，设于半导体衬底10上的元件区域20或源极电极17、漏极电极18等由于与图1～图3相同，故详细的说明及图示省略。另外，与图4相同的构成要素使用同一符号。
第二实施例中，第二主面Sf2侧的金属层结构由至少含有第一金属层31、第二金属层32、第三金属层33的多层金属结构构成。
第一金属层31设于第二主面Sf2的最表面，是具有耐腐蚀性及耐氧化性的金属层(例如Au)。第一金属层31的膜厚例如为
Figure A20071014177400151
另外，在半导体衬底10的第二主面Sf2表面设置提高粘接性的第二金属层32(例如Ti：厚度
Figure A20071014177400152
)。
第三金属层33设于第二金属层32和第一金属层31之间，是电阻值低且廉价的金属层，例如是Cu。另外，在第二实施例中，第三金属层33是厚膜金属层Tm。第三金属层33的厚度例如为
Figure A20071014177400153
另外，如图5所示，第三金属层33和第二金属层32之间也可以设置其它金属层(例如Ni：厚度
Figure A20071014177400154
)40。
即，第二主面Sf2侧的多层金属结构从半导体衬底10侧起，为Ti-Ni-Cu-Au。
在第二实施例中，设置第三金属层33作为厚膜金属层TM，其采用Cu。另外，在第二主面Sf2的最表面设置第一金属层31，其采用Au。由此，可降低衬底水平方向的电阻Rb，且可大幅度降低第二主面Sf2最表面的变色、腐蚀等不良的产生。
即使减薄成为第二主面Sf2的最表面的第一金属层31(Au)的膜厚，也可以利用厚膜金属层TM(第三金属层33)降低接通电阻，因此，与第一实施例相比较，可避免成本增加。
另外，第一金属层31的Au的溶点为1063℃。即，第二金属层32采用Ti(溶点：1668℃)，在第二实施例中，若第三金属层33采用Cu(溶点：1083℃)，则第一及第二实施例中，第二主面Sf2侧的多层金属层的溶点都为二1000℃以上。
例如图4、图5所示，在倒装片安装时，在安装的最表面(第一金属层31表面)激光印刷(标记)制品名、制造年月等。在本实施例中，第二主面Sf2侧全部是溶点为1000℃以上的金属层，因此，也可以提高相对于高温的激光印刷的耐性。由此，由于可将厚膜金属层TM(第一金属层31或第三金属层33)的消失设定在最小限，故可防止接通电阻的变动或从消失部分侵入水分。
需要说明的是，在本实施例中，作为半导体衬底(半导体芯片)10的安装例，以倒装片安装为例进行了说明。但是，本实施例中，在分立半导体中，在第一主面Sf1侧配置电路经路上的两个电极的情况下，可降低装置的电阻。因此，不限于上述例，即使是采用COB(Chip on Board)技术的安装，也可以同样实施。
采用COB技术的安装是将第二主面S2侧固定在印刷线路板等基板上，通过引线焊接等将第一主面S1侧的电极与基板上的导电图案连接，第二主面S2和基板的固定采用导电性或绝缘性粘接材料。
特别是在采用绝缘性粘接剂时，进一步降低半导体衬底1内的电阻的要求提高，但通过本实施例，可有效地降低装置的电阻。
其次，参照图6～图9对本发明第三实施例进行说明。需要说明的是，与第一实施例相同的构成要素使用同一符号，重复的部分省略其说明。
作为设于半导体衬底(半导体芯片)10上的元件区域20，若为分立(单功能)半导体，则其数量也可以为多个。第二实施例中，以将第一MOSFET100a及第二MOSFET100b这两个元件区域20a、20b公用漏极，集成化在一个半导体衬底(半导体芯片)10上的情况为例进行说明。
作为开关用途的半导体装置，已知不仅进行开关的切换，而且例如用于二次电池(LIB：Lithium Ion Battery)的保护电路的MOSFET，也可以进行电流经路的方向(电流流过的方向)的切换。
图6是表示由MOSFET构成可切换双方向电流经路的半导体装置(开关元件)的情况之一例的电路图。
开关元件200将分别由多个MOS晶体管构成的第一MOSFET100a及第二MOSFET100b分别用公共的漏极D串联连接。而且，在各栅极端子G1、G2上施加栅极信号，控制两MOSFET，根据施加在第一源极端子S1、第二源极端子S2上的电位差切换电流经路。
第一MOSFET100a及第二MOSFET100b分别具有寄生二极管。例如利用控制信号将第一MOSFET100a关闭，将第二MOSFET100b接通。而且，通过将第一源极端子S1设为比第二源极端子S2高的电位，利用第一MOSFET100a的寄生二极管和第二MOSFET100b形成d1方向的电流经路。
另外，利用控制信号将第一MOSFET100a接通，将第二MOSFET100关闭。而且，通过将第一源极端子S1设为比第二源极端子S2设为低的电位，利用第一MOSFET100a和第二MOSFET100b的寄生二极管形成d2方向的电流经路。
进而通过将栅极端子G1和栅极端子G2同时接通，不经由寄生二极管而形成电流经路。
图7是表示上述的开关元件200的平面图，表示开关元件200的各电极和外部连接电极。
在同一半导体衬底10上设置第一元件区域20a和第二元件区域20b。第一元件区域20a是第一MOSFET100a的元件区域，第二元件区域20b是第二MOSFET100b的元件区域。
第一MOSFET100a、第二MOSFET10b相对于芯片的中心线X-X例如线对称地配置，其上分别设置第一源极电极17a、第二源极电极17b、第一栅极补片电极19pa、第二栅极补片电极19pb。
第一MOSFET100a的源极区域(未图示)与覆盖在第一区域20a上的第一源极电极17a连接。在第一源极电极17a上设置第一源极补片电极27a。第一MOSFET100a的栅极电极(未图示)在半导体衬底10的周边部延伸，与第一栅极补片电极19pa连接。第二MOSFET100b也同样。
图8是图7的c-c线剖面图。
第一MOSFET100a、第二MOSFET100b设于具有第一主面Sf1和第二主面Sf2的同一半导体衬底10上。即，在半导体衬底10的第一元件区域20a设置第一MOSFET100a，在第二元件区域20b设置第二MOSFET100b。由此，第一MOSFET100a及第二MOSFET100b的漏极区域是公共的。
构成各元件区域20a、20b的MOS晶体管与第一实施例的相同，因此省略说明，但在第二实施例中，漏极端子未导出到外部，也可以不设置漏极电极。
即，在第一主面Sf1侧只是设置第一源极电极17a、第一栅极焊盘电极19pa、第二源极电极17b、第二栅极焊盘电极19pb。另外，设置与它们分别连接的第一源极补片电极27a、第一栅极补片电极29b、及第二源极补片电极27b、第二栅极补片电极29b(参照图7)。这些电极部分的详细的结构与第一实施例相同。另外，第一MOSFET100a及第二MOSFET100b的结构相同。
这样，在第二实施例中，第一源极电极17a及第二源极电极17b都成为设于半导体衬底10的第一主面Sf1侧的第一电极及第二电极，在其间形成电流经路。
具体而言，利用施加在第一栅极焊盘电极19pa及第二栅极焊盘电极19pb上的控制信号，例如将第一MOSFET100a关闭，将第二MOSFET100b接通。此时，通过将第一源极电极17a的电位设为比第二源极电极17b的电位高，沿图中d1方向形成电流经路。另一方面，利用控制信号将第一MOSFET100a接通，将第二MOSFETl00b关闭，若第一源极电极17a的电位比第二源极电极17b的电位低，则在d1方向的反方向的d2方向形成电流经路。另外，将第一MOSFET100a及第二MOSFET100b都接通，利用第一源极电极17a和第二源极电极17b的电位差，不经由寄生二极管即可沿d1方向或d2方向形成电流经路。
即，在第二实施例中，电流经路从第一MOSFET100a的第一源极电极17a经由半导体衬底10形成至第二MOSFET100b的第二源极电极17b(或其反方向)。
在第三实施例中，在上述半导体衬底10的第二主面Sf2侧，配置厚膜金属层TM作为第一金属层3l。即，在半导体衬底10的第二主面Sf2上设置用于提高粘接性的第二金属层32(例如Ti：
Figure A20071014177400181
)，并设置在第二主面Sf2侧露出的第一金属层31(厚膜金属层TM)。需要说明的是，如图8所示，在第一金属层31和第二金属层32之间也可以设置其它金属层40(例如Ni：
Figure A20071014177400182
)。
另外，图中未图示，还可以设置铜(Cu)作为其它金属层40，第二主面Sf2侧的多层金属结构从半导体衬底10侧起，为
Figure A20071014177400183
Figure A20071014177400184
厚膜金属层TM例如为Au，由于其电阻值低且其厚度厚，故可减小衬底水平方向的电阻Rb。
另外，Au其耐腐蚀性及耐氧化性高，可大幅抑制厚膜金属层TM的变色，腐蚀等不良的产生。
图9是表示上述半导体衬底(半导体芯片)10的安装例的侧面图。在印刷线路板51等上设置导电图案52，并倒装片安装半导体芯片10。
即，将第一源极补片电极27a、第一栅极补片电极29a、第二源极补片电极27b、第二栅极补片电极29b与对应的导电图案52连接。
设于第二主面Sf2侧的厚膜金属层TM的厚度具有第一MOSFET100a及第二MOSFET100b的接通电阻相关的关系(后述)。另外，其相关关系中，存在接通电阻降低饱和的厚膜金属层TM的厚度W。因此，通过将厚膜金属层TM的厚度W设为接通电阻的降低饱和的下限附近的厚度，可抑制成本的增加。
例如，在第三实施例中，在芯片尺寸为1.8mmx1.8mm时，厚膜金属层TM的膜厚W为
Figure A20071014177400191
在此，在第一及第二实施例中，表示了为实现倒装片安装或采用COB技术的安装，而将第一电极和第二电极配置于同一第一主面Sf1侧的情况。
另一方面，在第三实施例中，漏极电极为不导出到外部，而将电流经路上的第一电极(第一源极电极17a)及第二电极(第二源极电极l7b)设于第一主面Sf1侧的结构(参照图8)。即，第三实施例的结构不限于安装方法。例如，图中省略，而也采用在引线架上固定半导体芯片10的第二主面Sf2侧，将引线架和半导体芯片10由树脂层覆盖的一般的模制封装的安装方法等。
但是，在本实施例中，由于设于半导体衬底10的第二主面Sf2上的厚膜金属层TM，从而在第三实施例中，也可以降低半导体装置的接通电阻。
参照图10说明第四实施例。第四实施例是在第三实施例的基础上设置第三金属层33的情况。元件区域20a、20b由于与第三实施例相同，故图示及说明省略。另外，与图9相同的构成要素使用同一符号。
在第四实施例中，在半导体衬底10的第二主面Sf2侧设置第一金属层31、第二金属层32，且配置厚膜金属层TM作为第三金属层33。即，在半导体衬底10的第二主面Sf2上设置用于提高粘接性的第二金属层32(例如Ti：
Figure A20071014177400192
)，且设置在第二主面Sf2侧露出的第一金属层31。而且，将第三金属层33配置于第二金属层32及第一金属层31之间，将其设为厚膜金属层TM。需要说明的是，也可以在第二金属层32和第三金属层33之间设置其它金属层40(例如Ni：
Figure A20071014177400193
)。
厚膜金属层TM例如为Cu，由于其电阻值低且其厚度厚，故可减小基准水平方向的电阻Rb。
厚膜金属层TM的厚度具有与第一MOSFET100a及第二MOSFET100b的接通电阻相关的关系(后述)。另外，其相关关系中，存在接通电阻降低饱和的厚膜金属层TM的厚度W。因此，通过将厚膜金属层TM的厚度W设为接通电阻的降低饱和的下限附近的厚度，可抑制成本的增加。
另外，在第二主面Sf2的最表面设置第一金属层31，其采用Au。由此，可降低衬底水平方向的电阻Rb，且可大幅抑制第二主面Sf2最表面的变色、腐蚀等不良的产生。
另外，即使将第二主面s位的成为最表面的第一金属层31(Au)的膜厚减薄，也可以利用厚膜金属层TM(第三金属层33)降低接通电阻，因此，与第三实施例相比，可避免成本增加。
其次，参照图11说明厚膜金属层TM的厚度和装置的电阻的关系。图11表示厚膜金属层TM的厚度w和第三实施例的MOSFET的接通电阻(RSSON)的关系。横轴是实际的半导体衬底(半导体芯片)10的第二主面Sf2侧设置的厚膜金属层TM的厚度W(
Figure A20071014177400201
)，将第一金属层31(Au)设为厚膜金属层TM的情况。另外，纵轴是栅极电压Vc＝4V时的接通电阻RSSON(Ω)。半导体芯片10的尺寸为1.8mm×1.8mm。
上述电流经路中产生的电阻Ra、Rb、Rc给予MOSFET的接通电阻RSSON直接的影响。即，在电阻Ra、Rb、Rc大时，MOSFET的接通电阻也变大。
因此，通过在半导体芯片10的成为背面的第二主面Sf2侧设置电阻值低的厚膜金属层TM(Au)，可降低MOSFET的接通电阻。
但是，如图11所示，当厚膜金属层TM(Au)的厚度超过某一定值时，可知接通电阻的降低成为饱和状态。这是由于，通过加厚厚膜金属层TM，可减小衬底(芯片)在水平方向的电阻Rb，但作为MOSFET的接通电阻，衬底垂直方向的电阻Ra、Rb依然存在，而没有变化。
即，若为上述的芯片尺寸，则厚膜金属层TM(Au)的膜厚为
Figure A20071014177400202
程度，是充分的。若接通电阻的降低不再继续，则不需要将厚膜金属层TM设为其以上厚度，若厚膜金属层TM过厚，反而会产生问题。
例如，不需要厚的厚膜金属层TM当然会导致成本的增加，特别是在厚膜金属层TM采用Au时，会阻碍成本降低。
另外，若厚膜金属层31过厚(例如2μm以上)，则也会存在翘曲产生或组装工序中进行切割作业时刀片容易较早地磨损等问题。
因此，在本实施例中，在该厚膜金属层TM的厚度和电流经路中电阻值(这里为MOSFET的接通电阻)的相关关系上，将厚膜金属层TM的厚度设为电阻值饱和的下限附近的膜厚。
由此，可以以低的成本降低半导体装置的电阻值，进而可提供使耐腐蚀性、耐氧化性提高的可靠性高的半导体装置。
需要说明的是，在图11中，显示了有关一个芯片尺寸的特性，但即使是其它芯片尺寸，也可以得到相同的倾向。即，有电阻值饱和的饱和点因芯片尺寸而变动的可能性，但接通电阻和厚膜金属层TM的厚度W的关系下的饱和点存在。
即，本实施例的厚膜金属层TM的厚度W不限于上述值，就厚膜金属层TM的厚度W和电流经路中电阻值的相关关系而言，采用饱和点下限附近的膜厚。由此，可抑制成本的增加。

Claims (11)

1.一种半导体装置，其特征在于，具备：
具有第一主面及第二主面的半导体衬底；
设于所述半导体衬底上的分立半导体的元件区域；
设于所述第一主面侧且分别与所述元件区域连接的第一电极及第二电极；
在所述第二主面侧露出且具有耐腐蚀性及耐氧化性的第一金属层；
设于所述第一金属层和所述半导体衬底的所述第二主面之间的第二金属层；
从所述第一电极通过所述半导体衬底的内部到达所述第二电极的电流经路，
所述第一金属层为膜厚比所述第二金属层厚的厚膜金属层。
2.一种半导体装置，其特征在于，具备：
具有第一主面及第二主面的半导体衬底；
设于所述半导体衬底上的分立半导体的元件区域；
设于所述第一主面侧且分别与所述元件区域连接的第一电极及第二电极；
在所述第二主面侧露出且具有耐腐蚀性及耐氧化性的第一金属层；
设于所述第一金属层和所述半导体衬底的所述第二主面之间的第二金属层；
设于该第二金属层和所述第一金属层之间的第三金属层；
从所述第一电极通过所述半导体衬底的内部到达所述第二电极的电流经路，
所述第三金属层为膜厚比所述第一金属层厚的厚膜金属层。
3.如权利要求1或2所述的半导体装置，其特征在于，所述第一金属层是金。
4.如权利要求2所述的半导体装置，其特征在于，所述第三金属层是铜。
5.如权利要求1或2所述的半导体装置，其特征在于，所述厚膜金属层的厚度，在该厚膜金属层的厚度和所述电流经路的电阻值的相关关系的基础上，设为所述电阻值饱和的下限附近的膜厚。
6.如权利要求5所述的半导体装置，其特征在于，所述厚膜金属层的膜厚为5000～20000。
7.如权利要求1或2所述的半导体装置，其特征在于，在所述元件区域设置场效应晶体管、双极晶体管、二极管中之一。
8.一种半导体装置，在具有第一主面及第二主面的半导体衬底上设有分立半导体的元件区域，其特征在于，
所述元件区域具有将所述半导体衬底的局部设为公共的漏极区域的第一绝缘栅型半导体元件区域及第二绝缘栅型半导体元件区域，
具备：设于所述第一主面侧且分别与第一绝缘栅型半导体元件区域及第二绝缘栅型半导体元件区域连接的第一源极电极及第二源极电极；
在所述第二主面侧露出的具有耐腐蚀性及耐氧化性的第一金属层；
设于所述第一金属层和所述半导体衬底的所述第二主面之间的第二金属层；
从所述第一源极电极通过所述半导体衬底的内部到达所述第二源极电极的电流经路，
所述第一金属层为膜厚比所述第二金属层厚的厚膜金属层。
9.一种半导体装置，在具有第一主面及第二主面的半导体衬底上设有分立半导体的元件区域，其特征在于，
所述元件区域具有将所述半导体衬底的局部设为公共的漏极区域的第一绝缘栅型半导体元件区域及第二绝缘栅型半导体元件区域，
具备：设于所述第一主面侧且分别与第一绝缘栅型半导体元件区域及第二绝缘栅型半导体元件区域连接的第一源极电极及第二源极电极；
在所述第二主面侧露出的具有耐腐蚀性及耐氧化性的第一金属层；
设于所述第一金属层和所述半导体衬底的所述第二主面之间的第二金属层；
设于该第二金属层和所述第一金属层之间的第三金属层；
从所述第一源极电极通过所述半导体衬底的内部到达所述第二源极电极的电流经路，
所述第三金属层为膜厚比所述第一金属层厚的厚膜金属层。
10.如权利要求8或9所述的半导体装置，其特征在于，所述第一金属层是金。
11.如权利要求9所述的半导体装置，其特征在于，所述第三金属层是铜。
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US7772704B2 (en) 2010-08-10
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