JP6847887B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP6847887B2 JP6847887B2 JP2018055792A JP2018055792A JP6847887B2 JP 6847887 B2 JP6847887 B2 JP 6847887B2 JP 2018055792 A JP2018055792 A JP 2018055792A JP 2018055792 A JP2018055792 A JP 2018055792A JP 6847887 B2 JP6847887 B2 JP 6847887B2
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- 239000004065 semiconductor Substances 0.000 title claims description 231
- 239000012535 impurity Substances 0.000 claims description 69
- 230000002457 bidirectional effect Effects 0.000 description 29
- 230000000052 comparative effect Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 7
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 5
- 229910052698 phosphorus Inorganic materials 0.000 description 5
- 239000011574 phosphorus Substances 0.000 description 5
- 229910052785 arsenic Inorganic materials 0.000 description 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 238000001004 secondary ion mass spectrometry Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052787 antimony Inorganic materials 0.000 description 2
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
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Description
第1の実施形態の半導体装置は、第1の面と第2の面を有する半導体層と、第1のゲート電極と、第2のゲート電極と、半導体層の中に設けられた第1導電型の第1の半導体領域と、半導体層の中に設けられ、第1の半導体領域と第1の面との間に位置し、第1の半導体領域の第1導電型不純物濃度よりも第1導電型不純物濃度が低い第1導電型の第2の半導体領域と、半導体層の中に設けられ、第2の半導体領域と第1の面との間に位置する第2導電型の第3の半導体領域と、半導体層の中に設けられ、第2の半導体領域と第1の面との間に位置し、第3の半導体領域と分離された第2導電型の第4の半導体領域と、半導体層の中に設けられ、第3の半導体領域と第1の面の間に位置する第1導電型の第5の半導体領域と、半導体層の中に設けられ、第4の半導体領域と第1の面の間に位置する第1導電型の第6の半導体領域と、第1のゲート電極と第3の半導体領域との間に設けられた第1のゲート絶縁膜と、第2のゲート電極と第4の半導体領域との間に設けられた第2のゲート絶縁膜と、半導体層の中の第3の半導体領域と第4の半導体領域との間に設けられ、第1の半導体領域と第1の面との間に位置し、第2の半導体領域の第1導電型不純物濃度よりも第1導電型不純物濃度が高く、第1の半導体領域に第1導電型の第7の半導体領域と、を備える。
ドレイン領域30(第1の半導体領域)、ドリフト領域32(第2の半導体領域)、第1のベース領域34a(第3の半導体領域)、第2のベース領域34b(第4の半導体領域)、第1のソース領域36a(第5の半導体領域)、第2のソース領域36b(第6の半導体領域)、低抵抗領域(第7の半導体領域)40が設けられる。
第2の実施形態の半導体装置は、第1の位置における第7の半導体領域と第1の面との距離が、第1の位置よりも第3の半導体領域に近い第2の位置の第7の半導体領域と第1の面との距離よりも小さく、かつ、第1の位置よりも第4の半導体領域に近い第3の位置の第7の半導体領域と第1の面との距離よりも小さい点で、第1の実施形態と異なっている。以下、第1の実施形態と重複する内容については、一部記述を省略する。
26a 第1のゲート電極
26b 第2のゲート電極
28a 第1のゲート絶縁膜
28b 第2のゲート絶縁膜
30 ドレイン領域(第1の半導体領域)
32 ドリフト領域(第2の半導体領域)
34a 第1のベース領域(第3の半導体領域)
34b 第2のベース領域(第4の半導体領域)
36a 第1のソース領域(第5の半導体領域)
36b 第2のソース領域(第6の半導体領域)
40 低抵抗領域(第7の半導体領域)
100 双方向スイッチングデバイス(半導体装置)
101 第1のトランジスタ領域
102 第2のトランジスタ領域
111 第1のソース電極
112 第2のソース電極
120 ドレイン電極
121 第1のゲート電極パッド
122 第2のゲート電極パッド
200 双方向スイッチングデバイス(半導体装置)
C 第1の位置
E1 第2の位置
E2 第3の位置
P1 第1の面
P2 第2の面
Claims (8)
- 第1の面と第2の面を有する半導体層と、
前記半導体層の中に設けられた第1導電型の第1の半導体領域と、
前記半導体層の中に設けられ、前記第1の半導体領域と前記第1の面との間に位置し、前記第1の半導体領域の第1導電型不純物濃度よりも第1導電型不純物濃度が低い第1導電型の第2の半導体領域と、
前記半導体層の中に設けられ、前記第2の半導体領域と前記第1の面との間に位置する第2導電型の第3の半導体領域と、
前記半導体層の中に設けられ、前記第2の半導体領域と前記第1の面との間に位置し、前記第3の半導体領域と分離された第2導電型の第4の半導体領域と、
前記半導体層の中に設けられ、前記第3の半導体領域と前記第1の面の間に位置する第1導電型の第5の半導体領域と、
前記半導体層の中に設けられ、前記第4の半導体領域と前記第1の面の間に位置する第1導電型の第6の半導体領域と、
前記半導体層の中に設けられ、前記第3の半導体領域と前記第4の半導体領域との間の前記第1の面と前記第1の半導体領域との間に位置し、前記第2の半導体領域の第1導電型不純物濃度よりも第1導電型不純物濃度が高く、前記第1の半導体領域に接する第1導電型の第7の半導体領域と、
第1のゲート電極と、
第2のゲート電極と、
前記第2の半導体領域、前記第3の半導体領域及び前記第5の半導体領域と、前記第1のゲート電極との間に設けられた第1のゲート絶縁膜と、
前記第2の半導体領域、前記第4の半導体領域及び前記第6の半導体領域と、前記第2のゲート電極との間に設けられた第2のゲート絶縁膜と、
を備え、
前記第1の面に対し垂直な断面における前記第3の半導体領域から前記第4の半導体領域を結ぶ方向の前記第7の半導体領域の幅が、前記第1の面に対し垂直な断面における前記第3の半導体領域と前記第4の半導体領域の間隔よりも広く、
前記第7の半導体領域の前記幅が、前記第1の面に対し垂直な断面における前記第1のゲート電極と前記第2のゲート電極との間隔よりも狭い、半導体装置。 - 前記第7の半導体領域と前記第3の半導体領域との間、及び、前記第7の半導体領域と前記第4の半導体領域との間に、前記第2の半導体領域が存在する請求項1記載の半導体装置。
- 第1の面と第2の面を有する半導体層と、
前記半導体層の中に設けられた第1導電型の第1の半導体領域と、
前記半導体層の中に設けられ、前記第1の半導体領域と前記第1の面との間に位置し、前記第1の半導体領域の第1導電型不純物濃度よりも第1導電型不純物濃度が低い第1導電型の第2の半導体領域と、
前記半導体層の中に設けられ、前記第2の半導体領域と前記第1の面との間に位置する第2導電型の第3の半導体領域と、
前記半導体層の中に設けられ、前記第2の半導体領域と前記第1の面との間に位置し、前記第3の半導体領域と分離された第2導電型の第4の半導体領域と、
前記半導体層の中に設けられ、前記第3の半導体領域と前記第1の面の間に位置する第1導電型の第5の半導体領域と、
前記半導体層の中に設けられ、前記第4の半導体領域と前記第1の面の間に位置する第1導電型の第6の半導体領域と、
前記半導体層の中に設けられ、前記第3の半導体領域と前記第4の半導体領域との間の前記第1の面と前記第1の半導体領域との間に位置し、前記第2の半導体領域の第1導電型不純物濃度よりも第1導電型不純物濃度が高く、前記第1の半導体領域に接する第1導電型の第7の半導体領域と、
第1のゲート電極と、
第2のゲート電極と、
前記第2の半導体領域、前記第3の半導体領域及び前記第5の半導体領域と、前記第1のゲート電極との間に設けられた第1のゲート絶縁膜と、
前記第2の半導体領域、前記第4の半導体領域及び前記第6の半導体領域と、前記第2のゲート電極との間に設けられた第2のゲート絶縁膜と、
を備え、
前記第1の面に対し垂直な断面の第1の位置における前記第7の半導体領域と前記第1の面との距離が、前記第1の位置よりも前記第3の半導体領域に近い第2の位置の前記第7の半導体領域と前記第1の面との距離よりも小さく、かつ、前記第1の位置よりも前記第4の半導体領域に近い第3の位置の前記第7の半導体領域と前記第1の面との距離よりも小さい、半導体装置。 - 前記第7の半導体領域と前記第1の面との間に、前記第2の半導体領域が存在する請求項1ないし請求項3いずれか一項記載の半導体装置。
- 前記第1の面に対し垂直な断面における前記第3の半導体領域から前記第4の半導体領域を結ぶ方向の前記第7の半導体領域の幅が、前記第1の面に対し垂直な断面における前記第3の半導体領域と前記第4の半導体領域の間隔よりも広い請求項3又は請求項4記載の半導体装置。
- 前記第7の半導体領域の前記幅が、前記第1の面に対し垂直な断面における前記第1のゲート電極と前記第2のゲート電極との間隔よりも狭い請求項5記載の半導体装置。
- 前記第1のゲート電極に電気的に接続された第1のゲート電極パッドと、
前記第2のゲート電極に電気的に接続された第2のゲート電極パッドと、
を更に備える請求項1ないし請求項6いずれか一項記載の半導体装置。 - 前記半導体層の前記第1の面の側に前記第5の半導体領域に接して設けられた第1のソース電極と、
前記半導体層の前記第1の面の側に前記第6の半導体領域に接して設けられた第2のソース電極と、
前記半導体層の前記第2の面に接して設けられたドレイン電極と、
を更に備える請求項1ないし請求項7いずれか一項記載の半導体装置。
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