CN101133498B - 使用高介电常数电介质层的量子阱晶体管 - Google Patents
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Abstract
可以利用置换金属栅极法来形成量子阱晶体管或高电子迁移率晶体管。可以利用虚拟栅极来定义侧壁间隔物和源漏接触金属。可以移除虚拟栅极,并利用剩余结构作为掩模来蚀刻掺杂层以形成与所述开口自对准的源极和漏极。高介电常数材料可以涂覆所述开口的侧面,然后可以沉积金属栅极。结果,源极和漏极得以与金属栅极自对准。此外,金属栅极通过该高介电常数材料而与下面的阻挡层隔离。
Description
技术领域
一般来说,本发明涉及量子阱晶体管的形成。
背景技术
量子阱是将粒子限制在一个维度内以迫使它们占用平面区域的势阱。将第一材料夹在两个能带隙大于第一材料的材料层之间可以形成量子阱。量子阱或高电子迁移率晶体管(HEMT)是利用两种具有不同能带隙的材料之间的结作为沟道的场效应晶体管。该结可以展现出非常低的电阻或非常高的电子迁移率。施加在栅极上的电压可以改变该结的电导率。
量子阱晶体管易于具有高栅极漏电和寄生串联电阻。具体来说,利用周期表中的III-V族元素的量子阱晶体管易于存在这些问题。这些材料的实例包括砷化铟镓/砷化铟铝和锑化铟/锑化铝铟。
在现有量子阱晶体管的技术水平下,可以在阻挡层上沉积直接肖特基金属栅极以形成易于具有高栅极漏电的肖特基结。也可以将源极和漏极区域图案化,并在将栅极图案化之前完成源极和漏极接触金属。栅极图案化是在工艺的最后一步完成的,这会导致非自对准的源漏区域。这些非自对准的源漏区域易于具有寄生串联电阻。具有寄生串联电阻的器件会展现出较差的性能。
因此,需要用更好的方法来制造量子阱晶体管。
附图说明
图1是本发明的一个实施例的放大横截面图;
图2是根据本发明的一个实施例的处于制造前期的如图1所示的实施例的放大横截面图;
图3是根据本发明的一个实施例的在随后处理之后的如图2所示的实施例的放大横截面图;
图4是根据本发明的一个实施例的在随后处理之后的对应于图3的放大横截面图;
图5是根据本发明的一个实施例的在随后处理之后的对应于图4的放大横截面图;
图6是根据本发明的一个实施例的在随后处理之后的对应于图5的放大横截面图;
图7是根据本发明的一个实施例的在随后处理之后的对应于图6的放大横截面图;
图8是根据本发明的另一个实施例的在随后处理之后的对应于图7的放大横截面图;
图9是根据本发明的耗尽型实施例的在随后处理之后的对应于图8的放大横截面图;以及
图10是根据本发明的增强型实施例的在随后处理之后的对应于图7的放大横截面图。
具体实施方式
参照图1和图10,耗尽型(图1)或增强型(图10)自对准源漏量子阱晶体管可以形成有高介电常数电介质层24和充当肖特基栅极金属的金属栅电极38。这里所用的“高介电常数”是指介电常数为10或更大的电介质。
在硅衬底10上方的可以是调节层12。在一个实施例中,调节层12可以是具有15%铝的AlInSb。在硅衬底10上方,也可以在层12下方包含锗层(未示出)。调节层12用于调节晶格失配问题且用于将错位或缺陷限制在那个层12。
根据本发明的一个实施例,可以在调节层12上方形成下阻挡层14。作为两个实例,下阻挡层14可以由例如锑化铝铟或砷化铟铝形成。下阻挡层14可以由能带隙高于上面的量子阱16的材料形成。
在下阻挡层14上方形成未掺杂量子阱16。在一个实施例中,作为两个实例,未掺杂量子阱16可以由锑化铟或砷化铟镓形成。
接着,可以形成上阻挡层20。上阻挡层20可以由与下阻挡层14相同或不同的材料形成。上阻挡层20可以包括δ掺杂施主层18。作为两个实例,δ掺杂可以使用硅或碲来完成。掺杂施主层18将载流子供应给量子阱16以用于传输。掺杂施主层18是通过允许Te或Si掺杂剂以受控方式从固体源流入到MBE(分子束外延)腔室中而形成的。
因此,将量子阱16夹在上阻挡层20和下阻挡层14之间。上阻挡层20可以是电子供应层,其厚度将与形成栅电极38的肖特基金属层的功函数一起决定晶体管的阈电压。
金属栅电极38可以形成在高介电常数电介质材料26上。材料26在三个面上托住金属栅电极38。而高介电常数层26又可以由自对准的源漏接触金属22和间隔物层28托住。
如图2所示,如图1所示的耗尽型晶体管和图10的增强型晶体管的制造可以通过形成一直到并且包括n+掺杂层30的结构而开始。层30可以包括用Te和Si杂质掺杂的锑化铟或砷化铟镓。层30可以经重掺杂以便稍后形成成品晶体管中的源漏区域。
作为两个实例,多层外延衬底10可以利用分子束外延法或金属有机化学气相沉积法来生长。
参照图3,根据本发明的一个实施例,可以在n+掺杂层30上形成虚拟栅极32。它可以在图案化和蚀刻掉氮化物、碳化物或氧化物薄膜(未示出)后形成。有利地,这些薄膜可以通过低温沉积来形成,以便保持外延层结构的完整性。虚拟栅极32可以由例如氮化硅或金属形成。虚拟栅极32可以通过利用光刻和蚀刻(在氮化硅虚拟栅极32的情况下)或利用蒸镀和剥离(在金属栅极32的情况下,如铝金属栅极)进行图案化来形成。
接下来参照图4,可以形成用于托住虚拟栅极32的低温氧化硅、氮化硅或碳化硅间隔物28。间隔物28可以通过利用低温沉积技术、接着进行各向异性蚀刻来形成。
接下来转到图5,可以通过以下方法形成自对准源漏接触金属22:首先进行电子束蒸镀或反应性溅镀,也可在此之后进行化学机械平坦化处理,以便制作自对准接触物,这些自对准接触物还要在层30中形成源漏区域。源漏接触金属22可以由例如钛或金形成。
接着,如图6所示,可以利用湿式蚀刻来选择性地蚀刻掉虚拟栅极32。结果,形成开口34。金属虚拟栅极移除过程可以包括例如利用磷酸蚀刻的湿式蚀刻。对于氮化物虚拟栅极,可以使用盐酸。对于二氧化硅虚拟栅极,可以利用氢氟酸蚀刻。湿式蚀刻法对于n+掺杂层30具有选择性。
接着,如图7所示,对于耗尽型器件,可以选择性地蚀刻掉n+掺杂层30以便形成具有翼部36和基部34的倒T形开口。可以利用干式或湿式蚀刻来形成翼部36。例如,利用诸如柠檬酸加过氧化物的湿式蚀刻法来选择性地移除n+掺杂层30。
在原子层沉积高介电常数材料26之后,可以电子束蒸镀或溅镀金属栅电极38。举几个实例,栅电极38可以是例如铂、钨、钯或钼。作为两个实例,高介电常数电介质26可以是例如二氧化铪或二氧化锆。低温沉积法可以与有机前驱物(如用于二氧化铪沉积的醇盐前驱物)一起使用。
接着,可以使如图8所示的结构进行金属栅电极38和高介电常数电介质26的化学机械抛光,以便获得如图9所示的耗尽型结构。
就在蚀刻掉n+掺杂层30以便形成如图7所示的包括翼部36和基部34的开口34之后,可以通过电子供应阻挡层20来完成进一步的凹进蚀刻,该蚀刻正好在δ掺杂层18上方停止以便制造如图10所示的增强型器件。时间驱动蚀刻(未在图7中示出)可以在间隔物28下方部分地凹进图7中的电子供应阻挡层20中,以便增加晶体管的阈电压并形成增强型器件。
器件层结构幸免于高介电常数沉积工艺。在这之后可以进行肖特基栅电极38的溅镀沉积或电子束沉积。可以选择栅电极38的功函数以使其尽可能高,以便制作增强型器件。
本发明的一些实施例可以通过在电极38的肖特基栅极金属和半导体阻挡层20之间并入高介电常数电介质20来实现较低栅极漏电。在一些实施例中,较低寄生串联电阻可以由与栅极自对准的重掺杂源漏区域产生。在一些实施例中,通过将电子供应阻挡层20凹进蚀刻至所需厚度来形成增强型量子阱场效应晶体管。
尽管关于有限数量的实施例描述了本发明,但本领域的技术人员将由此明白众多修改和变型。希望所附权利要求覆盖所有那些落在本发明的真实精神和范围内的修改和变型。
Claims (41)
1.一种制造量子阱晶体管的方法,包括:
形成第一和第二阻挡层;
在所述阻挡层之间形成量子阱层;
在衬底上方、第二阻挡层下方形成调节层,用于调节晶格失配问题且用于将错位或缺陷限制在所述调节层;
在掺杂层中沉积栅电极;
从所述掺杂层形成与所述栅电极自对准的源漏极;以及
在所述掺杂层中形成开口,
其中,所述调节层是具有15%铝的AlInSb。
2.如权利要求1所述的方法,包括:沉积金属栅电极。
3.如权利要求2所述的方法,包括:利用所述掺杂层上方的虚拟栅极;随后移除所述虚拟栅极。
4.如权利要求3所述的方法,包括:利用所述虚拟栅极来定义侧壁间隔物。
5.如权利要求4所述的方法,包括:利用所述侧壁间隔物来定义自对准源漏接触物。
6.如权利要求5所述的方法,包括:在定义所述间隔物和所述接触物之后移除所述虚拟栅极。
7.如权利要求6所述的方法,包括:利用所述接触物和所述间隔物作为掩模来蚀刻所述掺杂层并定义栅极。
8.如权利要求7所述的方法,包括:蚀刻所述掺杂层以便底切所述间隔物。
9.如权利要求8所述的方法,包括:在所述开口中沉积介电常数大于10的电介质。
10.如权利要求9所述的方法,包括:在所述电介质上方形成金属栅电极。
11.如权利要求10所述的方法,包括:在所述电介质下方形成阻挡层。
12.如权利要求11所述的方法,包括:通过所述电介质将所述金属栅电极与所述阻挡层分离。
13.如权利要求1所述的方法,包括:通过蚀刻穿过所述掺杂层来形成耗尽型晶体管。
14.如权利要求12所述的方法,包括:通过在上阻挡层上方形成所述掺杂层并蚀刻进所述上阻挡层中以使得所述栅极电介质延伸穿过所述掺杂层并进入所述上阻挡层来形成增强型晶体管。
15.如权利要求8所述的方法,包括:控制蚀刻深度以确定形成增强型还是耗尽型器件。
16.如权利要求15所述的方法,包括:蚀刻穿过所述掺杂层并进入下面的阻挡层中以形成增强型器件。
17.一种制造量子阱晶体管的方法,包括:
形成具有阻挡层和肖特基栅极金属以及位于所述栅极金属和所述阻挡层之间的电介质的量子阱晶体管,所述电介质的介电常数大于10;
在衬底上方、阻挡层下方形成调节层,用于调节晶格失配问题且用于将错位或缺陷限制在所述调节层;
在掺杂层中沉积栅电极;
从所述掺杂层形成与所述栅电极自对准的源漏极;以及
在所述掺杂层中形成开口,
其中,所述调节层是具有15%铝的AlInSb。
18.如权利要求17所述的方法,包括:沉积金属栅电极。
19.如权利要求18所述的方法,包括:利用所述掺杂层上的虚拟栅极;随后移除所述虚拟栅极。
20.如权利要求19所述的方法,包括:利用所述虚拟栅极来定义侧壁间隔物。
21.如权利要求20所述的方法,包括:利用所述侧壁间隔物来定义自对准源漏接触物。
22.如权利要求21所述的方法,包括:在定义所述间隔物和所述接触物之后移除所述虚拟栅极。
23.如权利要求22所述的方法,包括:利用所述接触物和所述间隔物作为掩模来蚀刻所述掺杂层并定义栅极。
24.如权利要求23所述的方法,包括:蚀刻所述掺杂层以便底切所述间隔物。
25.如权利要求24所述的方法,包括:在所述开口中沉积介电常数大于10的电介质。
26.如权利要求25所述的方法,包括:在所述电介质上方形成金属栅电极。
27.如权利要求26所述的方法,包括:在所述电介质下方形成所述阻挡层。
28.如权利要求27所述的方法,包括:通过所述电介质将所述金属栅电极与所述阻挡层分离。
29.如权利要求17所述的方法,包括:通过蚀刻穿过所述掺杂层来形成耗尽型晶体管。
30.如权利要求25所述的方法,包括:通过在所述阻挡层上方形成所述掺杂层并蚀刻进所述阻挡层中以使得所述电介质延伸穿过所述掺杂层并进入所述阻挡层中来形成增强型晶体管。
31.如权利要求24所述的方法,包括:控制蚀刻深度以确定形成增强型还是耗尽型器件。
32.如权利要求31所述的方法,包括:蚀刻穿过所述掺杂层并进入下面的阻挡层中以形成增强型器件。
33.一种量子阱晶体管,包括:
第一和第二阻挡层;
位于所述阻挡层之间的量子阱层;
位于衬底上方、第二阻挡层下方的调节层,用于调节晶格失配问题且用于将错位或缺陷限制在所述调节层;
栅电极;
与所述栅电极自对准的源漏极;以及
位于所述栅电极上的侧壁间隔物,
其中,所述调节层是具有15%铝的AlInSb。
34.如权利要求33所述的晶体管,其特征在于,所述栅电极是金属栅电极。
35.如权利要求34所述的晶体管,包括:所述源极和漏极的接触金属。
36.如权利要求33所述的晶体管,包括:位于所述栅电极和所述第一阻挡层之间的电介质,所述电介质的介电常数大于10。
37.如权利要求36所述的晶体管,其特征在于,所述电介质是U形。
38.一种量子阱晶体管,包括:
第一和第二阻挡层;
位于所述阻挡层之间的量子阱层;
位于衬底上方、第二阻挡层下方的调节层,用于调节晶格失配问题且用于将错位或缺陷限制在所述调节层;
金属栅电极;
位于所述栅电极和所述第一阻挡层之间的电介质,所述电介质的介电常数大于10;
与所述栅电极自对准的源漏极;以及
位于所述栅电极上的侧壁间隔物,
其中,所述调节层是具有15%铝的AlInSb。
39.如权利要求38所述的晶体管,包括自对准源漏极。
40.如权利要求38所述的晶体管,包括所述源极和漏极的接触金属。
41.如权利要求38所述的晶体管,其特征在于,所述电介质是U形。
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Families Citing this family (45)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060086977A1 (en) | 2004-10-25 | 2006-04-27 | Uday Shah | Nonplanar device with thinned lower body portion and method of fabrication |
US7518196B2 (en) | 2005-02-23 | 2009-04-14 | Intel Corporation | Field effect transistor with narrow bandgap source and drain regions and method of fabrication |
US7547637B2 (en) | 2005-06-21 | 2009-06-16 | Intel Corporation | Methods for patterning a semiconductor film |
TWI401803B (zh) * | 2005-06-30 | 2013-07-11 | Semiconductor Energy Lab | 微結構、微機械、有機電晶體、電氣設備、及其製造方法 |
US20070090416A1 (en) | 2005-09-28 | 2007-04-26 | Doyle Brian S | CMOS devices with a single work function gate electrode and method of fabrication |
US20070093055A1 (en) * | 2005-10-24 | 2007-04-26 | Pei-Yu Chou | High-aspect ratio contact hole and method of making the same |
US7485503B2 (en) * | 2005-11-30 | 2009-02-03 | Intel Corporation | Dielectric interface for group III-V semiconductor device |
US8183556B2 (en) * | 2005-12-15 | 2012-05-22 | Intel Corporation | Extreme high mobility CMOS logic |
US8143646B2 (en) * | 2006-08-02 | 2012-03-27 | Intel Corporation | Stacking fault and twin blocking barrier for integrating III-V on Si |
US20080142786A1 (en) * | 2006-12-13 | 2008-06-19 | Suman Datta | Insulated gate for group iii-v devices |
US7601980B2 (en) * | 2006-12-29 | 2009-10-13 | Intel Corporation | Dopant confinement in the delta doped layer using a dopant segregation barrier in quantum well structures |
US9076852B2 (en) * | 2007-01-19 | 2015-07-07 | International Rectifier Corporation | III nitride power device with reduced QGD |
US7928426B2 (en) | 2007-03-27 | 2011-04-19 | Intel Corporation | Forming a non-planar transistor having a quantum well channel |
US7435987B1 (en) * | 2007-03-27 | 2008-10-14 | Intel Corporation | Forming a type I heterostructure in a group IV semiconductor |
US7713803B2 (en) * | 2007-03-29 | 2010-05-11 | Intel Corporation | Mechanism for forming a remote delta doping layer of a quantum well structure |
US7791063B2 (en) * | 2007-08-30 | 2010-09-07 | Intel Corporation | High hole mobility p-channel Ge transistor structure on Si substrate |
US20100006895A1 (en) * | 2008-01-10 | 2010-01-14 | Jianjun Cao | Iii-nitride semiconductor device |
US8362566B2 (en) | 2008-06-23 | 2013-01-29 | Intel Corporation | Stress in trigate devices using complimentary gate fill materials |
US8115235B2 (en) * | 2009-02-20 | 2012-02-14 | Intel Corporation | Modulation-doped halo in quantum well field-effect transistors, apparatus made therewith, and methods of using same |
CN101853882B (zh) * | 2009-04-01 | 2016-03-23 | 台湾积体电路制造股份有限公司 | 具有改进的开关电流比的高迁移率多面栅晶体管 |
US8816391B2 (en) * | 2009-04-01 | 2014-08-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Source/drain engineering of devices with high-mobility channels |
US8455860B2 (en) * | 2009-04-30 | 2013-06-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reducing source/drain resistance of III-V based transistors |
US9768305B2 (en) | 2009-05-29 | 2017-09-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Gradient ternary or quaternary multiple-gate transistor |
US8617976B2 (en) * | 2009-06-01 | 2013-12-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Source/drain re-growth for manufacturing III-V based transistors |
US8368052B2 (en) * | 2009-12-23 | 2013-02-05 | Intel Corporation | Techniques for forming contacts to quantum well transistors |
US8283653B2 (en) | 2009-12-23 | 2012-10-09 | Intel Corporation | Non-planar germanium quantum well devices |
US8193523B2 (en) | 2009-12-30 | 2012-06-05 | Intel Corporation | Germanium-based quantum well devices |
CN102254824B (zh) * | 2010-05-20 | 2013-10-02 | 中国科学院微电子研究所 | 半导体器件及其形成方法 |
US8455929B2 (en) | 2010-06-30 | 2013-06-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Formation of III-V based devices on semiconductor substrates |
US8084311B1 (en) | 2010-11-17 | 2011-12-27 | International Business Machines Corporation | Method of forming replacement metal gate with borderless contact and structure thereof |
CN103165429B (zh) * | 2011-12-15 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | 金属栅极形成方法 |
JP2013138201A (ja) | 2011-12-23 | 2013-07-11 | Imec | 置換ゲートプロセスに従って電界効果半導体デバイスを製造する方法 |
EP2696369B1 (en) | 2012-08-10 | 2021-01-13 | IMEC vzw | Methods for manufacturing a field-effect semiconductor device |
US8912059B2 (en) | 2012-09-20 | 2014-12-16 | International Business Machines Corporation | Middle of-line borderless contact structure and method of forming |
US9583574B2 (en) * | 2012-09-28 | 2017-02-28 | Intel Corporation | Epitaxial buffer layers for group III-N transistors on silicon substrates |
US8835237B2 (en) | 2012-11-07 | 2014-09-16 | International Business Machines Corporation | Robust replacement gate integration |
CN103855001A (zh) * | 2012-12-04 | 2014-06-11 | 中芯国际集成电路制造(上海)有限公司 | 晶体管及其制造方法 |
US9373706B2 (en) | 2014-01-24 | 2016-06-21 | Samsung Electronics Co., Ltd. | Methods of forming semiconductor devices, including forming a semiconductor material on a fin, and related semiconductor devices |
WO2017099707A1 (en) * | 2015-12-07 | 2017-06-15 | Intel Corporation | Self-aligned transistor structures enabling ultra-short channel lengths |
US10665688B2 (en) * | 2015-12-24 | 2020-05-26 | Intel Corporation | Low Schottky barrier contact structure for Ge NMOS |
TWI681561B (zh) * | 2017-05-23 | 2020-01-01 | 財團法人工業技術研究院 | 氮化鎵電晶體元件之結構及其製造方法 |
US11004958B2 (en) * | 2018-10-31 | 2021-05-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of manufacturing a semiconductor device and a semiconductor device |
TWI685968B (zh) | 2018-11-23 | 2020-02-21 | 財團法人工業技術研究院 | 增強型氮化鎵電晶體元件及其製造方法 |
US11127820B2 (en) * | 2019-09-20 | 2021-09-21 | Microsoft Technology Licensing, Llc | Quantum well field-effect transistor and method for manufacturing the same |
JP7456449B2 (ja) * | 2019-11-29 | 2024-03-27 | 日本電信電話株式会社 | 電界効果型トランジスタの製造方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1319881A (zh) * | 2000-03-09 | 2001-10-31 | 三星电子株式会社 | 在金属镶嵌栅极工艺中形成自对准接触焊盘的方法 |
US6498360B1 (en) * | 2000-02-29 | 2002-12-24 | University Of Connecticut | Coupled-well structure for transport channel in field effect transistors |
CN1429408A (zh) * | 2000-05-19 | 2003-07-09 | 秦内蒂克有限公司 | 载流子提取晶体管 |
CN1607677A (zh) * | 2003-10-14 | 2005-04-20 | 国际商业机器公司 | 制造高迁移率场效应晶体管的结构和方法 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02202029A (ja) * | 1989-01-31 | 1990-08-10 | Sony Corp | 化合物半導体装置 |
JPH0521468A (ja) * | 1991-07-17 | 1993-01-29 | Sumitomo Electric Ind Ltd | 電界効果トランジスタの製造方法 |
US5489539A (en) * | 1994-01-10 | 1996-02-06 | Hughes Aircraft Company | Method of making quantum well structure with self-aligned gate |
US5929467A (en) * | 1996-12-04 | 1999-07-27 | Sony Corporation | Field effect transistor with nitride compound |
US6144048A (en) * | 1998-01-13 | 2000-11-07 | Nippon Telegraph And Telephone Corporation | Heterojunction field effect transistor and method of fabricating the same |
US6278165B1 (en) * | 1998-06-29 | 2001-08-21 | Kabushiki Kaisha Toshiba | MIS transistor having a large driving current and method for producing the same |
US6232159B1 (en) * | 1998-07-22 | 2001-05-15 | Matsushita Electric Industrial Co., Ltd. | Method for fabricating compound semiconductor device |
JP2000349280A (ja) * | 1999-06-03 | 2000-12-15 | Nec Corp | 半導体装置及びその製造方法並びに半導体基板構造 |
JP3762588B2 (ja) * | 1999-10-05 | 2006-04-05 | 富士通株式会社 | 半導体装置の製造方法 |
JP3371871B2 (ja) * | 1999-11-16 | 2003-01-27 | 日本電気株式会社 | 半導体装置の製造方法 |
KR100379619B1 (ko) * | 2000-10-13 | 2003-04-10 | 광주과학기술원 | 단일집적 e/d 모드 hemt 및 그 제조방법 |
US6849882B2 (en) * | 2001-05-11 | 2005-02-01 | Cree Inc. | Group-III nitride based high electron mobility transistor (HEMT) with barrier/spacer layer |
US6900467B2 (en) * | 2001-05-21 | 2005-05-31 | Stanley Electric Co., Ltd. | Semiconductor light emitting device having quantum well layer sandwiched between carrier confinement layers |
WO2004019415A1 (en) * | 2002-08-26 | 2004-03-04 | University Of Florida | GaN-TYPE ENHANCEMENT MOSFET USING HETERO STRUCTURE |
-
2005
- 2005-01-03 US US11/028,378 patent/US20060148182A1/en not_active Abandoned
-
2006
- 2006-01-03 WO PCT/US2006/000138 patent/WO2006074197A1/en active Application Filing
- 2006-01-03 TW TW095100171A patent/TWI310990B/zh not_active IP Right Cessation
- 2006-01-03 GB GB0714638A patent/GB2438331B/en not_active Expired - Fee Related
- 2006-01-03 CN CN2006800068402A patent/CN101133498B/zh not_active Expired - Fee Related
- 2006-01-03 DE DE112006000133T patent/DE112006000133T5/de not_active Ceased
- 2006-01-03 KR KR1020077017824A patent/KR100948211B1/ko not_active IP Right Cessation
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6498360B1 (en) * | 2000-02-29 | 2002-12-24 | University Of Connecticut | Coupled-well structure for transport channel in field effect transistors |
CN1319881A (zh) * | 2000-03-09 | 2001-10-31 | 三星电子株式会社 | 在金属镶嵌栅极工艺中形成自对准接触焊盘的方法 |
CN1429408A (zh) * | 2000-05-19 | 2003-07-09 | 秦内蒂克有限公司 | 载流子提取晶体管 |
CN1607677A (zh) * | 2003-10-14 | 2005-04-20 | 国际商业机器公司 | 制造高迁移率场效应晶体管的结构和方法 |
Non-Patent Citations (4)
Title |
---|
JP特开平5-67816A 1993.03.19 |
Matthias et al..Self-aligned GaAs p-channel Enhancement Mode MOSheterostructure Field-Effect Transistor.IEEE Electron Device Letters23 9.2002,23(9),图1. |
Matthias et al..Self-aligned GaAs p-channel Enhancement Mode MOSheterostructure Field-Effect Transistor.IEEE Electron Device Letters23 9.2002,23(9),图1. * |
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GB2438331B (en) | 2010-10-13 |
WO2006074197A1 (en) | 2006-07-13 |
KR20070088817A (ko) | 2007-08-29 |
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US20060148182A1 (en) | 2006-07-06 |
KR100948211B1 (ko) | 2010-03-18 |
DE112006000133T5 (de) | 2008-04-30 |
GB0714638D0 (en) | 2007-09-05 |
CN101133498A (zh) | 2008-02-27 |
TW200636998A (en) | 2006-10-16 |
GB2438331A (en) | 2007-11-21 |
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