TWI310990B - Quantum well transistor using high dielectric constant dielectric layer - Google Patents

Quantum well transistor using high dielectric constant dielectric layer Download PDF

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TWI310990B
TWI310990B TW095100171A TW95100171A TWI310990B TW I310990 B TWI310990 B TW I310990B TW 095100171 A TW095100171 A TW 095100171A TW 95100171 A TW95100171 A TW 95100171A TW I310990 B TWI310990 B TW I310990B
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layer
forming
gate
quantum well
barrier layer
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TW200636998A (en
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Suman Datta
Justin Brask
Jack Kavalieros
Matthew Metz
Mark Doczy
Robert Chau
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Intel Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66848—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
    • H01L29/66856—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET with an active layer made of a group 13/15 material
    • H01L29/66863—Lateral single gate transistors
    • H01L29/66871—Processes wherein the final gate is made after the formation of the source and drain regions in the active layer, e.g. dummy-gate processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
    • H01L29/7784—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material with delta or planar doped donor layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/47—Schottky barrier electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Description

1310990 (1) 九、發明說明 【發明所屬之技術領域】 本發明係相關於量子井電晶體的形成。 【先前技術】 量子井是一限制粒子在一維空間中迫使粒子佔據一平 面區之電位井。夾置在具有比第一材料寬的能帶隙之兩層 Φ 材料之間的第一材料可形成量子井。量子井或高電子遷移 率電晶體（HEMTs )是具有在有著不同能帶隙的兩材料之 間的接面霄作通道之場效電晶體。接面可顯現出非常低的 電阻或高電子遷移率。施加到閘極的電壓可改變接面的導 電性。 量子井電晶體容易傾向高閘極漏洩及寄生串聯電阻。 尤其是’使用來自週期表的行III到V之元素的量子井電 晶體容易有此種問題。此種材料的例子包括砷化銦鎵/砷 φ 化銦鋁和銻化銦/銻化鋁銦。 在量子井電晶體的目前技藝狀態中，直接Schottky 金屬閘極可沉積在屏障層上而形成易有高閘極漏洩之 Schottky接面。而且，源極和汲極區可被圖型化，並且在 •閘極圖型化之前完成源極和汲極金屬化接點。在處理中， 閘極圖型化爲最後一步驟，如此產生非自我對準的源極汲 極區。此種非自我對準的源極汲極區易有寄生串聯電阻。 具有寄生串聯電阻的裝置可能顯現出不良的性能。 如此，需要有更好的方式製造量子井。 -5- (2) 1310990 【發明內容及實施方式】 參照圖I及10，空乏（圖1)或增強模式（圖10) 自我對準源極汲極量子井可被形成有高介電常數介電層 24及當作Schottky閘金屬的金屬閘電極38。本文所使用 的''高介電常數"意指具有介電常數10或更高之介質。 在矽基底1 0上可以是調節層1 2。在一實施例中，調 • 節層12可以是具有15%銘的AllnSb。在砂基底1〇上， 鍺層（未圖示）也可包括在層12下。調節層12用於調節 晶格失配問題並且限制那層1 2中的位錯或故障。 根據本發明的一實施例，在調節層12上可形成下屏 障層1 4。例如可由銻化鋁銦或砷化銦鋁形成下屏障層J 4 當作兩例子。可由能帶隙比下面量子井1 6高的材料形成 下屏障層14。在下屏障層14上形成未摻雜量子井16。在 一實施例中’可由銻化銦或砷化銦鎵形成未摻雜量子井 • 1 6當作兩例子。 接著’可形成上屏障層20。可由與下屏障層14相同 或不问的材料形成上屏障層20。上屏障層20可包括5慘 雜施體層18。可使用矽或碲進行（5摻雜當作兩例子。摻 、雜施體層18供應載子到量子井16用於輸送。藉由在控制 的方式下使Te或Si摻雜劑能夠從固體源流入MBE (分 子束外延）室內以形成摻雜施體層1 8。 如此，量子井1 6夾置在上和下屏障層2 0及1 4之間 。上屏障層20可以是電子供應層，其厚度與形成閘電極
-6- 1310990 _ (3) 38之Schottky金屬層的功函數將一起決定電晶體的臨界 電壓。 金屬閘電極38可形成在高介電常數介電材料26上。 材料2 6圍住金屬閘電極3 8在三側上。接著’可以自我對 準源極汲極金屬化接點22及間隔物層28圍住高介電常數 層2 6。 如圖2所示，可藉由形成結構直到並且包括n +摻雜 # 層3 0開始圖1所示的空乏模式電晶體和圖1 0的增強模式 電晶體之製造。層30可包括摻雜有Te及Si雜質的銻化 銦或砷化銦鎵。可高度摻雜層3 0用以稍後在完成的電晶 體中形成源極汲極區。 可使用分子束外延或金屬有機化學汽相沉積生長多層 外延基底1 〇當作兩例子。 參照圖3，根據本發明的一實施例，虛擬閘極3 2可 形成在η +慘雜層3 0上。可在圖型化及蝕刻掉氮化物、碳 φ 化物、或氧化物薄膜（未圖示）之後形成虛擬閘極3 2。 有利的是，可以低溫沉積形成這些薄膜以維持外延層的完 整。可例如由氮化矽或金屬形成虛擬閘極3 2。在氮化矽 虛擬閘極3 2的例子中可以平板印刷及蝕刻，或在諸如鋁 '金屬虛擬閘極等金屬閘32的例子中可以蒸發及拔除藉由 圖型化形成虛擬閘極3 2。 接著參照圖4，可形成圍住虛擬閘極3 2之低溫矽氧 化物、氮化物、或碳化物間隔物2 8。可利用低溫沉積技 術然後各向異性蝕刻以形成間隔物2 8。 (4) 1310990 接著到圖5，可藉由電子束蒸發或反應濺射法然後化 學機械平面化處理以形成自我對準源極汲極金屬化接點 22，用以產生到形成在層30中的源極汲極區之自我對準 接點。例如可由鈦或金形成源極汲極金屬化接點22。 然後，如圖6所示，可使用濕蝕刻選擇性蝕刻掉虛擬 閘極3 2。結果，形成開口 3 4。金屬虛擬閘極移除處理例 如可包括使用磷酸蝕刻的濕蝕刻。就氮化物虛擬閘極而言 φ ，可使用氫氯酸蝕刻。就二氧化矽虛擬閘極而言，可使用 氫氟酸蝕刻。濕蝕刻處理選擇性處理n +摻雜層3 0。 然後’如圖7所示，就空乏模式裝置而言，可達成 n +摻雜層30之選擇性蝕刻以形成具有翼36及基座34之 倒置的T型開口。乾或濕蝕刻可被用於形成翼3 6。例如 ’使用諸如檸檬酸加過氧化氫等濕蝕刻處理選擇性移除 η +撥雜層3 0。 高介電常數材料26的原子層沉積之後可接著金屬閘 Φ 電極3 8的電子束蒸發或濺射。閘電極3 8例如可以是鉑、 鎢、把、或鉬當作一些例子。高介電常數介質2 6例如可 以是二氧化飴或二氧化鉻當作兩例子。可與有機先質（諸 如用於二氧化鈴沉積的烷氧化物先質）一起使用低溫沉積 處理。 然後’圖8所示的結構可經過金屬閘電極3 8及高介 電常數介質26的化學機械拋光以達成圖9所示的空乏模 式結構。 如圖 7所示’在蝕刻 η +摻雜層30以形成包括翼36 8 1310990 ' (5) 及基座34的開口之後，可經由電子供應屏障層20進行另 一凹處蝕刻，如圖1 0所示，停止在剛好<5摻雜層1 8上以 製作增強模式裝置。時間驅動蝕刻（未圖示在圖7 )可局 部凹進圖7的電子供應屏障層20內及間隔物28下，以增 加電晶體的臨界電壓和形成增強模式裝置。 裝置層結構經過高介電常數沉積處理。接著Schottky 閘電極3 8的濺射沉積或電子束沉積。閘電極3 8功函數的 # 選擇越高越好以產生增強模式裝置。 本發明的某些實施例可從倂入高介電常數介質20到 電極38的Schottky閘金屬和半導體屏障層20之間以達 成較低的閘極漏洩。在某些實施例中，自我對準到閘極的 高摻雜源極汲極區產生較低的寄生串聯電阻。在某些實施 例中，電子供應屏障層2 0的凹處蝕刻到想要的厚度形成 增強模式量子井場效電晶體。 儘管已經由有限數目的實施例說明本發明，但是精於 • 本技藝之人士將明白可自此有許多修正和變化。附錄於後 的申請專利範圍用於涵蓋此種落在本發明的真正精神和範 圍之修正和變化。 【圖式簡單說明】 圖1爲本發明的一實施例之放大橫剖面圖； 圖2爲根據本發明的一實施例之早期製造階段中的圖 1所示之實施例的放大橫剖面圖； 圖3爲根據本發明的一實施例之後續處理後的圖2所 -9 - 也 1310990 . (6) 示之實施例的放大橫剖面圖； 圖4爲根據本發明的一實施例之後續處理後的對應於 圖3之放大橫剖面圖； 圖5爲根據本發明的一實施例之後續處理後的對應於 圖4之放大橫剖面圖； 圖6爲根據本發明的一實施例之後續處理後的對應於 圖5之放大橫剖面圖； g 圖7爲根據本發明的一實施例之後續處理後的對應於 圖6之放大橫剖面圖； 圖8爲根據本發明的另一實施例之後續處理後的對應 於圖7之放大橫剖面圖； 圖9爲根據本發明的空乏模式實施例之後續處理後的 對應於圖8之放大橫剖面圖；及 圖】〇爲根據本發明的增強模式實施例之後續處理後 的對應於圖7之放大橫剖面圖。 【主要元件符號說明】 1 〇 :矽基底 1 2 :調節層 1 4 :下屏障層 1 6 :未摻雜量子井 1 8 : (5摻雜施體層 20 :上屏障層 22 :自我對準源極汲極金屬化接點
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V (7) (7)1310990 24:高介電常數介電層 26:高介電常數材料 2 8 :間隔物層 3 0 : η +摻雜層 3 2 :虛擬閘極 34 :開口 34 :基座 36 :翼 3 8 :金屬閘電極
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Claims (1)

1^10990 十、申請專利範圍 附件2 A : 第9 5 1 0 0 1 7 1號專利申請案 中文申請專利範圍替換本 ί.·' . -f 斗 民國97年3月5 —白修正 η 一 1· 一種製造量子井電晶體之方法，包含：. 形成一量子井； 在該量子井上形成一屏障層； •在該屏障層上形成一閘介電質； 在該閘介電質上形成一閘電極； 形成一自我對準源極汲極； 選擇性地形成一空乏模式裝置，藉著在該屏障層的頂 部上形成該閘介電質；及 選擇性地形成一增強模式裝置，藉著在該屏障層內形 成閘氧化物。 2. 根據申請專利範圍第1項之方法，包括從一摻雜 Φ 層形成一自我對準源極汲極，在該摻雜層中形成一開口， 並且在該摻雜層中沉積一閘電極。 3. 根據申請專利範圍第2項之方法，包括沉積一金 屬閘電極。 ' 4.根據申請專利範圍第3項之方法，包括在該摻雜 • 層上使用一虛擬閘極’並且隨後移除該虛擬閘極。 5. 根據申請專利範圍第4項之方法，包括使用該虛 擬閘極界定一側壁間隔物。 6. 根據申請專利範圍第5項之方法，包括使用該側 1310990 f 壁間隔物以界定自我對準源極汲極接點。 7. 根據申請專利範圍第6項之方法，包括在界定該 間隔物和該接點之後移除該虛擬閘極。 8. 根據申請專利範圍第7項之方法，包括使用該接 點和該間隔物當作一掩模以蝕刻該摻雜層及界定一源極和 汲極。 9 ·根據申請專利範圍第8項之方法，包括蝕刻該摻 • 雜層以便底切該間隔物。 10·根據申請專利範圍第9項之方法，包括在該開口 中沉積具有大於10的介電常數之一層。 Π·根據申請專利範圍第10項之方法，包括在該介 電質上形成一金屬閘電極。
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TW095100171A 2005-01-03 2006-01-03 Quantum well transistor using high dielectric constant dielectric layer TWI310990B (en)

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CN (1) CN101133498B (zh)
DE (1) DE112006000133T5 (zh)
GB (1) GB2438331B (zh)
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WO (1) WO2006074197A1 (zh)

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