CN101124857A - 封装安装模块和封装基板模块 - Google Patents
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Abstract
本发明涉及在表面上装载有LSI等半导体芯片的封装基板模块和在大型计算机等的母板上安装有该封装基板的封装安装模块,可以减少在焊接部产生的应力。使支承封装基板(11)的加强件(140)和/或支承母板(21)的加强件(220)为粘贴热膨胀率互不相同的第一部件(141、221)和第二部件(142、222)的双金属结构,以效仿因温度变化而引起的封装基板(11)和母板(21)的弯曲的方式而使加强件(140、220)弯曲,由此抑制在锡焊部产生应力。
Description
技术领域
本发明涉及在表面上装载有LSI等半导体芯片的封装基板模块和在大型计算机等母板上安装有该封装基板的封装安装模块。
背景技术
近年来,在大型计算机等大规模计算机的基板(主要是母板)中,由于信号数的增大,已装载了超过端子数2000引脚的大型封装,其尺寸也超过了40mm×40mm。这样一来,由于封装尺寸较大,因而安装了防止封装整体弯曲的加强件。
图4是表示现有封装基板模块的剖视示意图。
在该图4所示的封装基板模块10中,通过由焊球13的熔融、固定而进行的焊接,将LSI芯片12装载在封装基板11的表面上,并且,还具有加强件14,该加强件14以围绕该LSI芯片12的方式在与封装基板11的表面相连接的状态下进行固定。该加强件14用于支承封装基板11并防止封装基板11的弯曲。在封装基板11的背面上具有焊球15,该封装基板11如以下参照图5所说明的那样装载在母板上。
图5是表示现有封装安装模块的剖面结构图。
这里,对图4所示的封装基板模块标记相同的符号,而省略重复说明。
在该图5所示的封装安装模块20中,通过由图4所示的封装基板11的背面的焊球15的熔融、固定而进行的焊接,将该图4所示的整个封装基板模块10装载在母板21的表面。另外,在母板20的背面的、与封装基板11夹持该母板21的位置上配备有加强件22。该加强件22具有比封装基板11的面积大的面积,在将封装基板11、母板21以及加强件22重叠投影来进行观察时,在处于封装基板11外围的、加强件22的周边部上,在多处通过连结部件(这里为螺钉23)对母板21和加强件22进行固定。
图6是图5所示的现有封装安装模块的问题的说明图。
一直以来,加强件14、22由单一金属构成,由于从锡焊熔点至常温的装配温度差、或者装置工作时和停止时的温度差,在LSI芯片12和封装基板11之间、封装基板11和母板12之间会产生因热膨胀率的差异引起的弯曲。通常,与LSI芯片12的热膨胀率(4ppm/K左右)相比较,封装基板11为9~15ppm/K,母板21为17~22ppm/K左右,均较大。如图6所示,以焊料熔点以上的温度进行焊接后,在向母板21侧弯曲(凸向封装基板11侧)的同时降至常温。此时,封装基板11和母板21残留着弯曲,而加强件14、22仍很平坦,封装基板11通过加强件14被强制矫正为平坦,母板21通过加强件22被强制矫正为平坦,因此在LSI芯片12和封装基板11之间的焊接部与封装基板11和母板21之间的焊接部上会产生应力。这些应力成为大大降低焊接的可靠性的主要原因之一,期望减少这些应力。特别是,由于近年来因限制有害物质而不能使用铅,因此使用锡-银-铜焊料(熔点218℃)等高熔点焊料来取代以前所使用的锡-铅共晶焊料(熔点:183℃),从焊料熔点至常温的温度范围扩大,从而使得产生较大应力的倾向愈加明显。
这里,专利文献1提出了使基板为双金属结构,使双金属在与由从焊料熔点至常温的温度变化引起的基板的翘曲相反的方向上发挥作用,来防止基板的翘曲的方案。
但是,这是利用基板自身矫正基板的弯曲,来取代参照图4~图6说明的通过加强件14、22矫正基板的弯曲的方案,其并不能防止因强制矫正基板的翘曲而产生的应力。
专利文献1:日本专利文献特开平2-116197号公报。
发明内容
本发明鉴于上述问题,目的在于提供可减少在锡焊部上产生的应力的封装安装模块和封装基板模块。
完成上述目的的本发明的封装安装模块,具有:封装基板,在其表面上装载有半导体芯片;母板,将所述封装基板的背面焊接在该母板的表面上;第一加强件,配备在所述母板背面并与所述封装基板夹持该母板,该第一加强件由连结部件固定在该母板上,所述封装安装模块的特征在于,
所述第一加强件的远离该母板的那侧表面和其与所述母板背面相连接的那侧表面相比具有较大的热膨胀率。
这里,在本发明的封装安装模块中,上述第一加强件也可以具有由第一部件和第二部件组成的双金属结构,所述第一部件与所述母板背面相连接,所述第二部件与该第一部件的、远离母板的那侧表面相连接,并具有大于该第一部件的热膨胀率。
另外,在上述本发明的封装安装模块中,上述连结部件通常采用螺钉,上述封装基板通过配置在该封装基板背面的焊球的熔融和固定而焊接在所述母板表面上。
根据本发明的封装安装模块,由于上述第一加强件通过例如采用双金属结构等,其远离母板的那侧表面具有大于与母板背面相连接的那侧表面的热膨胀率,因此当母板弯曲时第一加强件也会弯曲以与母板的弯曲相一致,因此第一加强件支承母板而不会强制矫正母板的弯曲,可以抑制在封装基板背面和母板表面之间的焊接部上产生的应力,能够确保该焊接部的焊接的高可靠性。
另外,在上述本发明的封装安装模块中,优选具有第二加强件,该第二加强件以围绕装载在所述封装基板表面上的半导体芯片的方式在与该封装基板表面相连接的状态下被固定,并且,该第二加强件远离该封装基板的那侧表面和其与该封装基板表面相连接的那侧表面相比具有较小的热膨胀率。
这里,所述第二加强件具有由第一部件和第二部件组成的双金属结构,所述第一部件与封装基板表面相连接,所述第二部件与该第一部件的、远离封装基板的那侧表面相连接,并具有小于该第一部件的热膨胀率。
如上所述,当具备例如具有双金属结构的、远离封装基板的那侧表面的热膨胀率比与封装基板表面相连接的那侧表面小的第二加强件时,可使该第二加强件效仿封装基板在各温度阶段的的弯曲而弯曲,从而在用第二加强件支承封装基板的同时,能够抑制在半导体芯片和封装基板之间的焊接部产生应力。
另外,本发明的封装基板模块具有:封装基板,在其表面上装载有半导体芯片;加强件,以围绕所述半导体芯片方式在与该封装基板表面相连接的状态下被固定,所述封装基板模块的特征在于,所述加强件的远离该封装基板的那侧表面和其与所述封装基板表面相连接的那侧表面相比具有较小的热膨胀率。
这里,在上述本发明的封装基板模块中,上述加强件也可以具有由第一部件和第二部件组成的双金属结构,所述第一部件与所述封装基板表面相连接,所述第二部件与该第一部件的、远离该封装基板的那侧表面相连接,并具有小于该第一部件的热膨胀率。
根据本发明的封装基板模块,与上述相同,该加强件可效仿封装基板在各温度阶段的弯曲而弯曲,从而在用加强件支承封装基板的同时,能够抑制在半导体芯片和封装基板之间的焊接部产生应力。
如上所述,根据本发明,由于具有根据温度而弯曲的结构的加强件,该加强件可担负起支承基板(封装基板或母板)的作用,同时能够抑制在焊接部产生应力,从而可以确保焊接的高可靠性。
附图说明
图1是表示作为本发明的一个实施方式的封装基板模块的剖面结构图;
图2是表示作为本发明的一个实施方式的封装安装模块的剖面结构图;
图3是示出图2所示的封装安装模块的母板根据温度变化而弯曲的状态的示意图;
图4为表示现有封装基板模块的剖面结构图;
图5为表示现有封装安装模块的剖面结构图;
图6是图5所示的现有封装安装模块的问题的说明图。
具体实施方式
以下,对本发明的实施方式进行说明。
图1是表示作为本发明的一个实施方式的封装基板模块的剖面结构图。
在该图1中,对于与作为现有封装基板模块附图的图4所示的各部件相同的部件,标记与图4中所标记的符号相同的符号。
在该图1所示的封装基板模块100中,通过由焊球13的熔融、固定而进行的焊接,将LSI芯片12装载在封装基板11的表面上,并且,还具有加强件140,该加强件140以围绕该LSI芯片12的方式在与封装基板11的表面相连接的状态下进行固定。该加强件140具有将第一部件141和第二部件142粘贴形成的结构,所述第一部件141与封装基板11的表面相连接,所述第二部件142与该第一部件141的、脱离封装基板11的一侧的表面相连接。这里,第二部件142具有小于第一部件141的热膨胀率,因此,在温度下降时,第二部件142的收缩小于第一部件,在从焊球13的熔融温度至常温的各温度阶段中,在支承封装基板11的同时效仿封装基板11的弯曲。因而,可以大大减少在LSI芯片12和封装基板11之间的焊接部上产生的应力。
图2是表示作为本发明的一个实施方式的封装安装模块的剖面结构图。
这里,对图1所示的封装基板模块标记相同的符号,并省略重复说明。
另外,图3是示出图2所示的封装安装模块的母板根据温度变化而弯曲的状态的示意图。
在图2所示的封装安装模块200中,通过图1所示的封装基板11的背面的焊球15的熔融、固定来进行封装基板11的焊接,从而将该图1所示的整个封装基板模块100装载在母板21的表面上。另外,在母板21的背面的、与封装基板11夹持该母板21的位置上配备有加强件220。该加强件220具有比封装基板11的面积大的面积,在将封装基板11、母板21以及加强件220重叠投影来进行观察时,在处于封装基板11外围的、加强件220的周边部上,在多处通过螺栓23对母板21和加强件22进行固定。
这里,该加强件220具有将第一部件221和第二部件222粘贴而成的结构,所述第一部件221与母板21的背面相连接,所述第二部件222与该第一部件221的、脱离母板21的一侧的表面相连接。该第二部件222具有大于第一部件221的热膨胀率,因此,在温度下降时,第二部件222的收缩大于第一部件,在从焊球15的熔融温度至常温的各温度阶段中,如图3所示,在支承母板21的同时效仿母板21的弯曲。因而,可以大大降低在封装基板11和母板21之间的焊接部上产生的应力。
如上所述,根据上述实施方式,加强件140、220允许封装基板11和母板21的弯曲(翘曲),大大减少了焊接部的应力,从而非常有助于提高焊接部的可靠性。
Claims (8)
1.一种封装安装模块,具有:
封装基板,在该封装基板的表面上装载有半导体芯片;
母板,在该母板的表面上焊接了所述封装基板的背面;
第一加强件,配备在所述母板背面并与所述封装基板夹持所述母板,该第一加强件由连结部件固定在所述母板上;
所述封装安装模块的特征在于,
所述第一加强件的远离所述母板的那侧表面和其与所述母板背面相连接的那侧表面相比具有较大的热膨胀率。
2.如权利要求1所述的封装安装模块,其特征在于,
所述第一加强件具有由第一部件和第二部件组成的双金属结构,所述第一部件与所述母板背面相连接,所述第二部件与该第一部件的、远离该母板的那侧表面相连接,并具有大于该第一部件的热膨胀率。
3.如权利要求1所述的封装安装模块,其特征在于,所述连结部件为螺钉。
4.如权利要求1所述的封装安装模块,其特征在于,
所述封装基板通过配置在该封装基板背面的焊球的熔融和固定而焊接在所述母板表面上。
5.如权利要求1所述的封装安装模块,其特征在于,
具有第二加强件,该第二加强件以围绕装载在所述封装基板表面上的半导体芯片的方式在与该封装基板表面相连接的状态下被固定,并且,该第二加强件的远离所述封装基板的那侧表面和其与所述封装基板表面相连接的那侧表面相比具有较小的热膨胀率。
6.如权利要求5所述的封装安装模块,其特征在于,
所述第二加强件具有由第一部件和第二部件组成的双金属结构,所述第一部件与所述封装基板表面相连接,所述第二部件与所述第一部件的、远离所述封装基板的那侧表面相连接,并具有大于所述第一部件的热膨胀率。
7.一种封装基板模块,具有:
封装基板,在该封装基板的表面上装载有半导体芯片;
加强件,以围绕所述半导体芯片的方式在与所述封装基板表面相连接的状态下被固定;
所述封装基板模块的特征在于,
所述加强件的远离所述封装基板的那侧表面和其与所述封装基板表面相连接的那侧表面相比具有较小的热膨胀率。
8.如权利要求7所述的封装基板模块,其特征在于,
所述加强件具有由第一部件和第二部件组成的双金属结构,所述第一部件与所述封装基板表面相连接,所述第二部件与所述第一部件的、脱离所述封装基板的那侧表面相连接,并具有大于所述第一部件的热膨胀率。
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102064137A (zh) * | 2010-12-06 | 2011-05-18 | 日月光半导体制造股份有限公司 | 具有金属边框的半导体结构 |
CN107210282A (zh) * | 2015-03-03 | 2017-09-26 | 英特尔公司 | 包括多层加强件的电子封装件 |
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US11102384B2 (en) | 2016-12-27 | 2021-08-24 | Huawei Technologies Co., Ltd. | Camera substrate assembly, camera module, and terminal device |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP2144483A4 (en) * | 2007-03-29 | 2011-06-08 | Fujitsu Ltd | DECAY-REDUCING FIXATION STRUCTURE |
CN101944489B (zh) * | 2009-07-07 | 2012-06-20 | 株式会社村田制作所 | 复合基板的制造方法 |
US8609465B2 (en) * | 2009-10-09 | 2013-12-17 | Toyota Jidosha Kabushiki Kaisha | Semiconductor device manufacturing method |
JP2012104660A (ja) * | 2010-11-10 | 2012-05-31 | Fujitsu Optical Components Ltd | 電子装置、デバイスの実装方法、および光通信装置 |
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US10651127B2 (en) | 2017-09-29 | 2020-05-12 | Intel Corporation | Ring-in-ring configurable-capacitance stiffeners and methods of assembling same |
TWI728922B (zh) | 2020-10-07 | 2021-05-21 | 頎邦科技股份有限公司 | 捲帶封裝的儲放構造及其載盤 |
WO2023127725A1 (ja) * | 2021-12-28 | 2023-07-06 | 京セラ株式会社 | スティフナ付き配線基板 |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4322156A (en) * | 1979-08-14 | 1982-03-30 | Tokyo Shibaura Denki Kabushiki Kaisha | Charging apparatus for copying machine |
JPS5627166A (en) * | 1979-08-14 | 1981-03-16 | Toshiba Corp | Copying apparatus |
JPH02116197A (ja) | 1988-10-26 | 1990-04-27 | Hitachi Ltd | 半導体実装用多層配線基板 |
US5528462A (en) * | 1994-06-29 | 1996-06-18 | Pendse; Rajendra D. | Direct chip connection using demountable flip chip package |
JPH08222658A (ja) * | 1995-02-17 | 1996-08-30 | Sumitomo Electric Ind Ltd | 半導体素子用パッケージ及びその製造方法 |
JPH10243326A (ja) | 1997-02-27 | 1998-09-11 | Sony Corp | 送出システム |
JP3537620B2 (ja) * | 1997-02-27 | 2004-06-14 | 京セラ株式会社 | 多層配線基板 |
JPH11265967A (ja) * | 1998-03-17 | 1999-09-28 | Nec Corp | Lsi実装基板の構造及びその製造方法 |
JP3161423B2 (ja) * | 1998-08-11 | 2001-04-25 | 日本電気株式会社 | Lsiの実装構造 |
JP3062192B1 (ja) * | 1999-09-01 | 2000-07-10 | 松下電子工業株式会社 | リ―ドフレ―ムとそれを用いた樹脂封止型半導体装置の製造方法 |
JP2001320145A (ja) * | 2000-05-10 | 2001-11-16 | Nec Corp | 電子部品の実装構造および実装方法 |
JP2002100886A (ja) * | 2000-09-25 | 2002-04-05 | Fujitsu Ltd | プリント板ユニット |
US7132744B2 (en) * | 2000-12-22 | 2006-11-07 | Broadcom Corporation | Enhanced die-up ball grid array packages and method for making the same |
JP2002263972A (ja) | 2001-03-13 | 2002-09-17 | Micron Seimitsu Kk | 工作機械ベッド構造、および工作機械ベッドの構成方法 |
JP2003258153A (ja) * | 2002-03-05 | 2003-09-12 | Nec Corp | 半導体パッケージの実装構造 |
JP3971296B2 (ja) * | 2002-12-27 | 2007-09-05 | Dowaホールディングス株式会社 | 金属−セラミックス接合基板およびその製造方法 |
US6992899B2 (en) * | 2003-03-21 | 2006-01-31 | Intel Corporation | Power delivery apparatus, systems, and methods |
US6743026B1 (en) * | 2003-04-15 | 2004-06-01 | International Business Machines Corporation | Printed wiring board thickness control for compression connectors used in electronic packaging |
-
2005
- 2005-02-15 JP JP2007503509A patent/JP4500348B2/ja not_active Expired - Fee Related
- 2005-02-15 WO PCT/JP2005/002274 patent/WO2006087769A1/ja not_active Application Discontinuation
- 2005-02-15 CN CN2005800483699A patent/CN101124857B/zh not_active Expired - Fee Related
-
2007
- 2007-08-14 US US11/838,431 patent/US7919856B2/en not_active Expired - Fee Related
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
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CN102064137A (zh) * | 2010-12-06 | 2011-05-18 | 日月光半导体制造股份有限公司 | 具有金属边框的半导体结构 |
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TWI614851B (zh) * | 2015-03-03 | 2018-02-11 | 英特爾公司 | 包括多層加強件之電子封裝體 |
US10535615B2 (en) | 2015-03-03 | 2020-01-14 | Intel Corporation | Electronic package that includes multi-layer stiffener |
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JPWO2006087769A1 (ja) | 2008-07-03 |
WO2006087769A1 (ja) | 2006-08-24 |
US20070278647A1 (en) | 2007-12-06 |
US7919856B2 (en) | 2011-04-05 |
CN101124857B (zh) | 2011-11-16 |
JP4500348B2 (ja) | 2010-07-14 |
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