JPWO2006087769A1 - パッケージ実装モジュールおよびパッケージ基板モジュール - Google Patents
パッケージ実装モジュールおよびパッケージ基板モジュール Download PDFInfo
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- JPWO2006087769A1 JPWO2006087769A1 JP2007503509A JP2007503509A JPWO2006087769A1 JP WO2006087769 A1 JPWO2006087769 A1 JP WO2006087769A1 JP 2007503509 A JP2007503509 A JP 2007503509A JP 2007503509 A JP2007503509 A JP 2007503509A JP WO2006087769 A1 JPWO2006087769 A1 JP WO2006087769A1
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- Prior art keywords
- package substrate
- package
- stiffener
- contact
- mother board
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/812—Applying energy for connecting
- H01L2224/8121—Applying energy for connecting using a reflow oven
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
- H01L2224/81815—Reflow soldering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0338—Layered conductor, e.g. layered metal substrate, layered finish layer, layered thin film adhesion layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/06—Thermal details
- H05K2201/068—Thermal details wherein the coefficient of thermal expansion is important
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10431—Details of mounted components
- H05K2201/10598—Means for fastening a component, a casing or a heat sink whereby a pressure is exerted on the component towards the PCB
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10734—Ball grid array [BGA]; Bump grid array
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/20—Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
- H05K2201/2009—Reinforced areas, e.g. for a specific part of a flexible printed circuit
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0058—Laminating printed circuit boards onto other substrates, e.g. metallic substrates
- H05K3/0061—Laminating printed circuit boards onto other substrates, e.g. metallic substrates onto a metallic substrate, e.g. a heat sink
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Structure Of Printed Boards (AREA)
- Combinations Of Printed Boards (AREA)
- Wire Bonding (AREA)
Abstract
Description
表面に半導体チップが搭載されたパッケージ基板と、
表面にパッケージ基板裏面がハンダ接合されたマザーボードと、
マザーボード裏面の、そのマザーボードをパッケージ基板とで挟む位置に配備された、そのマザーボードに締結部品で固定された第1のスティフナとを備え、
上記第1のスティフナは、マザーボード裏面に接する側の面よりもマザーボードから離れた側の面が大きな熱膨張率を有するものであることを特徴とする。
表面に半導体チップが搭載されたパッケージ基板と、
その半導体チップを取り巻くようにパッケージ基板表面に接した状態に固定されたスティフナとを備え、
そのスティフナは、パッケージ基板表面に接する側の面よりもパッケージ基板から離れた側の面が小さな熱膨張率を有するものであることを特徴とする。
Claims (8)
- 表面に半導体チップが搭載されたパッケージ基板と、
表面に前記パッケージ基板裏面がハンダ接合されたマザーボードと、
前記マザーボード裏面の、該マザーボードを前記パッケージ基板とで挟む位置に配備された、該マザーボードに締結部品で固定された第1のスティフナとを備え、
前記第1のスティフナは、前記マザーボード裏面に接する側の面よりも該マザーボードから離れた側の面が大きな熱膨張率を有するものであることを特徴とするパッケージ実装モジュール。 - 前記第1のスティフナが、前記マザーボード裏面に接する第1の部材と、該第1の部材の、該マザーボードから離れた側の面に接する、該第1の部材よりも大きな熱膨張率を有する第2の部材とからなるバイメタル構造を有するものであることを特徴とする請求項1記載のパッケージ実装モジュール。
- 前記締結部品がネジであることを特徴とする請求項1記載のパッケージ実装モジュール。
- 前記パッケージ基板は、該パッケージ基板裏面に配置されたハンダボールの溶融および固着により前記マザーボード表面にハンダ接合されたものであることを特徴とする請求項1記載のパッケージ実装モジュール。
- 前記パッケージ基板表面に搭載された半導体チップを取り巻くように、該パッケージ基板表面に接した状態に固定された第2のスティフナを備え、該第2のスティフナは、該パッケージ基板表面に接する側の面よりも該パッケージ基板から離れた側の面が小さな熱膨張率を有するものであることを特徴とする請求項1記載のパッケージ実装モジュール。
- 前記第2のスティフナが、前記パッケージ基板表面に接する第1の部材と、該第1の部材の、該パッケージ基板から離れた側の面に接する、該第1の部材よりも大きな熱膨張率を有する第2の部材とからなるバイメタル構造を有するものであることを特徴とする請求項5記載のパッケージ実装モジュール。
- 表面に半導体チップが搭載されたパッケージ基板と、
前記半導体チップを取り巻くように前記パッケージ基板表面に接した状態に固定されたスティフナとを備え、
前記スティフナは、前記パッケージ基板表面に接する側の面よりも該パッケージ基板から離れた側の面が小さな熱膨張率を有するものであることを特徴とするパッケージ基板モジュール。 - 前記スティフナが、前記パッケージ基板表面に接する第1の部材と、該第1の部材の、該パッケージ基板から離れた側の面に接する、該第1の部材よりも大きな熱膨張率を有する第2の部材とからなるバイメタル構造を有するものであることを特徴とする請求項7記載のパッケージ基板モジュール。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2005/002274 WO2006087769A1 (ja) | 2005-02-15 | 2005-02-15 | パッケージ実装モジュールおよびパッケージ基板モジュール |
Publications (2)
Publication Number | Publication Date |
---|---|
JPWO2006087769A1 true JPWO2006087769A1 (ja) | 2008-07-03 |
JP4500348B2 JP4500348B2 (ja) | 2010-07-14 |
Family
ID=36916185
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007503509A Expired - Fee Related JP4500348B2 (ja) | 2005-02-15 | 2005-02-15 | パッケージ実装モジュールおよびパッケージ基板モジュール |
Country Status (4)
Country | Link |
---|---|
US (1) | US7919856B2 (ja) |
JP (1) | JP4500348B2 (ja) |
CN (1) | CN101124857B (ja) |
WO (1) | WO2006087769A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012104660A (ja) * | 2010-11-10 | 2012-05-31 | Fujitsu Optical Components Ltd | 電子装置、デバイスの実装方法、および光通信装置 |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP2144483A4 (en) | 2007-03-29 | 2011-06-08 | Fujitsu Ltd | DECAY-REDUCING FIXATION STRUCTURE |
CN101944489B (zh) * | 2009-07-07 | 2012-06-20 | 株式会社村田制作所 | 复合基板的制造方法 |
WO2011042982A1 (ja) * | 2009-10-09 | 2011-04-14 | トヨタ自動車株式会社 | 半導体装置の製造方法 |
CN102064137A (zh) * | 2010-12-06 | 2011-05-18 | 日月光半导体制造股份有限公司 | 具有金属边框的半导体结构 |
CN107210282B (zh) * | 2015-03-03 | 2021-02-26 | 英特尔公司 | 包括多层加强件的电子封装件 |
US20170170087A1 (en) * | 2015-12-14 | 2017-06-15 | Intel Corporation | Electronic package that includes multiple supports |
US9799610B2 (en) * | 2015-12-18 | 2017-10-24 | Intel Corporation | Plurality of stiffeners with thickness variation |
CN108886566B (zh) | 2016-12-27 | 2021-10-22 | 华为技术有限公司 | 一种摄像头基板组件、摄像头模组及终端设备 |
US10157860B2 (en) | 2016-12-28 | 2018-12-18 | Intel Corporation | Component stiffener architectures for microelectronic package structures |
US10651127B2 (en) | 2017-09-29 | 2020-05-12 | Intel Corporation | Ring-in-ring configurable-capacitance stiffeners and methods of assembling same |
TWI728922B (zh) | 2020-10-07 | 2021-05-21 | 頎邦科技股份有限公司 | 捲帶封裝的儲放構造及其載盤 |
CN112512206A (zh) * | 2020-12-23 | 2021-03-16 | 昆山丘钛光电科技有限公司 | 一种补强温度变形的印刷电路板以及摄像头模组 |
WO2023127725A1 (ja) * | 2021-12-28 | 2023-07-06 | 京セラ株式会社 | スティフナ付き配線基板 |
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2005
- 2005-02-15 CN CN2005800483699A patent/CN101124857B/zh not_active Expired - Fee Related
- 2005-02-15 JP JP2007503509A patent/JP4500348B2/ja not_active Expired - Fee Related
- 2005-02-15 WO PCT/JP2005/002274 patent/WO2006087769A1/ja not_active Application Discontinuation
-
2007
- 2007-08-14 US US11/838,431 patent/US7919856B2/en not_active Expired - Fee Related
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JPS5627166A (en) * | 1979-08-14 | 1981-03-16 | Toshiba Corp | Copying apparatus |
JPH0845985A (ja) * | 1994-06-29 | 1996-02-16 | Hewlett Packard Co <Hp> | 取り外し可能なフリップチップパッケージを用いた直接チップ接続 |
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JP2004214284A (ja) * | 2002-12-27 | 2004-07-29 | Dowa Mining Co Ltd | 金属−セラミックス接合基板およびその製造方法 |
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Cited By (1)
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JP2012104660A (ja) * | 2010-11-10 | 2012-05-31 | Fujitsu Optical Components Ltd | 電子装置、デバイスの実装方法、および光通信装置 |
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US20070278647A1 (en) | 2007-12-06 |
CN101124857B (zh) | 2011-11-16 |
WO2006087769A1 (ja) | 2006-08-24 |
CN101124857A (zh) | 2008-02-13 |
US7919856B2 (en) | 2011-04-05 |
JP4500348B2 (ja) | 2010-07-14 |
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