CN101061587B - 应变全耗尽绝缘层上覆硅半导体装置及其制造方法 - Google Patents

应变全耗尽绝缘层上覆硅半导体装置及其制造方法 Download PDF

Info

Publication number
CN101061587B
CN101061587B CN200580035899XA CN200580035899A CN101061587B CN 101061587 B CN101061587 B CN 101061587B CN 200580035899X A CN200580035899X A CN 200580035899XA CN 200580035899 A CN200580035899 A CN 200580035899A CN 101061587 B CN101061587 B CN 101061587B
Authority
CN
China
Prior art keywords
drain
grid
interval body
outside
concave type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN200580035899XA
Other languages
English (en)
Chinese (zh)
Other versions
CN101061587A (zh
Inventor
相奇
N·苏巴
W·P·麦斯扎拉
Z·克里沃卡皮克
M-R·林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries Inc
Original Assignee
GlobalFoundries Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by GlobalFoundries Inc filed Critical GlobalFoundries Inc
Publication of CN101061587A publication Critical patent/CN101061587A/zh
Application granted granted Critical
Publication of CN101061587B publication Critical patent/CN101061587B/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01—Manufacture or treatment
    • H10D62/021—Forming source or drain recesses by etching e.g. recessing by etching and then refilling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6727—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device having source or drain regions connected to bulk conducting substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/794—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions comprising conductive materials, e.g. silicided source, drain or gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/797—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in source or drain regions, e.g. SiGe source or drain
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/938—Lattice strain control or utilization

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
CN200580035899XA 2004-11-10 2005-10-12 应变全耗尽绝缘层上覆硅半导体装置及其制造方法 Expired - Fee Related CN101061587B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/986,399 2004-11-10
US10/986,399 US7306997B2 (en) 2004-11-10 2004-11-10 Strained fully depleted silicon on insulator semiconductor device and manufacturing method therefor
PCT/US2005/036894 WO2006052379A1 (en) 2004-11-10 2005-10-12 Strained fully depleted silicon on insulator semiconductor device and manufacturing method therefor

Publications (2)

Publication Number Publication Date
CN101061587A CN101061587A (zh) 2007-10-24
CN101061587B true CN101061587B (zh) 2011-01-12

Family

ID=35658988

Family Applications (1)

Application Number Title Priority Date Filing Date
CN200580035899XA Expired - Fee Related CN101061587B (zh) 2004-11-10 2005-10-12 应变全耗尽绝缘层上覆硅半导体装置及其制造方法

Country Status (7)

Country Link
US (2) US7306997B2 (enExample)
EP (1) EP1815531A1 (enExample)
JP (1) JP2008520097A (enExample)
KR (1) KR101122753B1 (enExample)
CN (1) CN101061587B (enExample)
TW (1) TWI380373B (enExample)
WO (1) WO2006052379A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102122669A (zh) * 2011-01-27 2011-07-13 上海宏力半导体制造有限公司 晶体管及其制作方法

Families Citing this family (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2872626B1 (fr) * 2004-07-05 2008-05-02 Commissariat Energie Atomique Procede pour contraindre un motif mince
JP2006165335A (ja) * 2004-12-08 2006-06-22 Toshiba Corp 半導体装置
US7091071B2 (en) * 2005-01-03 2006-08-15 Freescale Semiconductor, Inc. Semiconductor fabrication process including recessed source/drain regions in an SOI wafer
US7446350B2 (en) * 2005-05-10 2008-11-04 International Business Machine Corporation Embedded silicon germanium using a double buried oxide silicon-on-insulator wafer
JP2006332243A (ja) * 2005-05-25 2006-12-07 Toshiba Corp 半導体装置及びその製造方法
US7384851B2 (en) * 2005-07-15 2008-06-10 International Business Machines Corporation Buried stress isolation for high-performance CMOS technology
DE102005052055B3 (de) 2005-10-31 2007-04-26 Advanced Micro Devices, Inc., Sunnyvale Eingebettete Verformungsschicht in dünnen SOI-Transistoren und Verfahren zur Herstellung desselben
GB2445511B (en) * 2005-10-31 2009-04-08 Advanced Micro Devices Inc An embedded strain layer in thin soi transistors and a method of forming the same
US7422950B2 (en) * 2005-12-14 2008-09-09 Intel Corporation Strained silicon MOS device with box layer between the source and drain regions
US7473593B2 (en) * 2006-01-11 2009-01-06 International Business Machines Corporation Semiconductor transistors with expanded top portions of gates
US7569434B2 (en) * 2006-01-19 2009-08-04 International Business Machines Corporation PFETs and methods of manufacturing the same
EP1833094B1 (en) * 2006-03-06 2011-02-02 STMicroelectronics (Crolles 2) SAS Formation of shallow SiGe conduction channel
US7613369B2 (en) * 2006-04-13 2009-11-03 Luxtera, Inc. Design of CMOS integrated germanium photodiodes
JP5182703B2 (ja) * 2006-06-08 2013-04-17 日本電気株式会社 半導体装置
US8154051B2 (en) * 2006-08-29 2012-04-10 Taiwan Semiconductor Manufacturing Co., Ltd. MOS transistor with in-channel and laterally positioned stressors
JP2008071851A (ja) * 2006-09-13 2008-03-27 Sony Corp 半導体装置および半導体装置の製造方法
JP2008153515A (ja) * 2006-12-19 2008-07-03 Fujitsu Ltd Ｍｏｓトランジスタ、そのｍｏｓトランジスタの製造方法、そのｍｏｓトランジスタを利用したｃｍｏｓ型半導体装置、及び、そのｃｍｏｓ型半導体装置を利用した半導体装置
US20080157118A1 (en) * 2006-12-29 2008-07-03 Chartered Semiconductor Manufacturing Ltd. Integrated circuit system employing strained technology
US9640666B2 (en) * 2007-07-23 2017-05-02 GlobalFoundries, Inc. Integrated circuit employing variable thickness film
JP2009212413A (ja) * 2008-03-06 2009-09-17 Renesas Technology Corp 半導体装置及び半導体装置の製造方法
US8421050B2 (en) * 2008-10-30 2013-04-16 Sandisk 3D Llc Electronic devices including carbon nano-tube films having carbon-based liners, and methods of forming the same
KR101592505B1 (ko) * 2009-02-16 2016-02-05 삼성전자주식회사 반도체 메모리 소자 및 이의 제조 방법
US8106456B2 (en) * 2009-07-29 2012-01-31 International Business Machines Corporation SOI transistors having an embedded extension region to improve extension resistance and channel strain characteristics
US7994062B2 (en) * 2009-10-30 2011-08-09 Sachem, Inc. Selective silicon etch process
CN102299092B (zh) * 2010-06-22 2013-10-30 中国科学院微电子研究所 一种半导体器件及其形成方法
CN102376769B (zh) * 2010-08-18 2013-06-26 中国科学院微电子研究所 超薄体晶体管及其制作方法
CN102487018B (zh) * 2010-12-03 2014-03-12 中芯国际集成电路制造(北京)有限公司 Mos晶体管及其形成方法
US8455308B2 (en) 2011-03-16 2013-06-04 International Business Machines Corporation Fully-depleted SON
US9184214B2 (en) * 2011-04-11 2015-11-10 Globalfoundries Inc. Semiconductor device exhibiting reduced parasitics and method for making same
US20120326230A1 (en) * 2011-06-22 2012-12-27 International Business Machines Corporation Silicon on insulator complementary metal oxide semiconductor with an isolation formed at low temperature
US20140183618A1 (en) * 2011-08-05 2014-07-03 X-Fab Semiconductor Foundries Ag Semiconductor device
US9136158B2 (en) * 2012-03-09 2015-09-15 Taiwan Semiconductor Manufacturing Company, Ltd. Lateral MOSFET with dielectric isolation trench
US8664050B2 (en) 2012-03-20 2014-03-04 International Business Machines Corporation Structure and method to improve ETSOI MOSFETS with back gate
CN102931092A (zh) * 2012-10-26 2013-02-13 哈尔滨工程大学 一种自对准soi fd mosfet形成方法
CN103779279B (zh) * 2012-10-26 2017-09-01 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法
US9525027B2 (en) * 2014-03-13 2016-12-20 Globalfoundries Inc. Lateral bipolar junction transistor having graded SiGe base
FR3025941A1 (fr) * 2014-09-17 2016-03-18 Commissariat Energie Atomique Transistor mos a resistance et capacites parasites reduites
CN105632909B (zh) * 2014-11-07 2019-02-01 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法、电子装置
US9281305B1 (en) 2014-12-05 2016-03-08 National Applied Research Laboratories Transistor device structure
CN105742248A (zh) * 2014-12-09 2016-07-06 中芯国际集成电路制造(上海)有限公司 半导体结构的形成方法
US20230292524A1 (en) * 2022-02-02 2023-09-14 Taiwan Semiconductor Manufacturing Company, Ltd. Ferroelectric memory device with relaxation layers
US12166729B2 (en) * 2022-02-18 2024-12-10 Psemi Corporation LNA with Tx harmonic filter
US12489013B2 (en) 2022-09-27 2025-12-02 Globalfoundries U.S. Inc. Semiconductor-on-insulator field-effect transistors including stress-inducing components

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6621131B2 (en) * 2001-11-01 2003-09-16 Intel Corporation Semiconductor transistor having a stressed channel

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2636786B2 (ja) * 1995-03-20 1997-07-30 日本電気株式会社 半導体装置の製造方法
DE19533313A1 (de) * 1995-09-08 1997-03-13 Max Planck Gesellschaft Halbleiterstruktur für einen Transistor
JP3373772B2 (ja) * 1997-11-19 2003-02-04 株式会社東芝 半導体装置
US6303448B1 (en) * 1998-11-05 2001-10-16 Taiwan Semiconductor Manufacturing Company Method for fabricating raised source/drain structures
US6339244B1 (en) * 2000-02-22 2002-01-15 Advanced Micro Devices, Inc. Fully depleted silicon on insulator semiconductor device and manufacturing method therefor
US6323104B1 (en) * 2000-03-01 2001-11-27 Micron Technology, Inc. Method of forming an integrated circuitry isolation trench, method of forming integrated circuitry, and integrated circuitry
JP2002083972A (ja) * 2000-09-11 2002-03-22 Hitachi Ltd 半導体集積回路装置
US6649480B2 (en) * 2000-12-04 2003-11-18 Amberwave Systems Corporation Method of fabricating CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
JP2002237590A (ja) * 2001-02-09 2002-08-23 Univ Tohoku Ｍｏｓ型電界効果トランジスタ
US6558994B2 (en) * 2001-03-01 2003-05-06 Chartered Semiconductors Maufacturing Ltd. Dual silicon-on-insulator device wafer die
US6660598B2 (en) * 2002-02-26 2003-12-09 International Business Machines Corporation Method of forming a fully-depleted SOI ( silicon-on-insulator) MOSFET having a thinned channel region
JP4173672B2 (ja) * 2002-03-19 2008-10-29 株式会社ルネサステクノロジ 半導体装置及びその製造方法
US6605498B1 (en) * 2002-03-29 2003-08-12 Intel Corporation Semiconductor transistor having a backfilled channel material
FR2838237B1 (fr) * 2002-04-03 2005-02-25 St Microelectronics Sa Procede de fabrication d'un transistor a effet de champ a grille isolee a canal contraint et circuit integre comprenant un tel transistor
US6995430B2 (en) * 2002-06-07 2006-02-07 Amberwave Systems Corporation Strained-semiconductor-on-insulator device structures
KR100416627B1 (ko) * 2002-06-18 2004-01-31 삼성전자주식회사 반도체 장치 및 그의 제조방법
US6680240B1 (en) * 2002-06-25 2004-01-20 Advanced Micro Devices, Inc. Silicon-on-insulator device with strained device film and method for making the same with partial replacement of isolation oxide
US20040033677A1 (en) * 2002-08-14 2004-02-19 Reza Arghavani Method and apparatus to prevent lateral oxidation in a transistor utilizing an ultra thin oxygen-diffusion barrier
JP4546021B2 (ja) * 2002-10-02 2010-09-15 ルネサスエレクトロニクス株式会社 絶縁ゲート型電界効果型トランジスタ及び半導体装置
US6902991B2 (en) * 2002-10-24 2005-06-07 Advanced Micro Devices, Inc. Semiconductor device having a thick strained silicon layer and method of its formation
CN100378901C (zh) 2002-11-25 2008-04-02 国际商业机器公司 应变鳍型场效应晶体管互补金属氧化物半导体器件结构
US6909186B2 (en) * 2003-05-01 2005-06-21 International Business Machines Corporation High performance FET devices and methods therefor
US8097924B2 (en) * 2003-10-31 2012-01-17 Taiwan Semiconductor Manufacturing Company, Ltd. Ultra-shallow junction MOSFET having a high-k gate dielectric and in-situ doped selective epitaxy source/drain extensions and a method of making same
US7037795B1 (en) * 2004-10-15 2006-05-02 Freescale Semiconductor, Inc. Low RC product transistors in SOI semiconductor process

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6621131B2 (en) * 2001-11-01 2003-09-16 Intel Corporation Semiconductor transistor having a stressed channel

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102122669A (zh) * 2011-01-27 2011-07-13 上海宏力半导体制造有限公司 晶体管及其制作方法

Also Published As

Publication number Publication date
TW200620489A (en) 2006-06-16
KR20070084008A (ko) 2007-08-24
US7306997B2 (en) 2007-12-11
JP2008520097A (ja) 2008-06-12
EP1815531A1 (en) 2007-08-08
KR101122753B1 (ko) 2012-03-23
CN101061587A (zh) 2007-10-24
US20080054316A1 (en) 2008-03-06
TWI380373B (en) 2012-12-21
US20060099752A1 (en) 2006-05-11
US8502283B2 (en) 2013-08-06
WO2006052379A1 (en) 2006-05-18

Similar Documents

Publication Publication Date Title
CN101061587B (zh) 应变全耗尽绝缘层上覆硅半导体装置及其制造方法
US10068908B2 (en) Method to form localized relaxed substrate by using condensation
KR101020811B1 (ko) 개선된 캐리어 이동도를 구비한 ｆｉｎｆｅｔ과 그 형성방법
KR100618839B1 (ko) 반도체 소자의 제조 방법
JP4110085B2 (ja) 二重ゲート型電界効果トランジスタの製造方法
US7435639B2 (en) Dual surface SOI by lateral epitaxial overgrowth
US7138302B2 (en) Method of fabricating an integrated circuit channel region
US20150255457A1 (en) Methods and apparatus to form fin structures of different compositions on a same wafer via mandrel and diffusion
US7018882B2 (en) Method to form local “silicon-on-nothing” or “silicon-on-insulator” wafers with tensile-strained silicon
US6864547B2 (en) Semiconductor device having a ghost source/drain region and a method of manufacture therefor
CN100573852C (zh) 在同一芯片上建置全耗尽和部分耗尽晶体管
KR100886708B1 (ko) Ｓｏｉ 소자 및 그의 제조방법
US7135379B2 (en) Isolation trench perimeter implant for threshold voltage control
US7566922B2 (en) Field effect transistor with suitable source, drain and channel materials and integrated circuit comprising same
US8802528B2 (en) Vertical PMOS field effect transistor and manufacturing method thereof
JP2002246601A (ja) 半導体装置及び半導体装置の製造方法
KR100486643B1 (ko) 모스전계효과 트랜지스터의 제조 방법
KR100569708B1 (ko) 반도체 장치 및 그 제조 방법
KR20050050909A (ko) Ｓｏｉ 반도체 소자의 제조 방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
ASS Succession or assignment of patent right

Owner name: GLOBALFOUNDRIES INC.

Free format text: FORMER OWNER: ADVANCED MICRO DEVICES INC.

Effective date: 20100730

C41 Transfer of patent application or patent right or utility model
COR Change of bibliographic data

Free format text: CORRECT: ADDRESS; FROM: CALIFORNIA STATE, USA TO: CAYMAN ISLANDS GRAND CAYMAN ISLAND

TA01 Transfer of patent application right

Effective date of registration: 20100730

Address after: Grand Cayman, Cayman Islands

Applicant after: Globalfoundries Semiconductor Inc.

Address before: American California

Applicant before: Advanced Micro Devices Inc.

C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20110112

Termination date: 20161012