Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/01—Manufacture or treatment
  • H10D62/021—Forming source or drain recesses by etching e.g. recessing by etching and then refilling
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
  • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
  • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/67—Thin-film transistors [TFT]
  • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
  • H10D30/6727—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device having source or drain regions connected to bulk conducting substrates
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/67—Thin-film transistors [TFT]
  • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
  • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
  • H10D30/794—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions comprising conductive materials, e.g. silicided source, drain or gate electrodes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
  • H10D30/797—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in source or drain regions, e.g. SiGe source or drain
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10S438/00—Semiconductor device manufacturing: process
  • Y10S438/938—Lattice strain control or utilization

Definitions

• the present invention relates generally to silicon-on-insulator semiconductor _devices_ and more particularly to fully depleted silicon-on-insulator transistors.
• Integrated circuits are used in everything from airplanes and televisions to wristwatches. Integrated circuits are made in and on silicon wafers by extremely complex systems that require the coordination of hundreds or even thousands of precisely controlled processes to produce a finished semiconductor wafer. Each finished semiconductor wafer has hundreds to tens of thousands of integrated circuits, each wafer worth hundreds or thousands of dollars.
• CMOS complementary metal oxide semiconductor
• CMOS transistor generally consist of a silicon substrate having shallow trench oxide isolation regions cordoning off transistor areas.
• the transistor areas contain polysilicon gates on silicon oxide gates, or gate oxides, over the silicon substrate.
• the silicon substrate on both sides of the polysilicon gate is slightly doped to become conductive. These lightly doped regions of the silicon substrate are referred to as “shallow source/drain”, which are separated by a channel region beneath the polysilicon gate.
• a curved silicon oxide or silicon nitride spacer, referred to as a "sidewall spacer” on the sides of the polysilicon gate allows deposition of additional doping to form more heavily doped regions of the shallow source/drain ("S/D”), which are called "deep S/D".
• S/D shallow source/drain
• a silicon oxide dielectric layer is deposited to cover the polysilicon gate, the curved spacer, and the silicon substrate.
• openings are etched in the silicon oxide dielectric layer to the polysilicon gate and the S/D. The openings are filled with metal to form electrical contacts.
• the contacts are connected to additional levels of wiring in additional levels of dielectric material to the outside of the dielectric material.
• CMOS transistor uses an insulating substrate and is called silicon on insulator ("SOI").
• SOI silicon on insulator
• FETs field effect transistors
• the SOI FETs are manufactured with an insulator, such as silicon dioxide, on a semiconductor substrate, such as silicon.
• the entire FETs, including their source junction, channel, drain junction, gate, ohmic contacts and wiring channels, are formed on silicon islands in the insulator and are insulated from any fixed potential. This results in what is called the "floating body” problem because the potential of the body or channel regions floats and can acquire a potential which can interfere with the proper functioning of the FETs.
• the floating body problem causes high leakage current and parasitic bipolar action since the semiconductor substrate is floating with respect to the channel. This problem has adverse affects on threshold voltage control and circuit operation.
• FDSOI CMOS Another key issue for fabrication of FDSOI CMOS is mechanisms to improve performance.
• One way to improve performance is to introduce tensile strain or compressive strain to the channel. Tensile strain along the direction of current flow increases both electron and hole mobility. On the other hand, compressive strain increases hole mobility but degrades electron mobility. Strain is introduced to the channel through trench isolation fill. However, mesa isolation, where there is no trench etch and fill, is conventionally used for FDSOI CMOS.
• the present invention provides a semiconductor substrate having an insulator thereon with a semiconductor layer on the insulator.
• a deep trench isolation is formed, introducing strain to the semiconductor layer.
• a gate dielectric and a gate are formed on the semiconductor layer.
• a spacer is formed around the gate, and the semiconductor layer and the insulator are removed outside the spacer. Recessed source/drain are formed outside the spacer.
• FIG. 1 is a cross-section of a fully depleted silicon on insulator semiconductor wafer
• FIG. 2 shows the structure of FIG. 1 with a gate formed thereon;
• FIG. 3 shows the structure of FIG. 2 with a liner and spacer deposited thereon;
• FIG. 4 shows the structure of FIG. 3 with recessed source/drain in accordance with an embodiment of the present invention
• FIG. 5 shows the structure of FIG. 4 after silicidation in accordance with an embodiment of the present invention
• FIG. 6 shows the structure of FIG. 5 with a contact etch stop layer in accordance with an alternate embodiment of the present invention.
• FIG. 7 is a flow chart of a method for manufacturing a strained fully depleted silicon on insulator semiconductor device in accordance with the present invention.
• horizontal as used herein is defined as a plane parallel to a substrate or wafer.
• vertical refers to a direction perpendicular to the horizontal as just defined. Terms, such as “on”, “above”, “below”, “bottom”, “top”, “side” (as in “sidewall”), "higher”, “lower”, “over”, and “under”, are defined with respect to the horizontal plane.
• processing includes deposition of material or photoresist, patterning, exposure, development, etching, cleaning, and/or removal of the material or photoresist as required in forming a described structure.
• FDSOI fully depleted silicon on insulator
• Si p-doped silicon
• BOX buried oxide layer
• SiO 2 silicon dioxide
• a deep trench isolation (“DTI") 108 spaced outside recessed source/drain 402 (FIG. 4), has been added to the FDSOI wafer 100.
• the DTI 108 is formed with a deep trench etch that etches through the channel layer 106, the BOX 104, and into the substrate 102. To maintain device isolation, the depth of the DTI must be greater than the recessed source/drain 402 (FIG. 4).
• the resulting deep trench is filled with a dielectric of a material such as SiO 2 .
• FIG. 2 therein is shown the structure of FIG. 1 after conventional deposition, patterning, photolithography, and etching to form a gate dielectric 202 of a material such as SiO 2 , silicon oxynitride ("SiON"), or silicon nitride ("Si 3 N 4 "), and a gate 204 of a material such as polysilicon or amorphous silicon which can be either doped or undoped.
• a gate dielectric 202 of a material such as SiO 2 , silicon oxynitride ("SiON"), or silicon nitride ("Si 3 N 4 ")
• Si 3 N 4 silicon nitride
• a liner 302 of a material such as SiO 2 is deposited on the gate 204, the channel layer 106, and the DTI 108.
• a spacer 304 of a material such as Si 3 N 4 is formed around the gate portion of the liner 302 and in the DTI 108.
• FIG. 4 therein is shown the structure of FIG 3 after processing in accordance with an embodiment of the present invention.
• Recessed source/drain 402 have been added to the FDSOI wafer 100.
• the channel layer 106 has been etched to form a channel 404.
• a suitable process such as etching, is used to penetrate through the channel layer 106 and the BOX 104 between the gate 204 and the DTI 108. It has been discovered that a thin BOX 104 from IOOA - 6O ⁇ A provides an optimal thickness. Selective epitaxial growth (“SEG”) then takes place on the surface of the substrate 102 and the sidewall of the channel 404. This ensures a continuous, high quality Si surface for the SEG of the recessed source/drain 402 even when silicon of the channel layer 106 may be partially or even entirely consumed by previous processes.
• SEG selective epitaxial growth
• the resulting structure retains the advantages of elevated source and drain, such as low parasitic series resistance, while overcoming the problem of SEG on thin silicon. At this stage, performance can be improved through modification of the SEG of the recessed source/drain 402.
• FIG. 5 therein is shown the structure of FIG. 4 after further processing in accordance with an embodiment of the present invention.
• Silicidation takes place on the gate 204 and the source/drain 402 to form a NiSi layer 504.
• the recessed source/drain 402 can be formed in situ during selective epitaxial growth of the recessed source/drain 402 or by ion implantation and rapid thermal anneal.
• the DTI 108 introduces strain to the channel 404 and is preferred for isolation among transistors. Introducing tensile strain or compressive strain to the channels of FDSOI CMOS devices improves performance. Tensile strain along the direction of current flow increases both electron and hole mobility in an
• strain can be further improved in FDSOI PMOS transistors by selective epitaxial growth of silicon germanium (SiGe).
• SiGe of the recessed source/drain 402 effectively induce strain in the channel 404 of a FDSOI PMOS transistor.
• the strain is also more effective because the recessed source/drain 402 are immediately adjacent the channel 404 and allow more strain to be introduced than can be introduced in raised source/drain.
• strain can be further improved in FDSOI NMOS transistors by selective epitaxial growth of silicon carbide (SiC).
• SiC of the recessed source/drain effectively induce strain in the channel 404 of a FDSOI NMOS transistor.
• the strain is also more effective because the recessed source/drain 402 are immediately adjacent the channel 404 and more strain can be introduced than can be introduced in raised source/drain.
• the above strain control can be implemented as an adjunct to the strain control from the DTI 108 or as the primary control where the DTI 108 is formed before the recessed source/drain 402.
• FIG. 6 therein is shown the structure of FIG. 5 after further processing in accordance with an alternate embodiment of the present invention.
• An etch has removed the spacer 304 (FIG. 5) and the dielectric fill of the DTI 108 (FIG. 5), leaving a trench 602.
• a contact etch stop layer 604 is deposited in the trench 602 and over the source/drain 402, the liner 302, and the gate 204.
• the contact etch stop layer 604 in the trench 602 introduces additional strain to the channel 404.
• the method 700 includes providing a semiconductor substrate having an insulator thereon with a semiconductor layer on the insulator in a block 702; forming a gate dielectric and a gate on the semiconductor layer in a block 704; forming a deep trench isolation spaced outside the spacer and introducing strain to the semiconductor layer in a block 706; forming a. spacer around the gate in a block 708; removing the semiconductor layer and the insulator outside the spacer in a block 710; and forming recessed source/drain outside the spacer in a block 712.

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• Insulated Gate Type Field-Effect Transistor (AREA)
• Thin Film Transistor (AREA)

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• 2004
  • 2004-11-10 US US10/986,399 patent/US7306997B2/en not_active Expired - Fee Related
• 2005
  • 2005-10-12 CN CN200580035899XA patent/CN101061587B/zh not_active Expired - Fee Related
  • 2005-10-12 EP EP05812228A patent/EP1815531A1/en not_active Withdrawn
  • 2005-10-12 WO PCT/US2005/036894 patent/WO2006052379A1/en not_active Ceased
  • 2005-10-12 KR KR1020077010284A patent/KR101122753B1/ko not_active Expired - Fee Related
  • 2005-10-12 JP JP2007541196A patent/JP2008520097A/ja active Pending
  • 2005-10-24 TW TW094137086A patent/TWI380373B/zh not_active IP Right Cessation
• 2007
  • 2007-10-29 US US11/926,655 patent/US8502283B2/en active Active

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