CN101055838B - 一种制造一半导体器件的方法 - Google Patents
一种制造一半导体器件的方法 Download PDFInfo
- Publication number
- CN101055838B CN101055838B CN2007101018002A CN200710101800A CN101055838B CN 101055838 B CN101055838 B CN 101055838B CN 2007101018002 A CN2007101018002 A CN 2007101018002A CN 200710101800 A CN200710101800 A CN 200710101800A CN 101055838 B CN101055838 B CN 101055838B
- Authority
- CN
- China
- Prior art keywords
- gate
- implant
- layer
- dielectric layer
- boron
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
- H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
- H10P32/14—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase
- H10P32/1408—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase from or through or into an external applied layer, e.g. photoresist or nitride layers
- H10P32/141—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase from or through or into an external applied layer, e.g. photoresist or nitride layers the applied layer comprising oxides only
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P10/00—Bonding of wafers, substrates or parts of devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0221—Manufacture or treatment of FETs having insulated gates [IGFET] having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
- H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
- H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
- H10D62/213—Channel regions of field-effect devices
- H10D62/221—Channel regions of field-effect devices of FETs
- H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
- H10D62/299—Channel regions of field-effect devices of FETs of IGFETs having lateral doping variations
- H10D62/307—Channel regions of field-effect devices of FETs of IGFETs having lateral doping variations the doping variations being parallel to the channel lengths
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
- H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
- H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H10D64/01306—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
- H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
- H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H10D64/01322—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor contacting the insulator having a lateral variation in doping, composition or deposition steps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
- H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
- H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H10D64/01324—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T or inverted-T
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
- H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
- H10D64/683—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being parallel to the channel plane
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P30/00—Ion implantation into wafers, substrates or parts of devices
- H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
- H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
- H10P32/17—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material
- H10P32/171—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material being group IV material
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
- H10P32/30—Diffusion for doping of conductive or resistive layers
- H10P32/302—Doping polycrystalline silicon or amorphous silicon layers
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Electrodes Of Semiconductors (AREA)
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US39202302P | 2002-06-26 | 2002-06-26 | |
| US39180202P | 2002-06-26 | 2002-06-26 | |
| US60/392,023 | 2002-06-26 | ||
| US60/391,802 | 2002-06-26 |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB038150255A Division CN100359652C (zh) | 2002-06-26 | 2003-06-18 | 一种制造一半导体器件的方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101055838A CN101055838A (zh) | 2007-10-17 |
| CN101055838B true CN101055838B (zh) | 2011-12-14 |
Family
ID=30003212
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2007101018002A Expired - Fee Related CN101055838B (zh) | 2002-06-26 | 2003-06-18 | 一种制造一半导体器件的方法 |
| CNB038150255A Expired - Fee Related CN100359652C (zh) | 2002-06-26 | 2003-06-18 | 一种制造一半导体器件的方法 |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB038150255A Expired - Fee Related CN100359652C (zh) | 2002-06-26 | 2003-06-18 | 一种制造一半导体器件的方法 |
Country Status (7)
| Country | Link |
|---|---|
| US (2) | US7723233B2 (https=) |
| EP (1) | EP1540720A4 (https=) |
| JP (2) | JP2005531158A (https=) |
| KR (2) | KR100683594B1 (https=) |
| CN (2) | CN101055838B (https=) |
| AU (1) | AU2003261078A1 (https=) |
| WO (1) | WO2004003970A2 (https=) |
Families Citing this family (26)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6686595B2 (en) | 2002-06-26 | 2004-02-03 | Semequip Inc. | Electron impact ion source |
| AU2003261078A1 (en) * | 2002-06-26 | 2004-01-19 | Semequip Inc. | A semiconductor device and method of fabricating a semiconductor device |
| KR100864048B1 (ko) * | 2002-06-26 | 2008-10-17 | 세미이큅, 인코포레이티드 | 이온 소스 |
| JP2005236210A (ja) * | 2004-02-23 | 2005-09-02 | Ricoh Co Ltd | スタンダードセルレイアウト、スタンダードセルライブラリ並びに半導体集積回路及びその設計方法 |
| KR100694660B1 (ko) * | 2006-03-08 | 2007-03-13 | 삼성전자주식회사 | 트랜지스터 및 그 제조 방법 |
| US7435638B2 (en) * | 2006-05-26 | 2008-10-14 | Texas Instruments Incorporated | Dual poly deposition and through gate oxide implants |
| JP4560820B2 (ja) * | 2006-06-20 | 2010-10-13 | エルピーダメモリ株式会社 | 半導体装置の製造方法 |
| CN101197284B (zh) * | 2006-12-05 | 2010-06-02 | 上海华虹Nec电子有限公司 | 高压非对称横向结构扩散型场效应管的制作方法 |
| JPWO2008156182A1 (ja) * | 2007-06-18 | 2010-08-26 | 日本電気株式会社 | 半導体装置及びその製造方法 |
| JP5220549B2 (ja) * | 2008-10-20 | 2013-06-26 | 本田技研工業株式会社 | アウタロータ型多極発電機のステータ構造体 |
| JP2010199520A (ja) * | 2009-02-27 | 2010-09-09 | Renesas Electronics Corp | 半導体レーザ及び半導体レーザの製造方法 |
| JP5714831B2 (ja) * | 2010-03-18 | 2015-05-07 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
| KR101129028B1 (ko) | 2010-03-24 | 2012-03-23 | 주식회사 하이닉스반도체 | 반도체 소자의 패시베이션 어닐 공정 방법 |
| CN101834141B (zh) * | 2010-04-28 | 2015-03-04 | 复旦大学 | 一种不对称型源漏场效应晶体管的制备方法 |
| CN102468147B (zh) * | 2010-11-01 | 2017-11-28 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件的栅极形成方法 |
| US8598025B2 (en) * | 2010-11-15 | 2013-12-03 | Varian Semiconductor Equipment Associates, Inc. | Doping of planar or three-dimensional structures at elevated temperatures |
| KR20120107762A (ko) | 2011-03-22 | 2012-10-04 | 삼성전자주식회사 | 반도체 소자의 제조 방법 |
| US8569158B2 (en) | 2011-03-31 | 2013-10-29 | Tokyo Electron Limited | Method for forming ultra-shallow doping regions by solid phase diffusion |
| US8580664B2 (en) | 2011-03-31 | 2013-11-12 | Tokyo Electron Limited | Method for forming ultra-shallow boron doping regions by solid phase diffusion |
| US9263272B2 (en) | 2012-04-24 | 2016-02-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Gate electrodes with notches and methods for forming the same |
| US9673245B2 (en) | 2012-10-01 | 2017-06-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Implant isolated devices and method for forming the same |
| US9355888B2 (en) | 2012-10-01 | 2016-05-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Implant isolated devices and method for forming the same |
| US20140291761A1 (en) | 2013-03-29 | 2014-10-02 | International Business Machines Corporation | Asymmetric Spacers |
| US9899224B2 (en) | 2015-03-03 | 2018-02-20 | Tokyo Electron Limited | Method of controlling solid phase diffusion of boron dopants to form ultra-shallow doping regions |
| CN109494224B (zh) * | 2017-09-08 | 2020-12-01 | 华邦电子股份有限公司 | 非挥发性存储器装置及其制造方法 |
| KR101938843B1 (ko) | 2018-05-18 | 2019-01-16 | 청오기초건설 주식회사 | 파일 야적 거치대 |
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| JPS4826179B1 (https=) * | 1968-09-30 | 1973-08-07 | ||
| JPS5626145B2 (https=) * | 1973-06-27 | 1981-06-17 | ||
| DE219243T1 (de) | 1985-10-11 | 1987-09-24 | Monolithic Memories, Inc., Santa Clara, Calif. | Verfahren zur herstellung eines bipolaren transistors. |
| JPH01225117A (ja) | 1988-03-04 | 1989-09-08 | Nippon Telegr & Teleph Corp <Ntt> | 半導体装置の製造方法及びその製造装置 |
| JP2889295B2 (ja) | 1989-07-17 | 1999-05-10 | 株式会社東芝 | 半導体装置及びその製造方法 |
| FR2652448B1 (fr) * | 1989-09-28 | 1994-04-29 | Commissariat Energie Atomique | Procede de fabrication d'un circuit integre mis haute tension. |
| JPH0410620A (ja) | 1990-04-27 | 1992-01-14 | Sony Corp | 半導体装置の製造方法 |
| JPH04112544A (ja) | 1990-08-31 | 1992-04-14 | Sanyo Electric Co Ltd | 半導体装置およびその製造方法 |
| JP3129774B2 (ja) | 1991-07-31 | 2001-01-31 | 日本電産コパル株式会社 | 発光装置 |
| JP2652108B2 (ja) | 1991-09-05 | 1997-09-10 | 三菱電機株式会社 | 電界効果トランジスタおよびその製造方法 |
| JP2702338B2 (ja) * | 1991-10-14 | 1998-01-21 | 三菱電機株式会社 | 半導体装置、及びその製造方法 |
| JP2707977B2 (ja) * | 1994-09-01 | 1998-02-04 | 日本電気株式会社 | Mos型半導体装置およびその製造方法 |
| KR0147870B1 (ko) * | 1994-10-24 | 1998-11-02 | 문정환 | 반도체 소자의 콘택 전도층 형성방법 |
| US5688706A (en) | 1996-08-01 | 1997-11-18 | Vanguard International Semiconductor Corporation | Method for fabricating a MOSFET device, with local channel doping, self aligned to a selectively deposited tungsten gate |
| US5817561A (en) | 1996-09-30 | 1998-10-06 | Motorola, Inc. | Insulated gate semiconductor device and method of manufacture |
| JP3749924B2 (ja) * | 1996-12-03 | 2006-03-01 | 富士通株式会社 | イオン注入方法および半導体装置の製造方法 |
| JP3660457B2 (ja) * | 1996-12-26 | 2005-06-15 | 株式会社東芝 | イオン発生装置及びイオン照射装置 |
| KR100231607B1 (ko) * | 1996-12-31 | 1999-11-15 | 김영환 | 반도체 소자의 초저접합 형성방법 |
| AU5818198A (en) * | 1997-01-10 | 1998-08-03 | Drexel University | Surface treatment of 312 ternary ceramic materials and products thereof |
| JP4010620B2 (ja) | 1997-01-10 | 2007-11-21 | 横浜ゴム株式会社 | 路面の凍結抑制構造 |
| US5837598A (en) * | 1997-03-13 | 1998-11-17 | Lsi Logic Corporation | Diffusion barrier for polysilicon gate electrode of MOS device in integrated circuit structure, and method of making same |
| US5885877A (en) * | 1997-04-21 | 1999-03-23 | Advanced Micro Devices, Inc. | Composite gate electrode incorporating dopant diffusion-retarding barrier layer adjacent to underlying gate dielectric |
| US5930634A (en) * | 1997-04-21 | 1999-07-27 | Advanced Micro Devices, Inc. | Method of making an IGFET with a multilevel gate |
| JPH11103050A (ja) | 1997-09-29 | 1999-04-13 | Fujitsu Ltd | 半導体装置及びその製造方法 |
| EP1036409A2 (en) * | 1998-06-11 | 2000-09-20 | Koninklijke Philips Electronics N.V. | Method of manufacturing a semiconductor device comprising a mos transistor |
| US6208004B1 (en) * | 1998-08-19 | 2001-03-27 | Philips Semiconductor, Inc. | Semiconductor device with high-temperature-stable gate electrode for sub-micron applications and fabrication thereof |
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| JP3277912B2 (ja) | 1999-03-24 | 2002-04-22 | 日本電気株式会社 | 半導体装置の製造方法 |
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| WO2000079601A1 (fr) * | 1999-06-23 | 2000-12-28 | Seiko Epson Corporation | Dispositif a semi-conducteur et procede de fabrication dudit dispositif |
| US6297109B1 (en) * | 1999-08-19 | 2001-10-02 | Chartered Semiconductor Manufacturing Ltd. | Method to form shallow junction transistors while eliminating shorts due to junction spiking |
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| JP3594550B2 (ja) | 2000-11-27 | 2004-12-02 | シャープ株式会社 | 半導体装置の製造方法 |
| US6693051B2 (en) * | 2001-02-01 | 2004-02-17 | Lucent Technologies Inc. | Silicon oxide based gate dielectric layer |
| AU2003261078A1 (en) * | 2002-06-26 | 2004-01-19 | Semequip Inc. | A semiconductor device and method of fabricating a semiconductor device |
| JP4112544B2 (ja) | 2004-09-15 | 2008-07-02 | 日精樹脂工業株式会社 | 成形監視システム |
-
2003
- 2003-06-18 AU AU2003261078A patent/AU2003261078A1/en not_active Abandoned
- 2003-06-18 CN CN2007101018002A patent/CN101055838B/zh not_active Expired - Fee Related
- 2003-06-18 JP JP2004517659A patent/JP2005531158A/ja active Pending
- 2003-06-18 WO PCT/US2003/019085 patent/WO2004003970A2/en not_active Ceased
- 2003-06-18 KR KR1020047021195A patent/KR100683594B1/ko not_active Expired - Fee Related
- 2003-06-18 KR KR1020067015937A patent/KR100768500B1/ko not_active Expired - Fee Related
- 2003-06-18 EP EP03761936A patent/EP1540720A4/en not_active Withdrawn
- 2003-06-18 CN CNB038150255A patent/CN100359652C/zh not_active Expired - Fee Related
- 2003-06-18 US US10/519,700 patent/US7723233B2/en not_active Expired - Fee Related
-
2009
- 2009-10-02 US US12/572,746 patent/US8236675B2/en not_active Expired - Fee Related
-
2010
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Also Published As
| Publication number | Publication date |
|---|---|
| CN101055838A (zh) | 2007-10-17 |
| JP2010161397A (ja) | 2010-07-22 |
| KR100768500B1 (ko) | 2007-10-19 |
| JP5437112B2 (ja) | 2014-03-12 |
| US20060099812A1 (en) | 2006-05-11 |
| EP1540720A4 (en) | 2007-09-26 |
| WO2004003970A3 (en) | 2004-06-03 |
| CN1663034A (zh) | 2005-08-31 |
| JP2005531158A (ja) | 2005-10-13 |
| CN100359652C (zh) | 2008-01-02 |
| AU2003261078A1 (en) | 2004-01-19 |
| KR20050008856A (ko) | 2005-01-21 |
| US7723233B2 (en) | 2010-05-25 |
| KR20060095580A (ko) | 2006-08-31 |
| WO2004003970A9 (en) | 2004-07-15 |
| EP1540720A2 (en) | 2005-06-15 |
| US20100022077A1 (en) | 2010-01-28 |
| US8236675B2 (en) | 2012-08-07 |
| AU2003261078A8 (en) | 2004-01-19 |
| WO2004003970A2 (en) | 2004-01-08 |
| KR100683594B1 (ko) | 2007-02-16 |
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