US20140291761A1 - Asymmetric Spacers - Google Patents
Asymmetric Spacers Download PDFInfo
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- US20140291761A1 US20140291761A1 US13/853,090 US201313853090A US2014291761A1 US 20140291761 A1 US20140291761 A1 US 20140291761A1 US 201313853090 A US201313853090 A US 201313853090A US 2014291761 A1 US2014291761 A1 US 2014291761A1
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- Prior art keywords
- spacer
- sidewall
- gate
- film layer
- semiconductor device
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- 125000006850 spacer group Chemical group 0.000 title claims abstract description 136
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7856—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with an non-uniform gate, e.g. varying doping structure, shape or composition on different sides of the fin, or different gate insulator thickness or composition on opposing fin sides
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
Definitions
- the present invention generally relates to semiconductor devices, and particularly to field effect transistor devices with sidewall spacers and methods for making the same.
- CMOS Complementary Metal-oxide-semiconductor
- FETs field effect transistors
- CMOS Complementary Metal-oxide-semiconductor
- FETs field effect transistors
- a channel region is formed in a n-doped or p-doped semiconductor substrate on which a gate structure is formed.
- the overall fabrication process is well known in the art, and includes forming a gate structure over a channel region connecting a source region and a drain region within the substrate on opposite ends of the gate, typically with some vertical overlap between the gate and the source/drain regions.
- the gate structure may be formed over or around a semiconductor fin on an insulator layer, with the source and the drain region formed on opposite ends of the semiconductor fin.
- an insulating spacer structure is formed on opposing sidewalls of the gate over, vertically overlapping a portion of the source/drain region.
- a semiconductor device comprises a gate formed on a top surface of a substrate, the gate having a first sidewall and a second sidewall, the first sidewall positioned opposite the second sidewall, a first spacer formed on and adjacent to the first sidewall of the gate, wherein the first spacer is made of a first material, and a second spacer formed on and adjacent to the second sidewall of the gate, wherein the second spacer is made of a second material different from the first material.
- a semiconductor device includes a gate formed on a top surface of a substrate, the gate having a first sidewall and a second sidewall, the first sidewall positioned opposite the second sidewall; a first spacer formed on the gate proximate to the first sidewall, wherein the first spacer is made of a first material; and a second spacer formed on and adjacent to the second sidewall of the gate, wherein the second spacer is made of a second material different from the first material.
- a method for forming a semiconductor device includes the steps of forming a gate onto a substrate, the gate having a first sidewall and a second sidewall, the first sidewall positioned opposite to the second sidewall; forming a first film layer on and adjacent to the first sidewall of the gate, wherein the first film layer is made from a first material; forming a second film layer made on and adjacent to the second sidewall of the gate, wherein the second film layer is made from a second material different from the first material; and shaping the first film layer to form a first spacer and shaping the second film layer to form a second spacer.
- a method for forming a semiconductor device includes forming a gate onto a substrate, the gate having a first sidewall and a second sidewall, the first sidewall positioned opposite to the second sidewall; forming a first film layer on the gate proximate to the first sidewall, wherein the first film layer is made from a first material; forming a second film layer made on and adjacent to the second sidewall of the gate, wherein the second film layer is made from a second material different from the first material; and shaping the first film layer to form a first spacer and shaping the second film layer to form a second spacer.
- FIG. 1A is a cross sectional front elevational view of a substrate layer formed during a step of a method for fabricating a FET device, according to an embodiment of the present invention
- FIG. 1B is a cross sectional front elevational view of a gate layer and a source/drain region formed onto the substrate layer depicted in FIG. 1A , according to an embodiment of the present invention
- FIG. 1C is a cross sectional front elevational view of a nitride spacer film layer formed onto the structure depicted in FIG. 1B , according to an embodiment of the present invention
- FIG. 1D is a cross sectional front elevational view of an oxide spacer film layer formed onto the structure depicted in FIG. 1C , according to an embodiment of the present invention
- FIG. 1E is a cross sectional front elevational view of an oxide spacer formed onto the structure depicted in FIG. 1D , according to an embodiment of the present invention
- FIG. 1F is a cross sectional front elevational view of a nitride spacer formed onto the structure depicted in FIG. 1E , having a relatively higher thickness than the oxide spacer depicted in FIG. 1E , according to an embodiment of the present invention
- FIG. 2A is a cross sectional front elevational view of an oxide spacer film layer formed onto a nitride film layer formed over an FET gate structure, according to an embodiment of the present invention
- FIG. 2B is a cross sectional front elevational view of an oxide spacer formed onto the structure depicted in FIG. 2A , according to an embodiment of the present invention.
- FIG. 2C is a cross sectional front elevational view of a nitride spacer formed onto the structure depicted in FIG. 2B , having a substantially equal thickness relative to the oxide spacer depicted in FIG. 2B , according to an embodiment of the present invention.
- FIG. 1A depicts a base substrate layer 102 .
- embodiments of the disclosed invention may comprise multi-layered substrates, including a buried oxide (BOX) layer (not shown), or a semiconductor-on-insulator (SOI) layer (not shown).
- the base substrate layer 102 may be made of any semiconductor material including, without limitation: silicon, germanium, silicon-germanium alloy, silicon carbide, silicon-germanium carbide alloy, and compound (e.g. III-V and II-VI) semiconductor materials.
- Non-limiting examples of compound semiconductor materials include gallium arsenide, indium arsenide, and indium phosphide.
- a BOX layer may be formed from any of several dielectric materials. Non-limiting examples include: oxides, nitrides, and oxynitrides of silicon, and combinations thereof. Oxides, nitrides, and oxynitrides of other elements are also envisioned. Further, the BOX layer (not shown) may include crystalline or non-crystalline dielectric material. The BOX layer (not shown) may be approximately 5 to approximately 500 nm thick, preferably approximately 200 nm A SOI layer (not shown) may be made of any of the several semiconductor materials possible for base substrate layer 102 .
- the base substrate layer 102 and the SOI layer may include either identical or different semiconducting materials with respect to chemical composition, dopant concentration and crystallographic orientation.
- the SOI layer (not shown) may be p-doped or n-doped with a dopant concentration of approximately 1 ⁇ 10 15 to approximately 1 ⁇ 10 18 /cm 3 , preferably approximately 1 ⁇ 10 15 /cm 3 .
- the SOI layer (not shown) may be approximately 2 to approximately 300 nm thick, preferably approximately 5 to approximately 100 nm
- a gate 104 is formed over a central portion of the base substrate layer 102 , and has a first sidewall 104 a and an opposing sidewall 104 b.
- the gate 104 may include a gate electrode, a gate dielectric, and a gate hard mask (not shown), made of, for example, a nitride material, and may be approximately 20 nm to approximately 150 nm thick, preferably approximately 50 nm
- the gate 102 may be formed using a gate-first process, in which case the gate electrode may further include a set of work-function metal layers, and a metal fill layer.
- the gate dielectric layer may be made of metal oxides, metal silicates, metal nitrides, transition metal oxides, transition metal silicates, transition metal nitrides, or combinations thereof, and may be approximately 1 nm to approximately 5 nm thick.
- Exemplary gate dielectric layer materials include silicon dioxide, hafnium oxide, and aluminum oxide.
- the work-function metal layers may include multiple metal-containing layers and may be made of titanium nitride, tantalum nitride, or titanium-aluminum and may be approximately 20 to approximately 100 angstroms thick.
- the metal fill layer may be made of, for example, silicon, aluminum, copper, tungsten, or some combination thereof. Other embodiments may include more or less metal layers depending on the application and the types of devices being formed.
- the composition of each metal layer may also vary and the process of selecting the material for each metal layer is known in the art.
- the gate 104 may be formed using a gate-last process, in which case the gate 104 may include a dummy gate layer made of, for example, silicon, and a dummy gate dielectric made of, for example, silicon oxide, intended to serve as a placeholder for the replacement gate formed after later processing steps.
- the gate 104 is replaced with a true gate dielectric and a gate conductor during subsequent processes.
- a source region 106 a and a drain region 106 b is formed on opposing sides of the gate 104 onto the substrate layer 102 , using any known method in the art, including, for example, ion implantation, gas phase doping, plasma doping, recess and in-situ doped epitaxy growth. It is not essential to the practice of the disclosed invention to form the source/drain regions 106 a and 106 b, although this step is typically performed in existing fabrication processes. Nor is it necessary to form the source/drain regions 106 a and 106 b in the depicted shape, length, width, height, or positions. Moreover, it is not necessary for these regions to be formed before sidewall spacers are formed.
- each of these two regions is referred to as either a source or a drain region for ease of reference, other embodiments of the disclosed invention may have the source region formed on the area denoted by 106 b, and the drain region formed in the area denoted by 106 a.
- a first spacer film layer 202 is formed onto a top surface of the gate 104 and adjacent to the first sidewall 104 a of the gate 104 and the substrate layer 102 where the source region 106 a is formed.
- the spacer film layer 202 may be formed using any known method in the art, such as masked deposition or etching, so that is formed only on one side of the gate 104 .
- the spacer film layer 202 may be formed on the top side and adjacent to the first sidewall 104 a and the second sidewall 104 b of the gate 104 , and thereafter selectively removed by any known means in the art, so that the spacer film layer 202 is removed from the second sidewall 104 b of the gate 104 .
- an additional method for forming the spacer film layer 202 onto the source region 106 a side of the gate 104 includes angled gas cluster ion beam (“angled GCIB”) deposition, as described in the co-pending U.S. Patent Application Serial No. (FIS920120314US1) incorporated herein by reference.
- angled GCIB angled gas cluster ion beam
- a second spacer film layer 204 is formed onto the top side and adjacent to the second sidewall 104 b of the transistor structure comprising the substrate layer 102 , the gate 104 , and the deposited spacer film layer 202 .
- the spacer film layer 204 may be formed adjacent to the first sidewall 104 a, the second sidewall 104 b, and the top side of the gate 104 , and thereafter selectively removed by any known means so that the spacer film layer 204 is removed from at least the first sidewall 104 a of the gate 104 .
- One process that may be used to selectively deposit the spacer film layer 204 is angled GCIB deposition, as described above.
- the spacer film layer 202 forms a thicker layer than the spacer film layer 204 in the depicted embodiment, the spacer film layer 202 may in fact be the thinner layer of the two in other embodiments. In other words, it is not necessary that the thicker layer of the two spacer film layers be formed first.
- the spacer film layer 204 is removed by any known method in the art, such as reactive ion etching (RIE) or GCIB etching (as described in the co-pending U.S. Patent Application Serial No. (FIS920120304US1)), to form a first spacer 302 on the second side of the gate 104 .
- RIE reactive ion etching
- GCIB GCIB etching
- the spacer film layer 202 is also removed by any known method in the art, as described above, to form a second spacer 304 on the first side of the gate 104 .
- the resulting structure shown in FIG. 1F comprises the substrate layer 102 , the gate layer 104 , the source region 106 a and the drain region 106 b, and the spacers 302 and 304 .
- the spacers 302 and 304 are formed using different materials, and have different thicknesses. Consequently, each spacer possesses a different dielectric capacitance that is, in part, a function of its material (having a distinct dielectric constant) and thickness.
- the spacer 304 is formed using an oxide compound and is thicker than the spacer 302 , which is formed using a nitride compound.
- the oxide spacer 304 has a thickness of 10 nm, and the nitride spacer 302 has a thickness of 5 nm Generally, nitride compounds have a higher dielectric constant than oxide compounds. Additionally, since the capacitance of each resulting structure is inversely proportional to the dielectric thickness of the structure, the thicker oxide spacer 304 has a lower capacitance than the thinner nitride spacer 302 .
- the oxide spacer 304 is formed on the drain side of the gate 104 , and the nitride spacer 302 is formed on the source side of the gate 104 .
- the first spacer 304 may be deposited onto the top surface of the gate 104 and adjacent to the first sidewall 104 a, such that the interface between the spacer 304 and the sidewall 104 a does not include the material used to form the spacer 302 .
- the spacer 302 may be deposited onto the top surface of the gate 104 and adjacent to the second sidewall 104 b, such that the interface between the spacer 302 and the sidewall 104 b does not include the material used to form the spacer 304 .
- Each of the two spacers 304 and 302 is in contact with, and is said to be adjacent to the sidewalls 104 a and 104 b, respectively.
- one or more intermediary layers may be formed at the interface of one of the spacer 302 or 304 and the respective sidewalls 104 b or 104 a, prior to the formation of that spacer film layer.
- an oxide layer may be formed onto the gate 104 and adjacent to the sidewall 104 a, and thereafter the spacer 304 may be formed on top of the oxide layer, proximate to the sidewall 104 a.
- the second spacer 302 may be formed on the gate and adjacent to the sidewall 104 b.
- the spacer 304 may be formed using an oxide compound (having, for example, a relative dielectric constant dielectric constant of 3.9), and the spacer 302 may be formed using a second compound having a lower dielectric constant, such as carbon doped-silicon oxide.
- a further embodiment of the disclosed invention includes the steps of forming a substrate layer 102 , a gate 104 having a first sidewall 104 a and a second sidewall 104 b, a source region 106 a and a drain region 106 b, and a first spacer film layer 202 onto a sidewall of the gate 104 and onto the substrate layer 102 , including the source region 106 a, in the same manner as described above and depicted in FIGS. 1A-1C (the steps depicted in FIGS. 1A-1C are not duplicated in FIGS. 2A-2C ).
- a second spacer film layer 204 is formed onto the top surface and adjacent to the second sidewall 104 b of the gate 104 and over the substrate layer 102 where the drain region 106 b is formed, using any known method in the art, including angled GCIB deposition, so that sufficient film material exists to allow the formation of spacers of substantially equal thickness in subsequent steps of the fabrication process.
- the spacer film layer 204 is removed by any known method in the art so as to form a first spacer 302 .
- the methods that may be used to form the spacer 302 is angled GCIB etching, as described in the co-pending U.S. Patent Application Serial No. (FIS920120304US1).
- the spacer film layer 202 is also removed by any known method in the art so as to form a second spacer 304 .
- the resulting structure comprises the substrate 102 , the gate 104 , the source region 106 a and the drain region 106 b, and the spacers 302 and 304 .
- the spacers 302 and 304 are of substantially equal shape and thickness, but are made from different materials.
- the interface between the spacer 304 and the sidewall 104 a does not include the material used to form the spacer 302 .
- the interface between the spacer 302 and the sidewall 104 b does not include the material used to make the spacer 304 .
- Each spacer is adjacent to the gate 104 via its respective sidewalls 104 a and 104 b.
- the spacer 304 may be formed proximate to the sidewall 104 a subsequent to forming an underlying layer using a material such as an oxide, and the spacer 302 may be formed adjacent to the sidewall 104 b.
- the spacer 302 is made from an oxide compound having a lower dielectric constant relative to the spacer 304 , and is formed over the drain side of the gate, whereas the spacer 304 is made from a nitride compound having a relatively higher dielectric constant and is formed over the source side of the gate.
- the spacer 304 is made from an oxide compound (having, for example, a relative dielectric constant of 3.9), and the spacer 302 is made from a material having a lower dielectric constant, such as carbon-doped silicon oxide.
- oxynitrides and doped materials, such as carbon-doped oxides, nitrides, and oxynitrides, as well as boron-doped nitrides, oxides, and oxynitrides.
- Each embodiment of the disclosed invention is advantageous relative to the prior art because it exhibits a higher dielectric constant on its source side, leading to better drive current; and a lower dielectric constant on its drain side, leading to decreased parasitic capacitance and lower power consumption.
- Each embodiment further allows for additional space in the trench structures formed between serially positioned transistors by using less spacer material on one or both sides of the gate 104 . The additional space can be used to form more reliable contacts during subsequent fabrication steps. This benefit becomes more critical as transistors are scaled down even further, limiting the space available for forming effective and reliable contact regions.
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Abstract
Description
- This application is related to the following commonly-owned, co-pending United States Patent Application filed on even date herewith, the contents and disclosure of which is expressly incorporated by reference herein in its entirety: U.S. Patent Application Serial No. (FIS920120314US1), for “ANGLED GAS CLUSTER ION BEAM”.
- The present invention generally relates to semiconductor devices, and particularly to field effect transistor devices with sidewall spacers and methods for making the same.
- Complementary Metal-oxide-semiconductor (CMOS) technology is commonly used for fabricating field effect transistors (FETs) as part of advanced integrated circuits, such as CPUs, memory, storage devices, and the like. At the core of planar FETs, a channel region is formed in a n-doped or p-doped semiconductor substrate on which a gate structure is formed. The overall fabrication process is well known in the art, and includes forming a gate structure over a channel region connecting a source region and a drain region within the substrate on opposite ends of the gate, typically with some vertical overlap between the gate and the source/drain regions. In finFETs, the gate structure may be formed over or around a semiconductor fin on an insulator layer, with the source and the drain region formed on opposite ends of the semiconductor fin. In planar FETs, an insulating spacer structure is formed on opposing sidewalls of the gate over, vertically overlapping a portion of the source/drain region.
- As the industry continues to move towards smaller scale devices that operate at faster speeds and with lesser operational costs, it becomes increasingly difficult to retain device operation and efficiency. This is partially because while operational side effects may be negligible at a given scale, they play a more critical role as devices are scaled down. A particular problem is the buildup of parasitic capacitance in FETs and similar structures. The source/drain regions and the gate are both conductors, and are separated by insulating spacers. Therefore, they functions as an unwanted capacitor, contributing to the buildup of parasitic capacitance. Because capacitance is inversely proportional to insulator thickness between two conductors, it increases as transistors become smaller and spaces become thinner. As the parasitic capacitance of a transistor increases, its operability and performance suffer.
- Therefore, it is desirable to form a transistor structure that reduces the build up of parasitic capacitance and improves device reliability and efficiency, particularly in scaled-down transistor structures.
- According to an embodiment of the disclosed invention, a semiconductor device comprises a gate formed on a top surface of a substrate, the gate having a first sidewall and a second sidewall, the first sidewall positioned opposite the second sidewall, a first spacer formed on and adjacent to the first sidewall of the gate, wherein the first spacer is made of a first material, and a second spacer formed on and adjacent to the second sidewall of the gate, wherein the second spacer is made of a second material different from the first material.
- According to a further embodiment of the disclosed invention, a semiconductor device includes a gate formed on a top surface of a substrate, the gate having a first sidewall and a second sidewall, the first sidewall positioned opposite the second sidewall; a first spacer formed on the gate proximate to the first sidewall, wherein the first spacer is made of a first material; and a second spacer formed on and adjacent to the second sidewall of the gate, wherein the second spacer is made of a second material different from the first material.
- According to another embodiment of the disclosed invention, a method for forming a semiconductor device includes the steps of forming a gate onto a substrate, the gate having a first sidewall and a second sidewall, the first sidewall positioned opposite to the second sidewall; forming a first film layer on and adjacent to the first sidewall of the gate, wherein the first film layer is made from a first material; forming a second film layer made on and adjacent to the second sidewall of the gate, wherein the second film layer is made from a second material different from the first material; and shaping the first film layer to form a first spacer and shaping the second film layer to form a second spacer.
- According to a further embodiment of the disclosed invention, a method for forming a semiconductor device, includes forming a gate onto a substrate, the gate having a first sidewall and a second sidewall, the first sidewall positioned opposite to the second sidewall; forming a first film layer on the gate proximate to the first sidewall, wherein the first film layer is made from a first material; forming a second film layer made on and adjacent to the second sidewall of the gate, wherein the second film layer is made from a second material different from the first material; and shaping the first film layer to form a first spacer and shaping the second film layer to form a second spacer.
- Elements of the figures are not necessarily to scale and are not intended to portray specific parameters of the invention. For clarity and ease of illustration, scale of elements may be exaggerated. The detailed description should be consulted for accurate dimensions. The drawings are intended to depict only typical embodiments of the invention, and therefore should not be considered as limiting the scope of the invention. In the drawings, like numbering represents like elements.
-
FIG. 1A is a cross sectional front elevational view of a substrate layer formed during a step of a method for fabricating a FET device, according to an embodiment of the present invention; -
FIG. 1B is a cross sectional front elevational view of a gate layer and a source/drain region formed onto the substrate layer depicted inFIG. 1A , according to an embodiment of the present invention; -
FIG. 1C is a cross sectional front elevational view of a nitride spacer film layer formed onto the structure depicted inFIG. 1B , according to an embodiment of the present invention; -
FIG. 1D is a cross sectional front elevational view of an oxide spacer film layer formed onto the structure depicted inFIG. 1C , according to an embodiment of the present invention; -
FIG. 1E is a cross sectional front elevational view of an oxide spacer formed onto the structure depicted inFIG. 1D , according to an embodiment of the present invention; -
FIG. 1F is a cross sectional front elevational view of a nitride spacer formed onto the structure depicted inFIG. 1E , having a relatively higher thickness than the oxide spacer depicted inFIG. 1E , according to an embodiment of the present invention; -
FIG. 2A is a cross sectional front elevational view of an oxide spacer film layer formed onto a nitride film layer formed over an FET gate structure, according to an embodiment of the present invention; -
FIG. 2B is a cross sectional front elevational view of an oxide spacer formed onto the structure depicted inFIG. 2A , according to an embodiment of the present invention; and -
FIG. 2C is a cross sectional front elevational view of a nitride spacer formed onto the structure depicted inFIG. 2B , having a substantially equal thickness relative to the oxide spacer depicted inFIG. 2B , according to an embodiment of the present invention. - Exemplary embodiments now will be described more fully herein with reference to the accompanying drawings, in which exemplary embodiments are shown. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of this disclosure to those skilled in the art. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.
- Referring to
FIGS. 1A-F , an exemplary embodiment of the disclosed invention is shown and discussed hereinafter.FIG. 1A depicts abase substrate layer 102. Although only one substrate layer is shown, embodiments of the disclosed invention may comprise multi-layered substrates, including a buried oxide (BOX) layer (not shown), or a semiconductor-on-insulator (SOI) layer (not shown). Thebase substrate layer 102 may be made of any semiconductor material including, without limitation: silicon, germanium, silicon-germanium alloy, silicon carbide, silicon-germanium carbide alloy, and compound (e.g. III-V and II-VI) semiconductor materials. Non-limiting examples of compound semiconductor materials include gallium arsenide, indium arsenide, and indium phosphide. A BOX layer (not shown) may be formed from any of several dielectric materials. Non-limiting examples include: oxides, nitrides, and oxynitrides of silicon, and combinations thereof. Oxides, nitrides, and oxynitrides of other elements are also envisioned. Further, the BOX layer (not shown) may include crystalline or non-crystalline dielectric material. The BOX layer (not shown) may be approximately 5 to approximately 500 nm thick, preferably approximately 200 nm A SOI layer (not shown) may be made of any of the several semiconductor materials possible forbase substrate layer 102. In general, thebase substrate layer 102 and the SOI layer (not shown) may include either identical or different semiconducting materials with respect to chemical composition, dopant concentration and crystallographic orientation. The SOI layer (not shown) may be p-doped or n-doped with a dopant concentration of approximately 1×1015 to approximately 1×1018/cm3, preferably approximately 1×1015/cm3. The SOI layer (not shown) may be approximately 2 to approximately 300 nm thick, preferably approximately 5 to approximately 100 nm - Referring now to
FIG. 1B , agate 104 is formed over a central portion of thebase substrate layer 102, and has afirst sidewall 104 a and an opposingsidewall 104 b. Thegate 104 may include a gate electrode, a gate dielectric, and a gate hard mask (not shown), made of, for example, a nitride material, and may be approximately 20 nm to approximately 150 nm thick, preferably approximately 50 nm In some embodiments, thegate 102 may be formed using a gate-first process, in which case the gate electrode may further include a set of work-function metal layers, and a metal fill layer. The gate dielectric layer may be made of metal oxides, metal silicates, metal nitrides, transition metal oxides, transition metal silicates, transition metal nitrides, or combinations thereof, and may be approximately 1 nm to approximately 5 nm thick. Exemplary gate dielectric layer materials include silicon dioxide, hafnium oxide, and aluminum oxide. The work-function metal layers may include multiple metal-containing layers and may be made of titanium nitride, tantalum nitride, or titanium-aluminum and may be approximately 20 to approximately 100 angstroms thick. The metal fill layer may be made of, for example, silicon, aluminum, copper, tungsten, or some combination thereof. Other embodiments may include more or less metal layers depending on the application and the types of devices being formed. The composition of each metal layer may also vary and the process of selecting the material for each metal layer is known in the art. - In other embodiments, the
gate 104 may be formed using a gate-last process, in which case thegate 104 may include a dummy gate layer made of, for example, silicon, and a dummy gate dielectric made of, for example, silicon oxide, intended to serve as a placeholder for the replacement gate formed after later processing steps. Thegate 104 is replaced with a true gate dielectric and a gate conductor during subsequent processes. - Further referring to
FIG. 1B , asource region 106 a and adrain region 106 b is formed on opposing sides of thegate 104 onto thesubstrate layer 102, using any known method in the art, including, for example, ion implantation, gas phase doping, plasma doping, recess and in-situ doped epitaxy growth. It is not essential to the practice of the disclosed invention to form the source/drain regions drain regions - Referring now to
FIG. 1C , a firstspacer film layer 202 is formed onto a top surface of thegate 104 and adjacent to thefirst sidewall 104 a of thegate 104 and thesubstrate layer 102 where thesource region 106 a is formed. Thespacer film layer 202 may be formed using any known method in the art, such as masked deposition or etching, so that is formed only on one side of thegate 104. In a related embodiment, thespacer film layer 202 may be formed on the top side and adjacent to thefirst sidewall 104 a and thesecond sidewall 104 b of thegate 104, and thereafter selectively removed by any known means in the art, so that thespacer film layer 202 is removed from thesecond sidewall 104 b of thegate 104. - Further referring to
FIG. 1C , an additional method for forming thespacer film layer 202 onto thesource region 106 a side of thegate 104 includes angled gas cluster ion beam (“angled GCIB”) deposition, as described in the co-pending U.S. Patent Application Serial No. (FIS920120314US1) incorporated herein by reference. - Referring now to
FIG. 1D , a secondspacer film layer 204 is formed onto the top side and adjacent to thesecond sidewall 104 b of the transistor structure comprising thesubstrate layer 102, thegate 104, and the depositedspacer film layer 202. In a related embodiment, thespacer film layer 204 may be formed adjacent to thefirst sidewall 104 a, thesecond sidewall 104 b, and the top side of thegate 104, and thereafter selectively removed by any known means so that thespacer film layer 204 is removed from at least thefirst sidewall 104 a of thegate 104. One process that may be used to selectively deposit thespacer film layer 204 is angled GCIB deposition, as described above. - Although the
spacer film layer 202 forms a thicker layer than thespacer film layer 204 in the depicted embodiment, thespacer film layer 202 may in fact be the thinner layer of the two in other embodiments. In other words, it is not necessary that the thicker layer of the two spacer film layers be formed first. - Referring now to
FIG. 1E , thespacer film layer 204 is removed by any known method in the art, such as reactive ion etching (RIE) or GCIB etching (as described in the co-pending U.S. Patent Application Serial No. (FIS920120304US1)), to form afirst spacer 302 on the second side of thegate 104. - Referring now to
FIG. 1F , thespacer film layer 202 is also removed by any known method in the art, as described above, to form asecond spacer 304 on the first side of thegate 104. - The resulting structure shown in
FIG. 1F comprises thesubstrate layer 102, thegate layer 104, thesource region 106 a and thedrain region 106 b, and thespacers spacers spacer 304 is formed using an oxide compound and is thicker than thespacer 302, which is formed using a nitride compound. Preferably, theoxide spacer 304 has a thickness of 10 nm, and thenitride spacer 302 has a thickness of 5 nm Generally, nitride compounds have a higher dielectric constant than oxide compounds. Additionally, since the capacitance of each resulting structure is inversely proportional to the dielectric thickness of the structure, thethicker oxide spacer 304 has a lower capacitance than thethinner nitride spacer 302. Theoxide spacer 304 is formed on the drain side of thegate 104, and thenitride spacer 302 is formed on the source side of thegate 104. - Further referring to
FIG. 1F , according to an aspect of the invention, thefirst spacer 304 may be deposited onto the top surface of thegate 104 and adjacent to thefirst sidewall 104 a, such that the interface between thespacer 304 and thesidewall 104 a does not include the material used to form thespacer 302. Likewise, thespacer 302 may be deposited onto the top surface of thegate 104 and adjacent to thesecond sidewall 104 b, such that the interface between thespacer 302 and thesidewall 104 b does not include the material used to form thespacer 304. Each of the twospacers sidewalls - According to another embodiment of the disclosed invention, one or more intermediary layers may be formed at the interface of one of the
spacer respective sidewalls gate 104 and adjacent to thesidewall 104 a, and thereafter thespacer 304 may be formed on top of the oxide layer, proximate to thesidewall 104 a. According to the disclosed embodiment, thesecond spacer 302 may be formed on the gate and adjacent to thesidewall 104 b. - In a related embodiment, the
spacer 304 may be formed using an oxide compound (having, for example, a relative dielectric constant dielectric constant of 3.9), and thespacer 302 may be formed using a second compound having a lower dielectric constant, such as carbon doped-silicon oxide. - Referring now generally to
FIGS. 2A-C , a further embodiment of the disclosed invention includes the steps of forming asubstrate layer 102, agate 104 having afirst sidewall 104 a and asecond sidewall 104 b, asource region 106 a and adrain region 106 b, and a firstspacer film layer 202 onto a sidewall of thegate 104 and onto thesubstrate layer 102, including thesource region 106 a, in the same manner as described above and depicted inFIGS. 1A-1C (the steps depicted inFIGS. 1A-1C are not duplicated inFIGS. 2A-2C ). - Referring now specifically to
FIG. 2A , a secondspacer film layer 204 is formed onto the top surface and adjacent to thesecond sidewall 104 b of thegate 104 and over thesubstrate layer 102 where thedrain region 106 b is formed, using any known method in the art, including angled GCIB deposition, so that sufficient film material exists to allow the formation of spacers of substantially equal thickness in subsequent steps of the fabrication process. - Referring now to
FIG. 2B , thespacer film layer 204 is removed by any known method in the art so as to form afirst spacer 302. Among the methods that may be used to form thespacer 302 is angled GCIB etching, as described in the co-pending U.S. Patent Application Serial No. (FIS920120304US1). - Referring now to
FIG. 2C , thespacer film layer 202 is also removed by any known method in the art so as to form asecond spacer 304. The resulting structure comprises thesubstrate 102, thegate 104, thesource region 106 a and thedrain region 106 b, and thespacers spacers - As described in connection with
FIGS. 1A-F , according to the disclosed embodiment, the interface between thespacer 304 and thesidewall 104 a does not include the material used to form thespacer 302. Likewise, the interface between thespacer 302 and thesidewall 104 b does not include the material used to make thespacer 304. Each spacer is adjacent to thegate 104 via itsrespective sidewalls - According to a related embodiment, the
spacer 304 may be formed proximate to thesidewall 104 a subsequent to forming an underlying layer using a material such as an oxide, and thespacer 302 may be formed adjacent to thesidewall 104 b. - According to the disclosed embodiment, the
spacer 302 is made from an oxide compound having a lower dielectric constant relative to thespacer 304, and is formed over the drain side of the gate, whereas thespacer 304 is made from a nitride compound having a relatively higher dielectric constant and is formed over the source side of the gate. - According to a related embodiment, the
spacer 304 is made from an oxide compound (having, for example, a relative dielectric constant of 3.9), and thespacer 302 is made from a material having a lower dielectric constant, such as carbon-doped silicon oxide. - Other embodiments of the disclosed invention may use one or more other materials exclusively or in addition to those recited above, including, and without limitation, oxynitrides, and doped materials, such as carbon-doped oxides, nitrides, and oxynitrides, as well as boron-doped nitrides, oxides, and oxynitrides.
- Each embodiment of the disclosed invention is advantageous relative to the prior art because it exhibits a higher dielectric constant on its source side, leading to better drive current; and a lower dielectric constant on its drain side, leading to decreased parasitic capacitance and lower power consumption. Each embodiment further allows for additional space in the trench structures formed between serially positioned transistors by using less spacer material on one or both sides of the
gate 104. The additional space can be used to form more reliable contacts during subsequent fabrication steps. This benefit becomes more critical as transistors are scaled down even further, limiting the space available for forming effective and reliable contact regions. - The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiment, the practical application or technical improvement over technologies found in the marketplace, or to enable other of ordinary skill in the art to understand the embodiments disclosed herein. It is therefore intended that the present invention not be limited to the exact forms and details described and illustrated but fall within the scope of the appended claims.
Claims (30)
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US9236447B2 (en) | 2013-03-29 | 2016-01-12 | Globalfoundries Inc. | Asymmetric spacers |
US20170271167A1 (en) * | 2013-12-23 | 2017-09-21 | International Business Machines Corporation | Fin density control of multigate devices through sidewall image transfer processes |
US10170327B2 (en) * | 2013-12-23 | 2019-01-01 | International Business Machines Corporation | Fin density control of multigate devices through sidewall image transfer processes |
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US9991117B2 (en) * | 2016-05-12 | 2018-06-05 | International Business Machines Corporation | Fin patterns with varying spacing without fin cut |
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US9984877B2 (en) * | 2016-05-12 | 2018-05-29 | International Business Machines Corporation | Fin patterns with varying spacing without fin cut |
US20190157084A1 (en) * | 2017-11-21 | 2019-05-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Directional Deposition for Semiconductor Fabrication |
US11075079B2 (en) * | 2017-11-21 | 2021-07-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Directional deposition for semiconductor fabrication |
US20210358752A1 (en) * | 2017-11-21 | 2021-11-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Directional Deposition for Semiconductor Fabrication |
US11569090B2 (en) * | 2017-11-21 | 2023-01-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Directional deposition for semiconductor fabrication |
US11955338B2 (en) | 2017-11-21 | 2024-04-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | Directional deposition for semiconductor fabrication |
CN112563200A (en) * | 2019-09-26 | 2021-03-26 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
US11508833B2 (en) * | 2019-09-26 | 2022-11-22 | Semiconductor Manufacturing International (Shanghai) Corporation | Semiconductor device and fabrication method thereof |
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US20150140799A1 (en) | 2015-05-21 |
US9236447B2 (en) | 2016-01-12 |
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