CN101038919B - 在体硅上制造1t-dram的方法 - Google Patents

在体硅上制造1t-dram的方法 Download PDF

Info

Publication number
CN101038919B
CN101038919B CN2007101006185A CN200710100618A CN101038919B CN 101038919 B CN101038919 B CN 101038919B CN 2007101006185 A CN2007101006185 A CN 2007101006185A CN 200710100618 A CN200710100618 A CN 200710100618A CN 101038919 B CN101038919 B CN 101038919B
Authority
CN
China
Prior art keywords
integrated circuit
transistor
region
silicon layer
bulk
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN2007101006185A
Other languages
English (en)
Chinese (zh)
Other versions
CN101038919A (zh
Inventor
吴宗泽
陈若文
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kaiwei International Co
Marvell International Ltd
Marvell Asia Pte Ltd
Original Assignee
Mawier International Trade Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mawier International Trade Co Ltd filed Critical Mawier International Trade Co Ltd
Publication of CN101038919A publication Critical patent/CN101038919A/zh
Application granted granted Critical
Publication of CN101038919B publication Critical patent/CN101038919B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/20—DRAM devices comprising floating-body transistors, e.g. floating-body cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/711—Insulated-gate field-effect transistors [IGFET] having floating bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices
    • H10D88/01—Manufacture or treatment

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Dram (AREA)
CN2007101006185A 2006-03-15 2007-03-15 在体硅上制造1t-dram的方法 Expired - Fee Related CN101038919B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US78247906P 2006-03-15 2006-03-15
US60/782,479 2006-03-15
US11/674,008 2007-02-12
US11/674,008 US8008137B2 (en) 2006-03-15 2007-02-12 Method for fabricating 1T-DRAM on bulk silicon

Publications (2)

Publication Number Publication Date
CN101038919A CN101038919A (zh) 2007-09-19
CN101038919B true CN101038919B (zh) 2012-01-04

Family

ID=38077174

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2007101006185A Expired - Fee Related CN101038919B (zh) 2006-03-15 2007-03-15 在体硅上制造1t-dram的方法

Country Status (5)

Country Link
US (1) US8008137B2 (https=)
EP (1) EP1835535A3 (https=)
JP (1) JP2007294897A (https=)
CN (1) CN101038919B (https=)
TW (1) TWI423422B (https=)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100714401B1 (ko) * 2006-02-08 2007-05-04 삼성전자주식회사 적층된 트랜지스터를 구비하는 반도체 장치 및 그 형성방법
US8278167B2 (en) 2008-12-18 2012-10-02 Micron Technology, Inc. Method and structure for integrating capacitor-less memory cell with logic
TWI433302B (zh) 2009-03-03 2014-04-01 旺宏電子股份有限公司 積體電路自對準三度空間記憶陣列及其製作方法
WO2011080998A1 (en) 2009-12-28 2011-07-07 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
WO2011114919A1 (en) * 2010-03-19 2011-09-22 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
KR101884031B1 (ko) * 2010-04-07 2018-07-31 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 기억 장치
WO2012002186A1 (en) 2010-07-02 2012-01-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
WO2012008304A1 (en) 2010-07-16 2012-01-19 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
WO2012029638A1 (en) 2010-09-03 2012-03-08 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP2012256821A (ja) 2010-09-13 2012-12-27 Semiconductor Energy Lab Co Ltd 記憶装置
TWI539453B (zh) * 2010-09-14 2016-06-21 半導體能源研究所股份有限公司 記憶體裝置和半導體裝置
US9048142B2 (en) 2010-12-28 2015-06-02 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
TWI564890B (zh) 2011-01-26 2017-01-01 半導體能源研究所股份有限公司 記憶體裝置及半導體裝置
WO2012102182A1 (en) * 2011-01-26 2012-08-02 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US9012993B2 (en) * 2011-07-22 2015-04-21 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
CN102446958B (zh) * 2011-11-08 2014-11-05 上海华力微电子有限公司 绝缘体上碳硅-锗硅异质结1t-dram结构及形成方法
US8981367B2 (en) 2011-12-01 2015-03-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP6081171B2 (ja) 2011-12-09 2017-02-15 株式会社半導体エネルギー研究所 記憶装置
JP6105266B2 (ja) 2011-12-15 2017-03-29 株式会社半導体エネルギー研究所 記憶装置
US9559113B2 (en) 2014-05-01 2017-01-31 Macronix International Co., Ltd. SSL/GSL gate oxide in 3D vertical channel NAND
US9287257B2 (en) * 2014-05-30 2016-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Power gating for three dimensional integrated circuits (3DIC)
US9281305B1 (en) * 2014-12-05 2016-03-08 National Applied Research Laboratories Transistor device structure
JP6901831B2 (ja) 2015-05-26 2021-07-14 株式会社半導体エネルギー研究所 メモリシステム、及び情報処理システム
JP6773453B2 (ja) 2015-05-26 2020-10-21 株式会社半導体エネルギー研究所 記憶装置及び電子機器
US10147722B2 (en) * 2016-08-12 2018-12-04 Renesas Electronics America Inc. Isolated circuit formed during back end of line process

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0774358A (ja) * 1993-06-30 1995-03-17 Fujitsu Ltd ペロブスカイト系酸化膜の形成方法およびペロブスカイト系酸化膜を用いた薄膜トランジスタとその製造方法
US5675185A (en) * 1995-09-29 1997-10-07 International Business Machines Corporation Semiconductor structure incorporating thin film transistors with undoped cap oxide layers
US8779597B2 (en) * 2004-06-21 2014-07-15 Sang-Yun Lee Semiconductor device with base support structure
JPH11233789A (ja) * 1998-02-12 1999-08-27 Semiconductor Energy Lab Co Ltd 半導体装置
KR100450595B1 (ko) * 2000-02-09 2004-09-30 히다찌 케이블 리미티드 결정실리콘 반도체장치 및 그 장치의 제조방법
US6635552B1 (en) 2000-06-12 2003-10-21 Micron Technology, Inc. Methods of forming semiconductor constructions
JP5792918B2 (ja) * 2000-08-14 2015-10-14 サンディスク・スリー・ディ・リミテッド・ライアビリティ・カンパニーＳａｎｄｉｓｋ ３Ｄ Ｌｌｃ 高集積メモリデバイス
JP2004039690A (ja) * 2002-06-28 2004-02-05 Seiko Epson Corp 半導体素子
WO2004015764A2 (en) 2002-08-08 2004-02-19 Leedy Glenn J Vertical system integration
JP2004079696A (ja) * 2002-08-14 2004-03-11 Renesas Technology Corp 半導体記憶装置
US7042756B2 (en) 2002-10-18 2006-05-09 Viciciv Technology Configurable storage device
US7541614B2 (en) 2003-03-11 2009-06-02 Semiconductor Energy Laboratory Co., Ltd. Integrated circuit, semiconductor device comprising the same, electronic device having the same, and driving method of the same
JP4028499B2 (ja) * 2004-03-01 2007-12-26 株式会社東芝 半導体記憶装置
JP3898715B2 (ja) 2004-09-09 2007-03-28 株式会社東芝 半導体装置およびその製造方法
KR100655664B1 (ko) * 2005-07-08 2006-12-08 삼성전자주식회사 스택형 반도체 장치 및 그 제조 방법

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Pierre C. Fazan.A simple 1-transistor capacitor-less memory cell for highperformance embedded DRAMs.IEEE 2002 custom integrated circuites conference.2002,99-102. *

Also Published As

Publication number Publication date
US8008137B2 (en) 2011-08-30
CN101038919A (zh) 2007-09-19
EP1835535A3 (en) 2010-07-14
JP2007294897A (ja) 2007-11-08
TWI423422B (zh) 2014-01-11
EP1835535A2 (en) 2007-09-19
US20070215906A1 (en) 2007-09-20
TW200742039A (en) 2007-11-01

Similar Documents

Publication Publication Date Title
CN101038919B (zh) 在体硅上制造1t-dram的方法
US7944743B2 (en) Methods of making a semiconductor memory device
TWI384586B (zh) 具有垂直存取裝置之記憶體
JP2023178501A (ja) 半導体装置
JP4431401B2 (ja) 極薄垂直ボデイトランジスタを有する折り返しビットラインｄｒａｍ
US8526220B2 (en) Complementary SOI lateral bipolar for SRAM in a low-voltage CMOS platform
US20120112156A1 (en) Non-Volatile Memory Devices Having Resistance Changeable Elements And Related Systems And Methods
US8669165B2 (en) Method of fabricating semiconductor device using deuterium annealing
JP2004527901A (ja) キャビティ内に部分的に製造されたコンデンサ構造を備えたｄｒａｍセル及びその作動方法
KR20170065241A (ko) 전기적 특성을 개선할 수 있는 에스램 소자 및 이를 포함하는 로직 소자
CN111052379A (zh) 带有后端晶体管的铁电电容器
CN116391452A (zh) 具有垂直晶体管和堆叠存储单元的存储器器件及其形成方法
CN114975446B (zh) 基于平场晶体管的动态随机存取存储器
CN116391454A (zh) 具有交错布局中的垂直晶体管的存储器器件
CN113823635A (zh) 具有与晶体管栅极叠层分离的铁电电容器的存储器单元
US8750023B2 (en) Semiconductor memory device
US20190326299A1 (en) Thin-film transistor embedded dynamic random-access memory
CN116391262A (zh) 具有垂直晶体管的存储器器件及其形成方法
JP2004165197A (ja) 半導体集積回路装置およびその製造方法
EP2490222B1 (en) Memory cell and memory array utilizing the memory cell
HK1111520A (en) Method for fabricating 1t-dram on bulk silicon
TWI908153B (zh) 使用半導體元件的三次元積層記憶體裝置
US20250309165A1 (en) Managing peripheral circuitries in semiconductive devices
CN119421414A (zh) 半导体结构的制备方法、半导体结构、器件及设备
CN119486266A (zh) 半导体结构及其制作方法、存储器系统

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
REG Reference to a national code

Ref country code: HK

Ref legal event code: DE

Ref document number: 1111520

Country of ref document: HK

C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
REG Reference to a national code

Ref country code: HK

Ref legal event code: WD

Ref document number: 1111520

Country of ref document: HK

TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20200424

Address after: Singapore City

Patentee after: Marvell Asia Pte. Ltd.

Address before: Ford street, Grand Cayman, Cayman Islands

Patentee before: Kaiwei international Co.

Effective date of registration: 20200424

Address after: Ford street, Grand Cayman, Cayman Islands

Patentee after: Kaiwei international Co.

Address before: Hamilton, Bermuda

Patentee before: Marvell International Ltd.

Effective date of registration: 20200424

Address after: Hamilton, Bermuda

Patentee after: Marvell International Ltd.

Address before: Babado J San Michael

Patentee before: MARVELL WORLD TRADE Ltd.

CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20120104