JP2007294897A - バルクシリコン上に1t−dramを製造するための方法 - Google Patents
バルクシリコン上に1t−dramを製造するための方法 Download PDFInfo
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- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 60
- 239000010703 silicon Substances 0.000 title claims abstract description 60
- 238000000034 method Methods 0.000 title description 36
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 59
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- 238000005516 engineering process Methods 0.000 claims abstract description 7
- 239000010410 layer Substances 0.000 claims description 84
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 25
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 15
- 229920005591 polysilicon Polymers 0.000 claims description 15
- 210000000746 body region Anatomy 0.000 claims description 11
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000011229 interlayer Substances 0.000 claims description 7
- 229910052759 nickel Inorganic materials 0.000 claims description 4
- 238000013500 data storage Methods 0.000 description 11
- 239000010408 film Substances 0.000 description 10
- 150000002500 ions Chemical class 0.000 description 9
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- 239000004065 semiconductor Substances 0.000 description 7
- 238000004364 calculation method Methods 0.000 description 6
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- 229910044991 metal oxide Inorganic materials 0.000 description 5
- 150000004706 metal oxides Chemical class 0.000 description 5
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- 239000010409 thin film Substances 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 4
- 238000004891 communication Methods 0.000 description 4
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
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Abstract
【解決手段】 集積回路は、バルクシリコン層及びバルクシリコン層の上に製造された相補型MOSFET(CMOS)トランジスタを有するバルク技術集積回路(バルクIC)を備えている。この集積回路はまた、バルクICに隣接して設けられ且つ一体化された単一トランジスタのダイナミックランダムアクセスメモリ(1T−DRAM)セル212を備えている。
【選択図】 図1E
Description
Claims (21)
- バルクシリコン層、及び該バルクシリコン層上に製造された相補型MOSFET(CMOS)トランジスタを有するバルク技術集積回路(バルクIC)と、
前記バルクICに隣接して設けられ且つ一体化された第1の単一トランジスタダイナミックランダムアクセスメモリ(1T−DRAM)セルと、
を備える集積回路。 - 前記第1の1T−DRAMセルが、
アモルファスシリコン層と、
前記アモルファスシリコン層に隣接して設けられた第1及び第2のゲート酸化層、並びに、前記第1及び第2のゲート酸化層内に設けられた第1及び第2のゲートポリシリコン層を有する第1及び第2のゲートと、
を備える、請求項1に記載の集積回路。 - 前記第1の1T−DRAMセルが、前記アモルファスシリコン層並びに前記第1及び第2のゲートに隣接して設けられた第1の層間誘電体(ILD)を有する、請求項2に記載の集積回路。
- 前記バルクICの前記バルクシリコン層が、第1及び第2のドープ領域を有するNウェル、並びに第3及び第4のドープ領域を有するPウェルを備え、
前記バルクICが、前記バルクシリコン層に隣接して設けられた第3及び第4のゲート酸化層、並びに、前記第3及び第4のゲート酸化層内に設けられた第3及び第4のゲートポリシリコン層を有する第3及び第4のゲートを更に備える、
請求項3に記載の集積回路。 - 前記バルクシリコン層並びに前記第3及び第4のゲートに隣接して設けられた第2のILDを更に備える、請求項4に記載の集積回路。
- 前記第2のILDの内に設けられ、且つ、前記バルクシリコン層の前記第1及び第4のドープ領域に接続する第1及び第2のコンタクトを更に備える、請求項5に記載の集積回路。
- 前記第1のILD内に設けられた第3及び第4のコンタクトを更に備え、前記第1及び第2のコンタクトが前記第3及び第4のコンタクトに接続する、請求項6に記載の集積回路。
- 前記第3及び第4のコンタクトに接続するメタルビット線を更に備える、請求項7に記載の集積回路。
- 前記アモルファスシリコン層が、第1、第2、及び第3のドープ領域を有し、前記第1のゲートが前記第1のドープ領域の一部及び第2のドープ領域の一部に隣接して設けられており、前記第2のゲートが前記第2のドープ領域の一部及び第3のドープ領域の一部に隣接して設けられている、請求項2に記載の集積回路。
- 前記第1のILD内に設けられ、且つ、前記アモルファスシリコン層の前記第2のドープ領域に接続する第5のコンタクトを更に備える、請求項9に記載の集積回路。
- 前記CMOSトランジスタ及び前記第1の1T−DRAMセルに接続するビット線を更に備える、請求項1に記載の集積回路。
- 前記第1の1T−DRAMセルが、ゲート領域を有する第1のトランジスタを備える、請求項11に記載の集積回路。
- 前記第1の1T−DRAMセルが、本体領域及びソース領域を有する第1のトランジスタを備える、請求項1に記載の集積回路。
- 前記本体領域がデータを蓄える、請求項13に記載の集積回路。
- 前記本体領域がアモルファスシリコン層を有する、請求項14に記載の集積回路。
- 前記ソ−ス領域を前記第1の1T−DRAMセルの前記トタンジスタと共有する第2のトランジスタを有する第2の1T−DRAMセルを更に備える、請求項13に記載の集積回路。
- 前記第1の1T−DRAMセル及び前記第2の1T−DRAMセルが2ビットのデータを蓄える、請求項16に記載の集積回路。
- 前記第1の1T−DRAMが、
ソ−ス領域と、
本体領域と、
ドレイン領域と、
を備え、
前記ソ−ス領域と、前記本体領域と、前記ドレイン領域とが、前記バルクICに隣接して設けられたドープアモルファスシリコン層内に形成されている、請求項1に記載の集積回路。 - 前記第1の1T−DRAMセルの前記ソース領域が、ニッケルを用いてシード形成された結晶化シリコンを備える、請求項18に記載の集積回路。
- 前記第1の1T−DRAMセルの前記ソース領域が、シード形成された結晶化シリコンのアイランドを備える、請求項18に記載の集積回路。
- 前記結晶化シリコンのアイランドと前記バルクICとが、共通の配向を有する、請求項20に記載の集積回路。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US78247906P | 2006-03-15 | 2006-03-15 | |
US11/674,008 US8008137B2 (en) | 2006-03-15 | 2007-02-12 | Method for fabricating 1T-DRAM on bulk silicon |
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JP2007294897A true JP2007294897A (ja) | 2007-11-08 |
JP2007294897A5 JP2007294897A5 (ja) | 2010-04-22 |
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JP2007067107A Pending JP2007294897A (ja) | 2006-03-15 | 2007-03-15 | バルクシリコン上に1t−dramを製造するための方法 |
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Country | Link |
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US (1) | US8008137B2 (ja) |
EP (1) | EP1835535A3 (ja) |
JP (1) | JP2007294897A (ja) |
CN (1) | CN101038919B (ja) |
TW (1) | TWI423422B (ja) |
Cited By (8)
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JP2012039101A (ja) * | 2010-07-16 | 2012-02-23 | Semiconductor Energy Lab Co Ltd | 半導体装置 |
JP2012256821A (ja) * | 2010-09-13 | 2012-12-27 | Semiconductor Energy Lab Co Ltd | 記憶装置 |
JP2012256835A (ja) * | 2011-01-26 | 2012-12-27 | Semiconductor Energy Lab Co Ltd | 半導体装置 |
US8378403B2 (en) | 2010-07-02 | 2013-02-19 | Semiconductor Energy Laboratory | Semiconductor device |
JP2014041689A (ja) * | 2010-04-07 | 2014-03-06 | Semiconductor Energy Lab Co Ltd | 半導体装置 |
JP2015029111A (ja) * | 2009-12-28 | 2015-02-12 | 株式会社半導体エネルギー研究所 | 半導体装置 |
JP2016213506A (ja) * | 2010-12-28 | 2016-12-15 | 株式会社半導体エネルギー研究所 | 半導体装置 |
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JP2012039101A (ja) * | 2010-07-16 | 2012-02-23 | Semiconductor Energy Lab Co Ltd | 半導体装置 |
US9042161B2 (en) | 2010-09-13 | 2015-05-26 | Semiconductor Energy Laboratory Co., Ltd. | Memory device |
JP2015146422A (ja) * | 2010-09-13 | 2015-08-13 | 株式会社半導体エネルギー研究所 | 記憶装置の作製方法 |
US9263116B2 (en) | 2010-09-13 | 2016-02-16 | Semiconductor Energy Laboratory Co., Ltd. | Memory device |
JP2016187047A (ja) * | 2010-09-13 | 2016-10-27 | 株式会社半導体エネルギー研究所 | 記憶装置 |
JP2012256821A (ja) * | 2010-09-13 | 2012-12-27 | Semiconductor Energy Lab Co Ltd | 記憶装置 |
US9954004B2 (en) | 2010-12-28 | 2018-04-24 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
JP2016213506A (ja) * | 2010-12-28 | 2016-12-15 | 株式会社半導体エネルギー研究所 | 半導体装置 |
JP2012256835A (ja) * | 2011-01-26 | 2012-12-27 | Semiconductor Energy Lab Co Ltd | 半導体装置 |
US9990965B2 (en) | 2011-12-15 | 2018-06-05 | Semiconductor Energy Laboratory Co., Ltd. | Storage device |
Also Published As
Publication number | Publication date |
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CN101038919A (zh) | 2007-09-19 |
EP1835535A3 (en) | 2010-07-14 |
EP1835535A2 (en) | 2007-09-19 |
TWI423422B (zh) | 2014-01-11 |
TW200742039A (en) | 2007-11-01 |
US20070215906A1 (en) | 2007-09-20 |
CN101038919B (zh) | 2012-01-04 |
US8008137B2 (en) | 2011-08-30 |
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