CN101038873A - 半导体装置的制造方法 - Google Patents
半导体装置的制造方法 Download PDFInfo
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- CN101038873A CN101038873A CNA2007100863716A CN200710086371A CN101038873A CN 101038873 A CN101038873 A CN 101038873A CN A2007100863716 A CNA2007100863716 A CN A2007100863716A CN 200710086371 A CN200710086371 A CN 200710086371A CN 101038873 A CN101038873 A CN 101038873A
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- Prior art keywords
- dielectric film
- hole
- etching
- film
- semiconductor device
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Abstract
本发明公开了一种半导体装置的制造方法,涉及用双层绝缘膜涂覆衬底的第一步骤和蚀刻所述绝缘膜的上层直到所述绝缘膜的下层的第二步骤,所述双层绝缘膜是具有无机材料的骨架结构的层叠结构。在制造半导体装置的该方法中,如此执行所述第一步骤使得所述骨架结构与碳氢化合物的孔形成材料结合,从而所述绝缘膜的一层包含比所述绝缘膜的另一层更多的碳。
Description
技术领域
本发明涉及制造半导体装置的方法,且更具体而言,涉及具有多孔绝缘膜的半导体装置的制造方法。
背景技术
最近比原来具有更高程度的集成和尺寸缩小的半导体装置造成了由于布线的时间常数所导致的电信号延迟的严重问题。该问题通过用低电阻率的铜(Cu)取代铝制造多层结构的布线解决。不幸的是,与过去的多层布线结构中使用的例如铝的其他金属性材料不同,铜难以进行用于构图的干法蚀刻。此缺点通过采用镶嵌法而克服,镶嵌法包含在绝缘膜中形成布线沟槽并在该布线沟槽中嵌入铜膜,因此形成布线图案。
上述步骤可以通过双镶嵌法更有效地实现,双镶嵌法包含形成通路孔和布线沟槽然后同时在其中嵌入铜。该方法因其有效减少了步骤的数目而引起关注。
高度集成的半导体装置由于布线之间增加的电容而变慢,因此,它们不可避免地需要精细的多层布线,通过所谓的低介电材料的层间绝缘膜,布线之间的电容保持得低。这样的材料的示例包括具有约3.5的介电常数的含氟氧化硅(FSG),以聚芳醚(polyarylether,PAE)为代表的有机聚合物和介电常数小于氧化硅的含碳氧化硅(SiOC)、含氢硅酸盐(hydrogen silsesquioxane,HSQ)和含甲基硅酸盐(methyl silsequioxane,MSQ)为代表的无机硅化合物。此外,进行尝试以通过使它们多孔而进一步减小它们的介电常数至大约2.3。
上述双镶嵌法通过如下步骤应用到具有低介电常数的层间绝缘膜:通过化学气相沉积(CVD)工艺在衬底上形成无机材料(SiOC)膜、通过涂覆在该无机膜上形成有机材料(PAE)膜、通过蚀刻在该有机膜中形成布线沟槽和在该无机膜中形成通路孔。如此形成的层结构具有在无机膜和有机膜之间的界面,且因此允许在良好控制下以前者对后者的高的蚀刻选择比进行蚀刻。(例如见日本特许公开No.2004-63859)。
此外,形成无机膜的CVD工艺自身可以容易地适应变化的条件(气体流速和RF功率)以应付膜质量的波动,且CVD工艺通常产生具有高机械强度的致密膜。
发明内容
然而,上述制造方法需要将衬底从用于CVD工艺来形成无机膜的一个设备移动到用于涂覆以形成有机膜的另一设备的额外步骤。此步骤对生产率来说是麻烦且有害的。具有如此优点的CVD工艺难以应用到作为其中形成布线沟槽的上层的绝缘膜的有机膜。不幸的是,多孔SiOC膜是介电常数可与有机膜相比的无机膜,但在蚀刻选择率上不与SiOC下层相匹配。这产生了不良的处理可控性的问题。
希望提供一种半导体装置的制造方法,该方法通过CVD工艺给出层叠膜使得上层比下层更容易进行蚀刻。
本发明的要点在于半导体装置的制造方法,涉及用双层绝缘膜涂覆衬底的第一步骤和蚀刻所述绝缘膜的上层直到所述绝缘膜的下层的第二步骤,所述双层绝缘膜是具有无机材料的骨架结构的层叠结构。在半导体装置的该制造方法中,如此执行所述第一步骤使得所述骨架结构与碳氢化合物的孔形成材料结合,从而所述绝缘膜的一层包含比所述绝缘膜的另一层更多的碳。
上述半导体装置的制造方法特征在于双绝缘膜之一在其骨架结构中包含碳氢化合物的孔形成材料,使得其具有比另一层更高的碳含量。具有更高碳含量的绝缘膜充当伪有机膜,产生在双绝缘膜之间(或伪有机膜和无机膜之间)的界面。所得的界面增加了第二步骤中的蚀刻中上层对下层的选择蚀刻比,该第二步骤在上层进行直到下层。因此,下绝缘膜充当停止层,因此提高制造可控性。此外,双绝缘膜具有无机材料的骨架结构,因此它们均能够通过CVD工艺形成。
根据本发明的方法允许对上绝缘层的蚀刻在良好控制下进行,这导致尺寸上精确的布线结构,布线材料嵌入在布线沟槽(在上绝缘膜中)和通路孔(在下绝缘膜中)中。此外,允许绝缘膜通过CVD工艺形成。CVD工艺可直接地适合于期望的膜质量的任何膜形成条件,因此对生产率有贡献,并且还产生具有高机械强度的致密膜。此外,能够连续形成双绝缘膜。
附图说明
图1是示出本发明的实施例中使用的CVD设备的结构的截面图;
图2是示出本发明的实施例中使用的电子束发射设备的结构的截面图;
图3A到3F是示出根据本发明的第一实施例的制造步骤的截面图;
图4是示出在本发明的第一实施例中的第二绝缘膜对第一绝缘膜的蚀刻选择比;
图5A到5D是示出在本发明的第一改进实施例中的制造步骤的截面图;
图6A到6F是示出根据本发明的第二实施例的制造步骤的截面图;
图7A到7D是示出在本发明的第三改进实施例中的制造步骤的截面图;
图8A到8D是示出在本发明的第四改进实施例中的制造步骤的截面图;
图9A到9L是示出根据本发明的第三实施例的制造步骤的截面图。
具体实施方式
将参考附图详细描述本发明的实施例。
第一实施例
根据本发明,用于制造半导体装置的方法采用CVD设备和电子束发射设备,首先参考图1和2(是截面图)解释这些设备。
图1所示的CVD设备1(其用于形成绝缘膜)具有反应腔2,膜在该反应腔中形成在衬底S的表面上。反应腔2具有连接到真空泵使其能够被排空的排气口(未示出)。
在反应腔2的底部是衬底支架3,衬底S放置在该支架上用于加工。衬底支架3还充当下电极以产生等离子体(后面提到),且它提供有加热衬底S的加热器。
在反应腔2的顶部是与衬底支架3相对的上电极4,该上电极4充当盖。上电极4提供有管(未示出),膜形成气体和运载气体通过该管提供到反应腔2。上电极4还在其与衬底支架3相对的整个表面中具有开口,气体通过该开口供应到放置于衬底支架3上的衬底S的表面。
操作上述CVD设备1以在衬底S表面上形成绝缘膜涉及如下步骤:将衬底S放置在反应腔2中的衬底支架3上;从上电极4中的气体供应开口供应膜形成气体;在电极之间施加电压,因此在衬底S上方产生等离子体P。如此产生的等离子体P引起其中的膜形成成分在衬底S的表面上形成绝缘膜。
为了分解并除去分散在绝缘膜中的孔形成材料(后面提到),此实施例采用包括反应腔6的电子束发射设备5,衬底S在该反应腔6中被照射电子束E。反应腔6在其底部具有衬底支架7,在该衬底支架7上放置衬底S,且该衬底支架7提供有加热衬底S的加热器(未示出)。
在反应腔6的顶部是电子束发射单元8,该电子束发射单元8朝放置在衬底支架7上的衬底S发射电子束E。
操作上述电子束发射设备5从而用电子束E照射衬底S的表面涉及如下步骤:将衬底S放置在反应腔6中的衬底支架7上和用电子束E照射衬底S的表面,其中衬底S上形成有绝缘膜,该绝缘膜包含孔形成材料。
根据此实施例,半导体装置通过图3A到3F(其是截面图)所示的步骤制造。制造步骤采用分别在图1和2示出的CVD设备和电子束发射设备。
图3A所示的制造的第一步骤涉及用骨架中含孔基(porogene)A’的无机材料的第一绝缘膜12涂覆衬底11。孔基A’是由骨架材料和碳氢化合物构成的孔形成材料。此步骤涉及使用含孔基A’的膜形成气体的等离子体增强型化学气相沉积(PE-CVD)。
具体地说,形成第一绝缘膜12的步骤开始于向CVD设备1(见图1)的反应腔2中引入衬底11(与衬底S相同),从而将衬底11放置在衬底支架3上然后加热衬底支架3,其中反应腔2被排空到13kPa以下。
接着,反应腔2被提供膜形成气体和运载气体氦(He),其中前者包含由二乙氧基甲基硅烷(diethoxymethylsilane,DEMS)和氧(O2)构成的骨架形成材料和孔基A’,该孔基A’例如可以是α-萜品烯(ATRP)。然后,等离子体P通过在衬底支架3和上电极4之间施加RF功率而产生。RF功率应该被控制,从而所得到的等离子体具有足够低的能量以防止孔基A’离解。此步骤典型地在气体流速比为DEMS∶O2∶ATRP∶He=1∶1∶2∶5,RF功率为500W,反应腔中的压强为7.0kPa,且衬底温度为250℃的条件下进行。
上述过程产生第一绝缘膜12,该第一绝缘膜12由无机材料(或者含碳氧化硅(SiOC))的骨架和以等离子体触发聚合物的形式分散在其中的孔基A’(ATRP)构成。
如此形成的第一绝缘膜12应该具有无机材料(不限于SiOC)的骨架,该无机材料具有低介电常数。在此步骤中使用的孔基A’不限于α-萜品烯(C10H16);其可以包括任何由CxHy代表的直链或分支的碳氢化合物以及由CxHyOz代表的含氧的碳氢化合物,其中x为1到12。此外,孔基A’应该优选地具有环状结构,类似苯和环己烷。
图3B所示的下一步骤涉及在衬底11的加热状态以电子束照射衬底11,用于从第一绝缘膜12分解和除去孔基A’。此步骤的结果是,图3A所示的第一绝缘膜12转变为具有孔A的第一多孔绝缘膜12A。此步骤开始于将其上形成有第一绝缘膜12的衬底11(与衬底S相同)放置在参考图2所述的电子发射设备5的反应腔6中的衬底支架7上。然后,衬底11的表面用从电子束发射单元8所发出的电子束E照射,衬底支架7在比如400℃被加热。
图3C所示的第三步骤涉及PE-CVD工艺,其在接收含骨架形成材料和碳氢化合物的孔基B’的膜形成气体时,在第一多孔绝缘膜12A上形成骨架中含孔基B’的无机材料的第二绝缘膜13。
如此形成的第二绝缘膜13包含碳氢化合物的孔基B’,且因此具有比第一多孔绝缘膜12A更高的碳含量。在第二绝缘膜13中孔基B’的含量高于第一绝缘膜12中孔基A’(图3A所示)的含量导致在第一多孔绝缘膜12A中更高的碳含量,这是所希望的。与孔基A’的情况一样,孔基B’可以是碳氢化合物。
第三步骤采用已经参考图1描述的CVD设备1。其开始于向反应腔2中引入膜形成气体和运载气体(He),前者由DEMS的骨架形成材料和ATRP的孔基B’构成,之后在衬底支架3和上电极4之间施加RF功率,以产生等离子体P。RF功率应该具有足够低的能量以防止孔基B’离解。此步骤的期望的条件是,气体流速为DEMS∶ATRP∶He=1∶6∶5,RF功率为500W,反应腔2中的压强为13kPa,且衬底温度为250℃。此条件不同于第一绝缘膜12的条件在于,第一绝缘膜12的条件中ATRP(孔基B’)与DEMS的比值高,且单独使用DEMS来形成骨架。结果是骨架具有更高的碳含量。
上述执行的第三步骤形成由无机材料的骨架和分散在其中的孔基B’构成的第二绝缘膜13。构成骨架的无机材料是具有比第一绝缘膜12更高碳含量的含碳氧化硅(SiOC)。孔基B’是已经被等离子体聚合的ATRP。如此形成的第二绝缘膜13包含的孔基B’比第一绝缘膜12包含的孔基A’更多。包含孔基B’,第二绝缘膜13是伪有机膜。
在图3D所示的第四步骤中,第二绝缘膜13通过预先形成在其上的第一掩模图案14进行蚀刻。此蚀刻形成穿透第二绝缘膜13并到达第一多孔绝缘膜12A的布线沟槽15。另外,第一掩模图案14应该由无机材料形成,例如氧化硅(SiO2),因为第二绝缘膜13是伪有机膜。
由于第二绝缘膜13中的碳氢化合物的孔基B’的高含量,上述蚀刻应该优选使用用于蚀刻含碳膜的氨(NH3)作为蚀刻气体。如此蚀刻的结果是第二绝缘膜13对第一多孔绝缘膜12A的高蚀刻选择比。期望的蚀刻条件的示例如下。蚀刻气体:NH3和O2;气体流速:NH3∶O2=30∶1;偏压功率:400W;和衬底温度:0℃。两种组分的蚀刻气体可以被单独的NH3取代。
如此蚀刻在第一多孔绝缘膜12A和第二绝缘膜13(其为伪有机膜)之间产生伪无机-有机界面。此界面有助于第二绝缘膜13对第一多孔绝缘膜12A的高蚀刻选择比。结果是对第二绝缘膜13的良好控制的蚀刻。第四步骤结束于除去第一掩模图案14。
图3E所示的第五步骤开始于用形成第二掩模图案16的光致抗蚀剂涂覆第二绝缘膜13。然后,暴露于布线沟槽15底部的第一多孔绝缘膜12A通过第二掩模图案16进行蚀刻。此蚀刻在第一多孔绝缘膜12A中形成连接孔17。蚀刻条件的示例如下。
蚀刻气体:八氟环丁烷(C4F8)、一氧化碳(CO)、氮(N2)和氩(Ar)的混合物;
气体流速:C4F8∶CO∶N2∶Ar=3∶10∶200∶500;
偏压功率:1000W;
衬底温度:20℃;
此步骤可以可选地包括除去第二掩模图案16。
图3F所示的第六步骤是用电子束照射,衬底11被加热,用于分解和除去包含在第二绝缘膜13中的孔基B’。结果是将图3E所示的第二绝缘膜13转化为具有孔B的第二多孔绝缘膜13B。此步骤涉及在电子束发射设备5的反应腔6中加热衬底支架7(例如在400℃),该衬底支架7上支持具有第二绝缘膜13的衬底11,并用从电子束发射单元8发出的电子束E照射衬底11例如五分钟。
此外,此实施例可以通过用紫外线照射取代电子束照射来在加热衬底21时分解和除去分别在第一绝缘膜12和第二绝缘膜13中的孔基A’和孔基B’而被改进。仅通过加热也将实现相同的效果。
上述步骤之后进行用导电材料填充布线沟槽15和连接孔17的完成步骤(未示出),因此形成连接到衬底11的通路和布线。
以上述方式制造半导体装置使得第二绝缘膜13包含比第一多孔绝缘膜12A更多的碳,因为在第一多孔绝缘膜12A上形成含孔基B’的第二绝缘膜13。结果是第二绝缘膜13对第一多孔绝缘膜12A的高蚀刻选择比。因此第一多孔绝缘膜12A充当停止层,允许布线沟槽15和连接孔17精确地形成。这依次会允许布线和通路分别在布线沟槽15和连接孔17中精确地形成。
用于形成第一绝缘膜12和第二绝缘膜13二者的CVD工艺可适应于应对膜质量波动。其给出具有高机械强度的致密膜并利于提高生产率。
同时,图4示出了第二绝缘膜13(或第二多孔绝缘膜13B)对第一多孔绝缘膜12A的蚀刻选择比,对此已经参考图3A到3F解释过。横坐标上的“参考”代表在400℃的加热条件下用电子束照射五分钟之后由第一绝缘膜12产生的第一多孔绝缘膜12A。类似地,(1)代表在400℃的加热条件下用电子束照射五分钟之后由第二绝缘膜13产生的第二多孔绝缘膜13B。(2)代表400℃的加热处理五分钟之后由第二绝缘膜13产生的第二多孔绝缘膜13B。(3)代表第二绝缘膜13。此三个膜的碳含量不同,使得(1)<(2)<(3)。通过以两种方式蚀刻而测量蚀刻选择比,一种是采用用于蚀刻含碳膜的NH3,另一种是使用用于蚀刻SiOC膜的O2和CxFy的组合。用NH3蚀刻显示了第二多孔绝缘膜13B(或第二绝缘膜13)对第一多孔绝缘膜12A的蚀刻选择比与碳含量成比例增加的迹象。作为对比,用含氧气体(例如O2和CO)和CxFy蚀刻显示了蚀刻选择比与碳含量成比例降低的迹象。这些结果证明了用O2和CxFy蚀刻给出第一多孔绝缘膜12A(具有低碳含量)对第二绝缘膜13或第二多孔绝缘膜13B(均具有高碳含量)的高蚀刻选择比。
与由“参考”表示的第一多孔绝缘膜12A相比,第二多孔绝缘膜13B在(1)中具有更高的蚀刻选择比。对此可能的原因是,当第一绝缘膜12和第二绝缘膜13在某条件下形成时第二绝缘膜12的骨架包含更多的碳,以及第二绝缘膜13中的孔基B’的含量高于第一绝缘膜12中的孔基A’的含量,并因此当在相同条件下进行移除步骤时孔基B’保持未被移除。
设计上述第一实施例来在第二绝缘膜13中形成布线沟槽15,然后在第一多孔绝缘膜12A中形成连接孔17。然而,还可能在第一多孔绝缘膜12A中形成连接孔17,然后在第二绝缘膜13中形成布线沟槽。
虽然上述第一实施例假设第二绝缘膜13下面的下层是多孔绝缘膜,但该下层可以被非多孔SiOC膜取代。在此情况,不需要用电子束照射第一绝缘膜12。这意味着CVD工艺可以用于连续形成第一绝缘膜12和第二绝缘膜13,因此进一步提高生产率。
改进的实施例1
上述第一实施例涉及蚀刻包含孔基B’且因此具有比第一多孔绝缘膜12高的碳含量的第二绝缘膜13的步骤。然而,可以将其改进使得对第二绝缘膜13进行蚀刻,第一绝缘膜12包含孔基A’且因此具有比第二绝缘膜13高的碳含量。
图5A所示的第一步骤开始于在衬底11上形成包含孔基A’的第一绝缘膜2,与第一实施例中参考图3C所述的第二绝缘膜13的方式相同。换言之,孔基A’是ATRP且选择适当的膜形成条件来防止孔基A’离解。随后,第一绝缘膜12被涂覆第二绝缘膜13,该第二绝缘膜13是非多孔SiOC膜。由于包含在其中的孔基A’,第一绝缘膜12具有比第二绝缘膜13高的碳含量,且因此其表现为类似伪有机膜。
在图5B所示的下一步骤中,第二绝缘膜13被涂覆抗蚀剂的第一掩模图案14,并通过掩模图案14进行直到第一绝缘膜12的蚀刻,从而布线沟槽15形成在第二绝缘膜13中。
此步骤中使用的蚀刻气体是含氧气体(例如O2和CO)和氟化碳(CxFy)的混合物。如参考图4所述的,该蚀刻气体对于具有低碳含量的无机膜给出了高的蚀刻选择比。蚀刻条件的示例如下。
蚀刻气体:C4F8、CO、N2和Ar的混合物;
气体流速:C4F8∶CO∶N2∶Ar=3∶10∶200∶500;
偏压功率:1000W;
衬底温度:20℃;
由于作为伪有机膜的第一绝缘膜12与作为无机膜的第二绝缘膜13之间的界面,如此的蚀刻具有第二绝缘膜13对第一绝缘膜12的高蚀刻选择比。因此,在良好控制下进行对第二绝缘膜13的蚀刻。蚀刻之后除去第一掩模图案14。
图5C所示的第三步骤涉及在第二绝缘膜13上形成SiO2等的第二掩模图案16,并通过第二掩模图案16对已经在布线沟槽15的底部暴露的第一多孔绝缘膜12A进行蚀刻,因此形成第一绝缘膜12中的连接孔17。蚀刻条件的示例如下:
蚀刻气体:NH3和O2的混合物;
气体流速:NH3∶O2=30∶1;
偏压功率:400W;
衬底温度:0℃;
蚀刻之后可以可选地除去第二掩模图案16。
图5D之后的第四步骤涉及在衬底21的加热状态用电子束照射,从而通过分解使第一绝缘膜12不含孔基A’。此步骤将第一绝缘膜12(图5C所示)转变为具有孔A的第一多孔绝缘膜12A。
用于制造半导体装置的上述方法还产生增加第二绝缘膜13对第一绝缘膜12的蚀刻选择比的效果,因为后者由于形成在含孔基A’的第一绝缘膜12上的SiOC的第二绝缘膜13而具有比前者更高的碳含量。结果,第一绝缘膜12充当停止层,允许用于布线沟槽15和连接孔17的良好控制的蚀刻。此外,CVD工艺可以用于形成第一绝缘膜12和第二绝缘膜13。总之,此改进版本产生于第一实施例的原始版本相同的效果。
此外,改进的实施例1可以如此改变从而用具有孔B的第二多孔绝缘膜13B取代SiOC的第二绝缘膜13,该第二多孔绝缘膜13B是在先前形成的含孔基B’的第二绝缘膜13通过分解而不含孔基B’时产生的。需要孔基B’具有比孔基A’低的离解能,从而形成第二多孔绝缘膜13B的步骤在只有孔基B’通过分解而被选择性地除去的条件下才执行。
改进实施例2
上述第一实施例(原始的)可以使其第三步骤(图3C所示)被修改,从而第二绝缘膜13如此形成:通过施加产生具有比孔基B’的离解能更高能量的等离子体的RF功率,而非施加调整来防止孔基B’离解的RF功率。如此产生的等离子体允许孔基B’的部分离解,因此产生具有贴附于其的碳(由离解产生)以及包含部分离解的孔基B’的SiOC的骨架。RF功率应该是800W到1500W。所得的第二绝缘膜13具有含高碳含量的骨架。这即使在第二绝缘膜13由于转变为第二多孔绝缘膜13B的离解而不含孔基B’的情况下也导致关于第一多孔绝缘膜12A的高蚀刻选择比。该第二多孔绝缘膜13B随后进行蚀刻以在其中形成布线沟槽15。此外,所得的第二绝缘膜13B由于其骨架结构具有贴附到其上的碳而具有高强度。
上述过程也适用于改进实施例1中参考图5A解释的步骤。换言之,第一绝缘膜12可以具有由SiOC构成且含有部分离解的孔基A’的骨架结构,由于具有比孔基A的离解能更高的能量的等离子体而导致孔基A’的部分离解产生具有贴附于其上的碳的骨架结构。
第二实施例
第二实施例在图6A到6F中示出,它们是截面图。旨在形成层叠结构的被蚀刻的多孔绝缘膜。
图6A和6B中所示的第一和第二步骤与第一实施例中参考图3A和3B解释的过程相同。第一步骤开始于用骨架结构含孔基A’的第一绝缘膜22涂覆衬底21。为了将第一绝缘膜22(图6A所示)转变为具有孔A的第一多孔绝缘膜22A(图6B所示),第二步骤涉及在衬底21的加热状态中用电子束照射,从而通过分解使第一绝缘膜22不含孔基A’。
图6C所示的第三步骤涉及PE-CVD以使用第二绝缘膜23涂覆第一多孔绝缘膜22,第二绝缘膜23由骨架形成材料、孔基B’(作为碳氢化合物的孔形成材料)和孔基C’(作为具有比孔基B’小的分子量的碳氢化合物的微孔形成材料)构成的气体形成。
孔基B’和孔基C’是由CxHy代表的碳氢化合物或者由CxHyOz代表的含氧的碳氢化合物,前者具有比后者大的碳数量。例如,孔基B’的碳氢化合物可以是碳数量为6到12的环形,而孔基C’的碳氢化合物的数量可以是具有1到5个碳数量(x)的那些。在此实施例中,孔基B’是ATRP,孔基C’是乙烯(C2H4)。还发现丙烯(C3H6)可用作孔基C’。应该选择适当的膜形成条件,适当控制RF功率以防止孔基C’离解,因为孔基C’具有比孔基B’低的离解能。
在CVD设备1(图1所示)中的反应腔2中进行膜形成工艺,该反应腔2被提供有DEMS作为骨架形成材料,ATRP作为孔基B’,乙烯作为孔基C’,且氦作为运载气体。反应腔2中的气体被施加在衬底支架3和上电极4之间的RF功率产生的等离子体P激发。第三步骤在下面条件下进行。
气体流速:DEMS∶ATRP∶C2H4∶He=1∶6∶2∶5
RF功率:500W
反应腔2中的压强:13kPa
衬底温度:250℃
如此的反应产生第二绝缘膜23,其SiOC的骨架包含分散在其中的已经被等离子体聚合的孔基B’和孔基C’。孔基B’的含量具有一极限,超过该极限,膜将不能形成。然而,即使当孔基B’的含量处于极限时,也可以添加具有比孔基B’低的分子量的孔基C’。因此,含孔基C’的膜形成气体产生碳含量比只含孔基B’的第二绝缘膜13高的第二绝缘膜23,在第一实施例中已经参考图3C解释了第二绝缘膜13。结果是第二绝缘膜23对第一多孔绝缘膜22A的更高的蚀刻选择比。
图6D所示的第四步骤涉及用SiO2的第一掩模图案24涂覆第二绝缘膜23,并通过此掩模图案蚀刻以在第二绝缘膜23中直到第一多孔绝缘膜22A形成布线沟槽25。此蚀刻在与第一实施例中参考图3D解释的步骤相同的条件下进行。
由于包含在其中的碳氢化合物的孔基B’和孔基C’,第二绝缘膜23充当伪有机膜,结果在第一多孔绝缘膜22A(作为伪无机膜)和第二绝缘膜23(作为伪有机膜)之间产生界面。该界面有助于第二绝缘膜23对第一多孔绝缘膜22A的高蚀刻选择比,且第一多孔绝缘膜22A充当停止层,允许在第二绝缘膜23上的良好控制的蚀刻。此蚀刻之后除去第二掩模图案24。
图6E所示的第五步骤涉及在第二绝缘膜23上形成抗蚀剂的第二掩模图案26,并通过此掩模图案对在布线沟槽25底部暴露的第一多孔绝缘膜22A进行蚀刻。此蚀刻在与第一实施例中参考图3E解释的步骤相同的条件下进行。此步骤在第一多孔绝缘膜22A中形成连接孔27。此蚀刻之后根据需要除去第二掩模图案26。
为了将第二绝缘膜23(图6E所示)转变为具有孔B和孔C(尺寸比孔B小)的第二多孔绝缘膜23B,图6F所示的第六步骤涉及在衬底21的加热状态用电子束照射,从而通过分解使第二绝缘膜23不含孔基B’和孔基C’。第二绝缘膜23由于其与第一实施例中参考图3C所述的仅包含孔基B’的第二绝缘膜13相比包含更多的孔基而具有更高的孔含量,且因此所得的第二多孔绝缘膜23B具有比图3F所示的第二多孔绝缘膜13B更低的介电常数。
通过用导电材料填充布线沟槽25和连接孔27并通过形成连接到衬底21的通路和互联而完成上述步骤。
如果第一多孔绝缘膜22A用含孔基B’和孔基C’的第二绝缘膜23涂覆(且因此包含比第一多孔膜22A更多的碳),则上述用于制造半导体装置的方法也产生提高第二绝缘膜23对第一多孔绝缘膜22A的蚀刻选择比的效果。此实施例中的第二绝缘膜23包含比第一实施例中预期的更多的碳,这有助于第一多孔绝缘膜22A的更高的蚀刻选择比,这允许布线沟槽25和连接孔27由良好控制的蚀刻形成。因此,布线沟槽25的布线和连接孔27的通路通过良好的尺寸控制性而形成。
此外,此实施例产生含有比第一实施例中的第二多孔绝缘膜13B(图3F所示)更多的孔的第二多孔绝缘膜23B。高的孔含量有助于进一步减小介电常数并因此减小布线电容。
由于此实施例采用CVD来形成第一绝缘膜22和第二绝缘膜23,所以其产生与第一实施例相同的效果。
改进实施例3
这是第二实施例的改进。图7A所示的第一步骤开始于用第二绝缘膜23涂覆第一多孔绝缘膜22A。图7B所示的第二步骤涉及在300℃热处理0.5小时以形成第二多孔绝缘膜23B’,其仅具有通过分解除去的孔基C’但包含由聚合的孔基B’导致的孔B”,该聚合的孔基B’的中心部分通过分解除去。
图7C所示的第三步骤涉及用第一掩模图案24涂覆第二多孔绝缘膜23B’并随后蚀刻以在第二多孔绝缘膜23B’中形成布线沟槽25。由于剩余的孔基B’,此蚀刻可能具有关于第一多孔绝缘膜22A的高的蚀刻选择比。由于第二多孔绝缘膜23B’具有孔C(其在低分子量的碳氢化合物通过分解除去之后剩下)和孔B”(其在聚合的孔基B’通过分解部分除去之后剩下),且孔B”具有小尺寸并被剩余的孔基B’围绕,对其的蚀刻比对孔基B’和C’完全除去的多孔膜的蚀刻引起较少的损坏。
图7D所示的第四步骤涉及在暴露于布线沟槽25底部的第一多孔绝缘膜22A中形成连接孔27,并在400℃进行额外的热处理0.5小时以通过分解除去剩余的孔基B’(见图7C)。此热处理将第二多孔绝缘膜23B’转变为具有形成在其中的孔的第二多孔绝缘膜23B。设计此改进的实施例在两阶段中除去孔基B’和孔基C’而完全除去它们。
上述用于制造半导体装置的方法还产生与第一实施例相同的效果,因为其涉及对含有比第一多孔绝缘膜22A更多碳的第二绝缘膜23的蚀刻且如此方式的蚀刻具有高的蚀刻选择比。
改进实施例4
上述涉及对第二绝缘膜23的蚀刻的第二实施例可以通过应用改进的实施例1而改进,考虑到含在其中的孔基B’和孔基C’,该第二绝缘膜23包括比第一多孔绝缘膜22A更多的碳。
根据改进的实施例4,图8A所示的第一步骤开始于在与上述第二改进实施例中图6C所示的第二绝缘膜23相同的条件下用含孔基A’和孔基C’的第一绝缘膜22涂覆衬底11。孔基A’是ATRP且孔基C’是C2H4。膜形成条件应该适合于防止孔基C’离解。上述步骤之后用第二绝缘膜23涂覆第一绝缘膜22,该第二绝缘膜23是非多孔SiOC膜。如此形成的含孔基A’的第一绝缘膜22具有比第二绝缘膜23高的碳含量,且因此其充当伪有机膜。SiOC的第二绝缘膜23可以被其中具有孔B的第二多孔绝缘膜23B取代,如在改进实施例1中一样。
通过与上述改进实施例1中相同的方式进行的图8B所示的第二步骤涉及用第一掩模图案24涂覆第二绝缘膜23,并通过第一掩模图案24蚀刻,从而在第二绝缘膜23中形成布线沟槽25(其到达第一绝缘膜22)。蚀刻条件与参考图5B所解释的改进实施例1中的相同。因为第二绝缘膜23与第一绝缘膜22之间(或伪有机膜和无机膜之间)的界面,此蚀刻显示了第二绝缘膜23对第一绝缘膜22的高蚀刻选择比;结果是第二绝缘膜23的良好控制的蚀刻。上述步骤之后进行第一掩模图案24除去。
图8C所示的第三步骤涉及用第二掩模图案26涂覆第二绝缘膜23,并通过第二掩模图案26蚀刻,从而在暴露于布线沟槽25底部的第一绝缘膜22中形成连接孔27。蚀刻条件与参考图5C解释的步骤相同。上述步骤之后根据需要除去第一掩模图案26。
图8D所示的第四步骤涉及在衬底21的加热状态用电子束照射,从而通过分解使得第一绝缘膜22没有孔基A’和孔基C’。此步骤将第一绝缘膜22(见图8C)转变为具有孔A的第一多孔绝缘膜22A。
因为由含孔基A’和孔基C’的第一绝缘膜22以及形成在其上的SiOC的第二绝缘膜23构成的特定层结构,所以上述用于制造半导体装置的方法还产生与第二实施例相同的效果。此层结构导致第一绝缘膜22中比第二绝缘膜23中更高的碳含量,因此导致了后者对前者的高蚀刻选择比。因此,第一绝缘膜22充当允许在良好控制下形成布线沟槽25和连接孔27的停止层。此外,CVD工艺可以用于形成第一绝缘膜22和第二绝缘膜23。
改进实施例5
上述第二实施例和改进实施例3设计为使得第二绝缘膜23由防止孔基C’离解的适当的RF功率形成。然而,它们可以被改进以控制RF功率从而产生比孔基C’的离解能高而比孔基B’的离解能低的能量的等离子体。所得的第二绝缘膜23具有含孔基B’并具有由离解的孔基C’产生的贴附于其的碳的骨架结构。随后通过分解去除孔基B’将第二绝缘膜23转变为具有孔B的第二多孔绝缘膜23B。结果是骨架由于贴附于其的离解的碳而具有高的碳含量。此高的碳含量导致高强度,且孔B有助于具有低介电常数的第二多孔绝缘膜23B。
此外,第二绝缘膜23还可以通过适当调整RF功率而形成,使得产生的等离子体具有比孔基B’的离解能更高的能量且因此不仅离解孔基C’而且离解部分孔基B’。因此,所得的第二绝缘膜23具有包含离解的碳和部分离解的孔基B’的骨架结构。最后,第二绝缘膜23不含孔基B’而转变为具有孔B的第二多孔绝缘膜23B。上述过程产生含孔基C’和部分离解的孔基B’的骨架结构。所得的第二多孔绝缘膜23B由于在其骨架结构中的高碳含量而具有高强度。
上述过程给出其骨架结构具有贴附于其的由孔基C’或孔基C’和部分离解的孔基B’产生的碳的第二绝缘膜23,上述过程的优点是即使将第二绝缘膜23制成多孔以转变为第二多孔绝缘膜23,所得的第二多孔绝缘膜23B也保持比第一多孔绝缘膜22A高的碳含量,这允许第一多孔绝缘膜22A的高蚀刻选择比。
上述内容也可以应用于改进实施例4中参考图7A解释的步骤。即,第一绝缘膜22可以通过适当调整RF功率而形成,使得产生的等离子体具有比孔基C’的离解能高且比孔基A’的离解能低的能量,且所得的第一绝缘膜22具有含有从孔基C’和孔基A’产生的碳的骨架结构。类似地,第二绝缘膜23可以通过适当调整RF功率而形成,使得所产生的等离子体具有比孔基A’的离解能高的能量,且其骨架结构包含有孔基C’和部分离解的孔基A’产生的碳。
第三实施例
图9A到9L(截面图)示出的第三实施例涉及应用本发明的双镶嵌法。此外,其基于上述参考图3A到3F所解释的第一实施例。
图9A中所示的第一步骤开始于用布线绝缘膜(为由PAE膜102和SiOC膜103构成的叠层)涂覆半导体衬底101(具有形成在其上的元件区(未示出))。涂覆步骤之后在布线绝缘膜中形成布线沟槽104并在布线沟槽104中形成嵌入的铜布线106,夹置有阻挡金属105。第一步骤结束于在铜布线106和SiOC膜103上形成SiC的蚀刻防止膜107。
图9B所示的第二步骤涉及:用其骨架包含孔基A’的第一绝缘膜108涂覆蚀刻防止膜107(与第一实施例中参考图3A到3C解释的过程相同),在衬底101的加热状态用电子束照射,因此通过分解使得第一绝缘膜108(见图9A)不含孔基A’以转变为含孔A的第一多孔绝缘膜108A,并用其骨架包含孔基B’的第二绝缘膜109涂覆第一多孔绝缘膜108A。
图9C所示的第三步骤涉及依次用氧化硅(SiO2)的第一掩模形成层201、氮碳化硅(SiCN)的第二掩模形成层202和氧化硅(SiO2)的第三掩模形成层203涂覆第二绝缘膜109。
在三个掩模形成层201到203中,SiO2的第一和第三掩模形成层201和203以甲硅烷(SiH4)作为硅源以及一氧化二氮(N2O)气体作为氧化剂通过PE-CVD而产生,且SiCN的第二掩模形成层202通过PE-CVD形成。第三掩模形成层203涂覆有具有布线沟槽图案的抗蚀剂掩模301。
图9D所示的第四步骤涉及通过第三掩模形成层203(见图9C)上的抗蚀剂掩模301的干法蚀刻,以形成具有布线沟槽图案的第三掩模203’,并用O2等离子体进行灰化以及使用有机胺化学处理以完全除去抗蚀剂掩模301和由蚀刻产生的剩余物。
图9E所示的第五步骤涉及用具有连接孔图案的抗蚀剂掩模302涂覆第二掩模形成层202(具有形成在其上的第三掩模203’)。抗蚀剂掩模302被如此构图使得其中的连接孔至少部分覆盖第三掩模203’的布线图案中的开口。
图9F所示的第六步骤涉及通过抗蚀剂掩模302(见图9E)依次对第三掩模203’、第二掩模形成层202(见图9E)、第一掩模形成层201(见图9E)和第二绝缘膜109进行干法蚀刻。此蚀刻允许第二绝缘膜109对第一多孔绝缘膜108A的高的蚀刻选择比,因为前者包含以聚合形式分散在其中的孔基B’且后者充当停止层。此步骤产生连接孔303,第一多孔绝缘膜108A通过该孔暴露。
在第六步骤中的蚀刻还去除抗蚀剂掩模302,同时留下充当布线沟槽图案的掩模的第三掩模203’。对第二掩模形成层202的蚀刻形成第二掩模202’,该第二掩模202’充当连接图案的掩模。
上述对第三掩模(SiO2)203’到第一掩模形成层(SiO2)201的蚀刻通过使用普通的磁控管蚀刻设备在下述条件下完成。
蚀刻气体:三氟代甲烷(CHF3)、氧(O2)和氩(Ar)
气体流速:CHF3∶O2∶Ar=5∶1∶50
偏压功率:1000W
衬底温度:40℃
对下面的第二绝缘层109的蚀刻也通过使用普通的磁控管蚀刻设备在下述条件下完成。
蚀刻气体:NH3和O2
气体流速:NH3∶O2=30∶1
偏压功率:400W
衬底温度:0℃
图9G所示的第七步骤涉及通过第三掩模(SiO2)203’对第二掩模(SiCN)202’上的干法蚀刻。被蚀刻的第二掩模202’充当布线沟槽图案的掩模。第一掩模形成层201(见图9E)转变为具有形成在其上的连接孔图案的第一掩模201’。在此步骤中的蚀刻将第一多孔绝缘膜108A(暴露于连接孔303底部)挖掘到其中部,因此加深了连接孔303。
图9H所示的第八步骤涉及通过第一掩模(SiO2)201’对第一多孔绝缘膜108A的下层的蚀刻,因此进一步挖掘连接孔303以将蚀刻停止膜107暴露。此步骤还涉及通过第三掩模(SiO2)203’(见图9G)和第二掩模(SiCN)202’对第一掩模(SiO2)201’的蚀刻,因此在第一掩模201’中形成布线沟槽304。
上述蚀刻通过使用普通的磁控管蚀刻设备在下述条件下进行。
蚀刻气体:八氟环丁烷(C4F8),一氧化碳(CO),氮(N2)和氩(Ar)
气体流速:C4F8∶CO∶N2∶Ar=3∶10∶200∶500
偏压功率:1000W
衬底温度:20℃
图9I所示的第九步骤涉及通过第二掩模(SiCN)202’对含孔基B’的第二绝缘膜109的蚀刻,其中该第二绝缘膜109保持在布线沟槽304底部。此蚀刻进一步挖掘形成在第一掩模201’中的布线沟槽304,因此在第一掩模201’和第二绝缘膜109中形成布线沟槽304。此蚀刻允许第二绝缘膜109对第一多孔绝缘膜108A的高的蚀刻选择比,因为前者包含以聚合形式分散在其中的孔基B’且后者充当停止层。
前述蚀刻通过使用普通磁控管蚀刻设备在下述条件下完成。
蚀刻气体:NH3和O2
气体流速:NH3∶O2=30∶1
偏压功率:400W
衬底温度:0℃
对保持在连接孔303底部的蚀刻停止膜107连续进行蚀刻,从而允许在布线沟槽304底部敞开的连接孔303与下布线106联通。如此完成双镶嵌工艺。此蚀刻通过使用普通磁控管蚀刻设备在下述条件下完成。
蚀刻气体:二氟代甲烷(CH2F2),氧(O2)和氩(Ar)
气体流速:CH2F2∶O2∶Ar=2∶1∶5
偏压功率:100W
为了将第二绝缘膜109(见图9I)转变为具有孔B的第二多孔绝缘膜109B,图9J所示的第十步骤涉及在衬底101的加热状态用电子束照射,以通过分解形成不含孔基B’的第二绝缘膜109。
随后进行普通的镶嵌工艺。即,图9K所示的第十一步骤涉及溅射以形成钽的阻挡金属305和电解铜镀覆或者溅射以使用铜导电膜306填充布线沟槽304和连接孔303。
图9L所示的第十二步骤涉及化学机械研磨(CMP)以除去导电部分306(见图9K)外的布线图案不需要的那些部分(保留在第一掩模201’上方),并在连接孔303中形成通路307以在布线沟槽304中形成布线308。此步骤通过在第一掩模201’上和布线308顶部形成SiC的停止膜309而结束。
重复图9A到9L所示的上述步骤以形成双镶嵌结构的多层布线结构。
制造半导体装置的上述方法产生与第一实施例相同的效果,因为第一多孔绝缘膜108A涂覆有含孔基B’的第二绝缘膜109,使得其包含比第一多孔绝缘膜108A更多的碳,且所得的第二绝缘膜109具有对第一多孔绝缘膜108A的高的蚀刻选择比。另外的原因是可以应用CVD工艺以形成第一绝缘膜108和第二绝缘膜109。
本领域的技术人员将理解,根据设计需要和其他因素可以进行各种改进、组合、子组合和替换,只要它们落入权利要求或其等同特征的范围内。
本发明专利申请要求于2006年3月15日在日本专利局提交的日本专利申请JP 2006-070272的优先权,将其整个内容引用结合于此。
Claims (8)
1、一种半导体装置的制造方法,涉及用双层绝缘膜涂覆衬底的第一步骤和蚀刻所述绝缘膜的上层直到所述绝缘膜的下层的第二步骤,所述双层绝缘膜是具有无机材料的骨架结构的层叠结构,
其中如此执行所述第一步骤使得所述骨架结构与碳氢化合物的孔形成材料结合,从而所述绝缘膜的一层包含比所述绝缘膜的另一层更多的碳。
2、根据权利要求1所述的半导体装置的制造方法,其中所述第二步骤之后,进行通过分解使所述绝缘膜的一层没有孔形成材料的步骤,因此在所述绝缘膜中形成孔。
3、根据权利要求1所述的半导体装置的制造方法,其中所述无机材料是含碳硅。
4、根据权利要求1所述的半导体装置的制造方法,其中进行所述第一步骤以形成所述绝缘膜的一层,使得所述孔形成材料结合到包含贴附于其的碳的骨架结构中,所述碳由所述孔形成材料的部分离解产生。
5、根据权利要求1所述的半导体装置的制造方法,其中进行所述第一步骤,使得所述骨架结构与所述碳氢化合物的孔形成材料和微孔形成材料结合,所述微孔形成材料具有比所述孔形成材料小的分子量。
6、根据权利要求5所述的半导体装置的制造方法,其中所述第一和第二步骤由如下步骤分隔:使所述绝缘膜的一层通过分解而不含所述微孔形成材料和通过分解而部分不含所述孔形成材料,因此在所述绝缘膜的所述层中形成孔,并使其成为多孔的;且
所述第二步骤之后进行通过分解除去剩余的所述孔形成材料的步骤。
7、根据权利要求5所述的半导体装置的制造方法,其中进行所述第一步骤以形成所述绝缘膜的一层,使得所述孔形成材料结合在包含贴附于其的碳的骨架结构中,所述碳由所述孔形成材料的离解产生。
8、根据权利要求1所述的半导体装置的制造方法,其中所述第二步骤涉及采用所述绝缘膜的下层作为停止层的图案蚀刻,因此在所述绝缘膜的上层中制作布线沟槽,并且所述第二步骤还涉及在暴露于所述布线沟槽底部的绝缘膜的下层上的图案蚀刻,因此在所述绝缘膜的下层中制作连接孔。
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JP (1) | JP4788415B2 (zh) |
KR (1) | KR101354413B1 (zh) |
CN (1) | CN100485882C (zh) |
TW (1) | TWI338347B (zh) |
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JP5173863B2 (ja) * | 2009-01-20 | 2013-04-03 | パナソニック株式会社 | 半導体装置およびその製造方法 |
JP5671220B2 (ja) * | 2009-08-25 | 2015-02-18 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
CN102339741B (zh) * | 2010-07-22 | 2013-09-18 | 中芯国际集成电路制造(上海)有限公司 | 化学机械研磨方法 |
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CN102891080B (zh) * | 2011-07-18 | 2015-10-14 | 中芯国际集成电路制造(上海)有限公司 | 介质层的形成方法 |
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CN105826237A (zh) * | 2015-01-06 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | 互连结构及其形成方法 |
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JP2007250706A (ja) | 2007-09-27 |
JP4788415B2 (ja) | 2011-10-05 |
TW200810013A (en) | 2008-02-16 |
KR101354413B1 (ko) | 2014-01-22 |
CN100485882C (zh) | 2009-05-06 |
KR20070093920A (ko) | 2007-09-19 |
US8759222B2 (en) | 2014-06-24 |
TWI338347B (en) | 2011-03-01 |
US20080254631A1 (en) | 2008-10-16 |
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