CN100555461C - 高速可写半导体存储器装置 - Google Patents
高速可写半导体存储器装置 Download PDFInfo
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- CN100555461C CN100555461C CNB2006101310142A CN200610131014A CN100555461C CN 100555461 C CN100555461 C CN 100555461C CN B2006101310142 A CNB2006101310142 A CN B2006101310142A CN 200610131014 A CN200610131014 A CN 200610131014A CN 100555461 C CN100555461 C CN 100555461C
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Images
Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5628—Programming or writing circuits; Data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5642—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
- G11C16/3445—Circuits or methods to verify correct erasure of nonvolatile memory cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
- G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/021—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in voltage or current generators
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/562—Multilevel memory programming aspects
- G11C2211/5621—Multilevel programming verification
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/564—Miscellaneous aspects
- G11C2211/5642—Multilevel memory with buffers, latches, registers at input or output
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/564—Miscellaneous aspects
- G11C2211/565—Multilevel memory comprising elements in triple well structure
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Read Only Memory (AREA)
Abstract
Description
Claims (20)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005371125A JP5065594B2 (ja) | 2005-12-23 | 2005-12-23 | 半導体記憶装置 |
JP371125/2005 | 2005-12-23 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101060013A CN101060013A (zh) | 2007-10-24 |
CN100555461C true CN100555461C (zh) | 2009-10-28 |
Family
ID=38193519
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2006101310142A Active CN100555461C (zh) | 2005-12-23 | 2006-12-22 | 高速可写半导体存储器装置 |
Country Status (4)
Country | Link |
---|---|
US (1) | US7554862B2 (zh) |
JP (1) | JP5065594B2 (zh) |
KR (1) | KR100858178B1 (zh) |
CN (1) | CN100555461C (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105637196A (zh) * | 2013-10-25 | 2016-06-01 | 艾克莫特公司 | 电控涡轮机的转子的保持 |
Families Citing this family (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3935139B2 (ja) | 2002-11-29 | 2007-06-20 | 株式会社東芝 | 半導体記憶装置 |
US7499345B2 (en) * | 2005-11-25 | 2009-03-03 | Giovanni Campardo | Non-volatile memory implemented with low-voltages transistors and related system and method |
DE602006016230D1 (de) * | 2006-03-17 | 2010-09-30 | St Microelectronics Srl | Mit Niederspannungstransistoren implementierter Pegelschieber für eine Halbleiterspeichervorrichtung |
US7652918B2 (en) * | 2006-12-28 | 2010-01-26 | Sandisk Corporation | Retention margin program verification |
JP5178167B2 (ja) * | 2007-12-04 | 2013-04-10 | 株式会社東芝 | 半導体記憶装置及びそのデータ書き込み方法 |
JP2009230818A (ja) | 2008-03-24 | 2009-10-08 | Toshiba Corp | 半導体記憶装置 |
KR100956776B1 (ko) * | 2008-04-18 | 2010-05-12 | 주식회사 하이닉스반도체 | 네거티브 전압 생성 장치 |
JP5377131B2 (ja) | 2009-07-17 | 2013-12-25 | 株式会社東芝 | 半導体記憶装置 |
US8233324B2 (en) | 2010-03-25 | 2012-07-31 | Sandisk Il Ltd. | Simultaneous multi-state read or verify in non-volatile storage |
KR101131945B1 (ko) * | 2010-07-07 | 2012-03-29 | 주식회사 하이닉스반도체 | 비휘발성 메모리 장치 |
US8559229B2 (en) * | 2010-09-30 | 2013-10-15 | Samsung Electronics Co., Ltd. | Flash memory device and wordline voltage generating method thereof |
KR101682189B1 (ko) * | 2011-01-04 | 2016-12-05 | 삼성전자주식회사 | 플래시 메모리 장치 및 그것의 워드라인 전압 발생 방법 |
DE102011056141A1 (de) * | 2010-12-20 | 2012-06-21 | Samsung Electronics Co., Ltd. | Negativspannungsgenerator, Dekoder, nicht-flüchtige Speichervorrichtung und Speichersystem, das eine negative Spannung verwendet |
FR2981190B1 (fr) * | 2011-10-06 | 2014-03-21 | St Microelectronics Rousset | Circuit d'ecoulement de charges electriques pour une mesure temporelle |
JP2014127220A (ja) * | 2012-12-27 | 2014-07-07 | Toshiba Corp | 半導体記憶装置 |
CN105518795B (zh) * | 2013-09-13 | 2019-08-13 | 东芝存储器株式会社 | 半导体存储装置以及存储系统 |
KR102243497B1 (ko) | 2014-07-22 | 2021-04-23 | 삼성전자주식회사 | 불 휘발성 메모리 장치 및 그것의 프로그램 방법 |
KR102294352B1 (ko) * | 2015-04-20 | 2021-08-26 | 삼성전자주식회사 | 불휘발성 메모리 장치 및 그것의 프로그램 방법과 독출 방법 |
CN108733305B (zh) * | 2017-04-13 | 2021-09-03 | 旺宏电子股份有限公司 | 存储器装置、系统及其操作方法 |
KR102490567B1 (ko) | 2018-03-27 | 2023-01-20 | 에스케이하이닉스 주식회사 | 디스터번스를 방지하는 반도체 메모리 장치 |
US10535401B2 (en) | 2018-06-05 | 2020-01-14 | Sandisk Technologies Llc | Dynamic bit-scan techniques for memory device programming |
US20210134369A1 (en) * | 2019-10-30 | 2021-05-06 | Sandisk Technologies Llc | Method for concurrent programming |
US11081184B2 (en) | 2019-10-30 | 2021-08-03 | Sandisk Technologies Llc | Method of concurrent multi-state programming of non-volatile memory with bit line voltage step up |
US11423993B2 (en) * | 2019-11-06 | 2022-08-23 | Sandisk Technologies Llc | Bi-directional sensing in a memory |
JP6966587B2 (ja) * | 2020-03-02 | 2021-11-17 | ウィンボンド エレクトロニクス コーポレーション | 半導体記憶装置および読出し方法 |
CN111785308B (zh) * | 2020-06-10 | 2021-09-10 | 芯天下技术股份有限公司 | 减少非型闪存编程泵面积的方法、系统、储存介质和终端 |
US20220375952A1 (en) * | 2021-05-18 | 2022-11-24 | Silicon Storage Technology, Inc. | Non-volatile memory cell array formed in a p-well in a deep n-well in a p-substrate |
JP2023045252A (ja) * | 2021-09-21 | 2023-04-03 | キオクシア株式会社 | 半導体記憶装置 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3197119B2 (ja) * | 1993-06-30 | 2001-08-13 | 株式会社東芝 | 不揮発性半導体記憶装置 |
JPH1145986A (ja) * | 1997-07-28 | 1999-02-16 | Sony Corp | 不揮発性半導体記憶装置 |
JPH11186419A (ja) * | 1997-12-25 | 1999-07-09 | Toshiba Corp | 不揮発性半導体記憶装置 |
KR100295150B1 (ko) * | 1997-12-31 | 2001-07-12 | 윤종용 | 비휘발성메모리장치의동작방법과상기동작을구현할수있는장치및그제조방법 |
JP3999900B2 (ja) * | 1998-09-10 | 2007-10-31 | 株式会社東芝 | 不揮発性半導体メモリ |
JP2000294658A (ja) | 1999-04-02 | 2000-10-20 | Matsushita Electronics Industry Corp | 不揮発性半導体記憶装置及びその駆動方法 |
JP4579493B2 (ja) | 2000-08-03 | 2010-11-10 | スパンション エルエルシー | 不揮発性半導体記憶装置及びデータ読出し方法 |
KR100390955B1 (ko) * | 2001-06-28 | 2003-07-12 | 주식회사 하이닉스반도체 | 낸드-타입 메모리 어레이 및 이를 이용한 독출, 프로그램및 소거 방법 |
JP3935139B2 (ja) | 2002-11-29 | 2007-06-20 | 株式会社東芝 | 半導体記憶装置 |
JP4213532B2 (ja) * | 2003-07-15 | 2009-01-21 | 株式会社東芝 | 不揮発性半導体記憶装置 |
-
2005
- 2005-12-23 JP JP2005371125A patent/JP5065594B2/ja not_active Expired - Fee Related
-
2006
- 2006-12-12 US US11/609,503 patent/US7554862B2/en active Active
- 2006-12-21 KR KR1020060131594A patent/KR100858178B1/ko active IP Right Grant
- 2006-12-22 CN CNB2006101310142A patent/CN100555461C/zh active Active
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105637196A (zh) * | 2013-10-25 | 2016-06-01 | 艾克莫特公司 | 电控涡轮机的转子的保持 |
Also Published As
Publication number | Publication date |
---|---|
US7554862B2 (en) | 2009-06-30 |
CN101060013A (zh) | 2007-10-24 |
KR100858178B1 (ko) | 2008-09-10 |
KR20070066911A (ko) | 2007-06-27 |
JP5065594B2 (ja) | 2012-11-07 |
JP2007172769A (ja) | 2007-07-05 |
US20070147141A1 (en) | 2007-06-28 |
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TR01 | Transfer of patent right |
Effective date of registration: 20170803 Address after: Tokyo, Japan Patentee after: TOSHIBA MEMORY Corp. Address before: Tokyo, Japan Patentee before: Toshiba Corp. |
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Address after: Tokyo, Japan Patentee after: TOSHIBA MEMORY Corp. Address before: Tokyo, Japan Patentee before: Japanese businessman Panjaya Co.,Ltd. Address after: Tokyo, Japan Patentee after: Kaixia Co.,Ltd. Address before: Tokyo, Japan Patentee before: TOSHIBA MEMORY Corp. |
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Effective date of registration: 20220112 Address after: Tokyo, Japan Patentee after: Japanese businessman Panjaya Co.,Ltd. Address before: Tokyo, Japan Patentee before: TOSHIBA MEMORY Corp. |
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