CN100485910C - 电子元器件及其制造方法 - Google Patents

电子元器件及其制造方法 Download PDF

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CN100485910C
CN100485910C CNB2005800407411A CN200580040741A CN100485910C CN 100485910 C CN100485910 C CN 100485910C CN B2005800407411 A CNB2005800407411 A CN B2005800407411A CN 200580040741 A CN200580040741 A CN 200580040741A CN 100485910 C CN100485910 C CN 100485910C
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components
electronic devices
ceramic
covering member
circuit board
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CN101065842A (zh
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西泽吉彦
池田哲也
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Murata Manufacturing Co Ltd
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Murata Manufacturing Co Ltd
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    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Organic Chemistry (AREA)
  • Structural Engineering (AREA)
  • Materials Engineering (AREA)
  • Electromagnetism (AREA)
  • Inorganic Chemistry (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
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Abstract

如专利文献1所述，若随着混合IC等电子元器件进一步降低高度，而减薄屏蔽壳，则由于屏蔽壳是金属制的，因此难以高精度地对它进行弯折等加工，另外由于吸取时作用的外力，使屏蔽壳的变形显著。在专利文献2所述的技术中，由于陶瓷制的盖罩形成为箱型形状，因此若为了电子元器件降低高度，而减薄盖罩的陶瓷厚度，则例如图18(a)、(b)所示，顶部2A产生弯曲。本发明的电子元器件10包括；具有布线图形14的布线基板11；安装在布线基板11的上表面的表面安装元器件12；以及覆盖布线基板11的盖罩13，盖罩13包括；利用平板状的陶瓷构件形成的顶部13A；以及利用具有与表面安装元器件12相同程度的高度的柱状构件而形成的脚部13B。

Description

电子元器件及其制造方法
技术领域
本发明涉及用覆盖构件覆盖安装在布线基板上的表面安装元器件的电子元器件及其制造方法，更详细地说，涉及改进覆盖构件结构、能够促进小型化及降低高度的电子元器件及其制造方法。
背景技术
作为以往的这种技术，有专利文献1～专利文献3中提出的技术。
在专利文献1中，提出了在陶瓷基板上安装金属制的屏蔽壳的混合IC。该混合IC包括；具有布线图形的陶瓷基板；以及在陶瓷基板的单面或双面上进行表面安装的微型计算机、晶体管、IC等电子元器件。陶瓷基板具有从外周边缘向垂直下方延伸的多个连接端。另外，在陶瓷基板的上表面安装将矩形板的两端弯折形成的金属制的屏蔽壳，利用该屏蔽壳，屏蔽掉外来干扰。该屏蔽壳还具有作为将混合IC向母板吸取时的吸附面的作用。
在专利文献2中，提出了包括具有箱型形状的陶瓷制覆盖构件的半导体芯片用陶瓷组件。该半导体芯片用陶瓷组件具有安装半导体芯片的陶瓷制的组件基体、以及与组件基体粘接的陶瓷制覆盖构件而构成。在该覆盖构件的内表面设置镀铜层，在封接面通过镀铜层设置封接用焊锡层，封接面的镀铜层与内表面的镀铜层电连接。然后，在组件基体的封接面设置接地电极，在通过覆盖构件的封接用焊锡层封接组件基体时，将覆盖构件的封接面的镀铜层与组件基体的接地电极电连接，形成接地电极层，覆盖构件的内表面的镀铜层形成电磁屏蔽层。
在专利文献3中，提出了半导体器件的封接用覆盖构件及其制造方法。该封接用覆盖构件形成作为由多个陶瓷层构成的多层结构，在内层利用糊料的全面印刷，形成屏蔽层。在陶瓷覆盖构件的正面及反面中，将反面和与其相对的基板本体利用接合糊料进行接合，通过这样将基板本体的空腔封接。在陶瓷覆盖构件的正反两面能够分别安装芯片元器件。
专利文献1；特开平6-350280号公报
专利文献2；特开平8-250615号公报
专利文献3；特开平11-354663号公报
但是，在专利文献1所述的技术中，若随着混合IC等电子元器件进一步降低高度，而减薄屏蔽壳，则存在的问题是，由于屏蔽壳是金属制的，因此难以高精度地对它进行弯折等加工，另外由于吸取时作用的外力，使屏蔽壳的变形显著。特别是若屏蔽壳的变形显著，则一般如图17(a)所示，在进行电子元器件1的特性分选时，使用夹具J对电子元器件1从屏蔽壳2的上面施加载荷，如图17(b)所示，使电子元器件1的基板本体3的反面形成的端子电极4与测试设备的测试用端子P电接触，但因这时的载荷作用，屏蔽壳2的上面挠曲，从而有可能屏蔽壳2与芯片元器件等要素元器件5接触，产生短路。另外，由于屏蔽壳2与要素元器件5的距离变化，而引起要素元器件5的特性值变化，进而难以正确测定电子元器件1的特性值，有的情况下，往往将合格品作为不合格品去掉，或者将不合格品作为合格品上市。为了避免这样的事态发生，虽然也考虑在屏蔽壳2的内侧形成薄的树脂膜作为绝缘层，但为了形成树脂膜，则制造成本增大，或者有可能树脂膜产生剥离等，使电子元器件的可靠性降低。
另外，在专利文献2所述的技术中，由于陶瓷制的覆盖构件形成为箱型形状，因此若为了电子元器件降低高度，而减薄覆盖构件的陶瓷厚度，则例如图18(a)、(b)所示，由于烧成时的箱型形状覆盖构件2的顶部2A与外周壁部2B在面方向的收缩动作差异，而在顶部2A产生起伏波纹。由于该起伏波纹，作为覆盖构件2的顶部2A的实质上的厚度没有减少，进而不能进一步使电子元器件降低高度，另外在将电子元器件安装到母板上时，由于覆盖构件2的顶部2A不平坦，因此在吸取时，难以通过覆盖构件2来吸附电子元器件，容易产生安装不好的情况。另外，图18(a)为将多个覆盖构件一次制造时的部分剖视图，图18(b)为切断成一个个覆盖构件时的剖视图。
另外，在专利文献3所述的技术中，是利用平板状覆盖构件封接电子元器件的空腔部分用的技术，对于没有空腔的电子元器件就不能适用。即，在这种情况下，为了使用覆盖构件，必须在布线基板侧形成空腔，制造工序复杂，导致成本提高。再有，在对覆盖构件安装芯片元器件的情况下，要在对覆盖构件安装元器件时及在对布线基板安装覆盖构件时必须经过两次焊接，进行回流焊。然而，在对布线基板安装覆盖构件时，安装在覆盖构件上的芯片元器件因焊锡再熔融而掉下，或者断线，有的情况下因焊锡的再晶化而进一步导致合金化或脆性化，焊锡连接处的可靠性显著降低。
本发明正是为了解决上述问题而提出的，其目的在于提供一种具有覆盖构件的电子元器件及其制造方法，它能够以薄的厚度而且高精度进行制造，同时对布线基板的安装精度高，而且能够进一步降低高度。
发明内容
本发明的第1方面所述的电子元器件，包括：具有布线图形的布线基板；安装在该布线基板的主表面上的表面安装元器件；以及覆盖该表面安装元器件的覆盖构件，上述覆盖构件包括：利用平板状的陶瓷构件形成的顶部；以及利用至少具有在上述表面安装元器件的高度以上的高度的柱状构件形成的脚部，上述柱状构件是柱状金属，该柱状金属与上述平板状的陶瓷构件通过同时烧成而形成一体化。
本发明的第2方面所述的电子元器件，是在第1方面所述的发明中，上述顶部具有将多个陶瓷层进行层叠而构成的多层结构，而且在其内层部分及/或外侧表面部分配置屏蔽电极层，上述屏蔽电极层通过设置在上述陶瓷层的通路导体，与上述柱状金属连接。
本发明的第3方面所述的电子元器件，是在第2方面所述的发明中，上述屏蔽电极层与上述柱状金属通过同时烧成而形成一体化。
本发明的第4方面所述的电子元器件，是在第2或第3方面所述的发明中，上述屏蔽电极层中在至少与一个上述表面安装元器件相对的部分形成开口部。
本发明的第5方面所述的电子元器件，是在第1至第3方面的任一项所述的发明中，上述顶部具有将多个陶瓷层进行层叠而构成的多层结构，而且在其内层部分及/或内侧表面部分及/或外侧表面部分配置厚膜电阻体，上述厚膜电阻体通过设置在上述陶瓷层的通路导体，与上述柱状金属连接。
本发明的第6方面所述的电子元器件，是在第5方面所述的发明中，上述顶部在其内层部分及/或外侧表面部分配置屏蔽电极层，上述屏蔽电极层中在与上述厚膜电阻体相对的部分形成开口部。
本发明的第7方面所述的电子元器件，是在第1至第3方面的任一项所述的发明中，在上述顶部设置将陶瓷烧结体作为坯体、而且具有端子电极的片状陶瓷电子元器件，该片状陶瓷电子元器件的至少一部分埋入上述顶部。
本发明的第8方面所述的电子元器件，是在第1至第3方面的任一项所述的发明中，上述布线基板形成作为将多个第1低温共烧陶瓷层进行层叠而构成的陶瓷多层基板，在其内层具有以银或铜为主要成分的布线图形。
本发明的第9方面所述的电子元器件，是在第8方面所述的发明中，上述顶部具有将多个第2低温共烧陶瓷层进行层叠而构成的层叠结构，该第2低温共烧陶瓷层与上述第1低温共烧陶瓷层由相同的材料组成。
另外，本发明的第10方面所述的电子元器件的制造方法，包括以下工序：制造具有布线图形的布线基板的工序；制造具有平板状的顶部、与该顶部形成一体化而且由该顶部沿垂直方向延伸的柱状构件构成的脚部的覆盖构件的工序；以及将上述覆盖构件重叠在布线基板的主表面上、并通过上述脚部与上述布线基板连接的工序，制造上述覆盖构件的工序包括：制造以低温共烧陶瓷为主要成分、而且在内层部分及/或表面部分具有未烧成屏蔽电极层的顶部用陶瓷未烧成体的工序；制造以在上述低温共烧陶瓷的烧成温度下不烧结的难烧结陶瓷为主要成分、而且具有成为上述柱状构件的未烧成柱状构件的收缩抑制用陶瓷未烧成体的工序；在上述顶部用陶瓷未烧成体的一个主表面上重叠上述收缩抑制用陶瓷未烧成体的工序；将这两个陶瓷未烧成体用上述低温共烧陶瓷的烧成温度进行烧成、使上述顶部用陶瓷未烧成体进行烧结同时使上述未烧成屏蔽电极层与上述未烧成柱状构件通过同时烧结而形成一体化的工序；以及除去上述收缩抑制用陶瓷未烧成体的工序。
另外，本发明的第11方面所述的电子元器件的制造方法，是在第10方面所述的发明中，上述顶部具有将多个陶瓷层进行层叠而构成的多层结构，在其内层部分及/或表面部分配置屏蔽电极层，上述柱状构件是与上述屏蔽电极层通过同时烧结而形成一体化的柱状金属。
另外，本发明的第12方面所述的电子元器件的制造方法，是在第10方面所述的发明中，上述顶部用陶瓷未烧成体在其内层部分及/或表面部分具有未烧成厚膜电阻体。
另外，本发明的第13方面所述的电子元器件的制造方法，是在第10方面所述的发明中，上述未烧成屏蔽电极层中，在至少与一个安装在上述布线基板的主表面上的表面安装元器件相对的部分具有开口部。
另外，本发明的第14方面所述的电子元器件的制造方法，是在第10方面的任一项所述的发明中，上述顶部用陶瓷未烧成体在上述主表面上具有将陶瓷烧结体作为坯体、而且具有端子电极的片状陶瓷电子元器件。
另外，本发明的第15方面所述的电子元器件的制造方法，是在第10至第14方面的任一项所述的发明中，将上述柱状构件形成为截面是锥状。
另外，本发明的第16方面所述的电子元器件的制造方法，是在第10至第14方面的任一项所述的发明中，将上述覆盖构件的柱状构件通过接合材料与设置在上述布线基板的表面的上述布线图形连接。
另外，本发明的第17方面所述的电子元器件的制造方法，是在第10至第14方面的任一项所述的发明中，具有以集合基板状态将上述布线基板与上述覆盖构件进行连接、并将它分割成一个个电子元器件的工序。
另外，本发明的第18方面所述的电子元器件的制造方法，是在第17方面所述的发明中，在分割上述集合基板状态的材料时，也分割上述柱状构件，得到将该柱状构件的分割面作为侧面电极的电子元器件。
根据本发明的第1至第18方面所述的发明，提供一种具有覆盖构件的电子元器件及其制造方法，它能够以薄的厚度而且高精度进行制造，同时对布线基板的安装精度高，而且能够进一步降低高度。
附图说明
图1(a)、(b)分别所示为本发明的电子元器件的一种实施形态图，(a)所示为整个电子元器件的剖视图，(b)所示为电子元器件的覆盖构件的立体图。
图2(a)～(c)分别所示为图1所示的电子元器件的布线基板的制造工序主要部分的工序图。
图3(a)～(c)分别所示为图1所示的电子元器件的覆盖构件的制造工序主要部分的工序图。
图4(a)～(c)分别所示为图1所示的电子元器件的组装工序的工序图。
图5所示为图1(b)所示的覆盖构件的集合基板的立体图。
图6所示为使用图5所示的集合基板进行组装的电子元器件的集合体的剖视图。
图7所示为本发明的电子元器件的其它实施形态中使用的覆盖构件的集合基板的立体图。
图8所示为使用图7所示的集合基板进行组装的电子元器件的集合体的剖视图。
图9(a)、(b)分别所示为电子元器件的覆盖构件与表面安装元器件的关系的剖视图，(a)所示为图1所示的电子元器件中使用的覆盖构件与表面安装元器件的关系图，(b)所示为以往的电子元器件中使用的金属制覆盖构件与表面安装元器件的关系图。
图10所示为本发明的电子元器件的另外其它实施形态的剖视图。
图11(a)、(b)所示为将图1所示的电子元器件的覆盖构件的脚部与本发明的另外其它实施形态的电子元器件的覆盖构件的脚部进行比较的剖视图。
图12(a)、(b)所示为本发明的电子元器件的另外其它实施形态的覆盖构件的制造工序主要部分的剖视图。
图13(a)、(b)分别所示为本发明的电子元器件的另外其它实施形态的剖视图，所示为电子元器件的组装工序图。
图14(a)～(d)分别所示为本发明的电子元器件的另外其它实施形态的主要部分的剖视图。
图15(a)～(c)分别所示为本发明的电子元器件的另外其它实施形态的主要部分的剖视图。
图16(a)、(b)分别所示为使用图15(a)所示的覆盖构件的电子元器件的剖视图。
图17(a)、(b)分别所示为以往的电子元器件的剖视图。
图18(a)、(b)分别所示为以往的其它电子元器件的覆盖构件的制造工序主要部分的剖视图。
标号说明
10 电子元器件
11 布线基板
12 表面安装元器件
13 覆盖构件
13A 顶部
13B 脚部(柱状构件、柱状金属)
13C 屏蔽电极层
13D 通路导体
13E 开口部
13F 厚膜电阻体
13H 片状陶瓷电子元器件
14 布线图形
100、100A收缩抑制用薄片(收缩抑制用陶瓷未烧成体)
113A 顶部用陶瓷生片(顶部用陶瓷未烧成体)
113C 未烧成屏蔽电极层
112C 未烧成通路导体
P 接合材料
具体实施方式
以下，根据图1～图16所示的实施形态来说明本发明。
第1实施形态
本实施形态的电子元器件10例如图1(a)所示，包括；具有规定的布线图形的布线基板11；安装在该布线基板的主表面(上表面)上的多个表面安装元器件12；以及覆盖这些表面安装元器件12的覆盖构件13，例如安装在母板(未图示)等安装基板上那样构成。
布线基板11如图1(a)所示，例如形成为将多个陶瓷层11A进行层叠而构成的陶瓷多层基板。布线基板14包含在上下陶瓷层11A与11A的界面以规定的图形形成的面内导体14A；为了将上下的面内导体14A与14A电连接而贯穿陶瓷层、以规定的图形配置而形成的通路导体14B；以及在布线基板11的上下两面分别叫规定的图形形成的表面电极(端子电极)14C与14C。
作为表面安装元器件12，例如图1(a)所示，安装了硅半导体元件、砷化镓半导体元件等片状有源电子元器件12A、以及电容器、电感器、电阻器等片状无源电子元器件12B等。这些表面安装元器件12A及12B例如该图所示，通过焊锡或导电性树脂、或者通过Au、Al、Cu等键合引线，与布线基板11的上表面的表面电极14C、即布线图形14电连接，互相导通。
覆盖构件13如图1(a)、(b)所示，具有利用平板状的陶瓷构件形成的顶部13A、以及由该顶部13A的下表面的周边部分沿垂直向下方向延伸的柱状构件形成的多个脚部13B。顶部13A具有多个陶瓷层层叠形成的层叠结构。脚部13B例如利用柱状金属形成为比表面安装元器件12距离布线基板11的上表面的高度要高，而且利用烧结与顶部13A形成一体化。在顶部13A内，沿面方向形成屏蔽电极层13C，同时形成将屏蔽电极层13C的周边部分与脚部13B连接的通路导体13D。脚部13B、屏蔽电极层13C、以及通路导体13D最好用同一种导电性金属材料形成。顶部13A内的屏蔽电极层13C通过通路导体13D及脚部13B与布线基板11的布线图形14连接，在外部的电磁场环境中保护表面安装元器件12。另外，最好屏蔽电极层13C与布线基板11上设置的接地电极、通过由柱状金属形成的脚部13B接地，但不一定必须接地。
另外，陶瓷层11A及覆盖构件13的顶部13A的陶瓷层都是利用陶瓷材料形成的，最好这两者用同一种陶瓷材料形成。作为陶瓷材料，可以使用例如低温共烧陶瓷(LTCC；Low Temperature Co-fired Ceramic)材料。所谓低温共烧陶瓷材料，是能够用1050℃以下的温度进行烧结、能够与电阻率小的银或铜等同时进行烧成的陶瓷材料。作为低温共烧陶瓷，具体来说，可以举出有对氧化铝、氧化锆、氧化镁或镁橄榄石等陶瓷粉末混合硼硅酸系玻璃而制成的玻璃复合系LTCC材料、使用ZnO-MgO-Al2O3-SiO2系晶化玻璃的晶化玻璃系LTCC材料、以及使用BaO-Al2O3-SiO2系陶瓷粉末或Al2O3-CaO-SiO2-MgO-B2O3系陶瓷粉末等的非玻璃系LTCC材料等。
覆盖构件13的屏蔽电极层13C、通路导体13D、脚部13B、以及布线基板11的布线图形14分别如上所述，利用导电性金属材料形成。作为导电性金属材料，可以使用以Ag、Ag-Pt合金、Ag-Pd合金、Cu、Ni、Pt、Pd、W、Mo及Au中所选择的至少一种为主要成分的金属。这些导电性金属材料中，由于Ag、Ag-Pt合金、Ag-Pd合金及Cu的电阻率小，因此特别能够适用于作为布线材料。另外，在使用低温共烧陶瓷材料作为形成陶瓷层11A及顶部13A的陶瓷层的陶瓷材料时，作为导电性金属材料，可以使用Ag或Cu等具有低电阻、并具有1050℃以下的低熔点的金属，这些金属材料能够与低温共烧陶瓷材料以1050℃以下的低温同时进行烧成。
另外，在本实施形态中，布线基板11及覆盖构件13分别使用的陶瓷材料及布线图形用的导电性金属材料最好实质上是同一种。若布线基板11与覆盖构件13的材料不同，则有可能因各自材料对于温度变化产生的热膨胀率之差，而使覆盖构件13从布线基板11剥离。
下面，参照图2～图4，说明本发明的电子元器件的制造方法的一种实施形态。在本实施形态中，采用无收缩工艺制造布线基板11及覆盖构件13。所谓无收缩工艺，是指在陶瓷基板烧成前后、陶瓷基板的平面方向的尺寸实质上不变化的工艺。在该无收缩工艺中，使用后述的收缩抑制片。本实施形态的电子元器件的制造方法如以下说明的那样，包含；制造具有布线图形14的布线基板11的工序；制造具有利用平板状的陶瓷构件形成的顶部13A、与该顶部13A一体化而且从该顶部13A向下方延伸的由柱状构件构成的脚部13B的覆盖构件13的工序；以及将覆盖构件13重叠在布线基板11的上面、通过脚部13B与布线基板11连接的工序。
1.布线基板的制造
1)基板用陶瓷未烧成体(基板用陶瓷生片)的制造
首先，作为低温共烧陶瓷粉末，例如调制由氧化铝粉末及硼硅酸玻璃构成的混合粉末。使该混合粉末分散在有机媒液中，调制浆料，利用铸造法将这浆料成形为片状，从而例如以20μm的厚度制成规定片数的图2(a)所示的基板用陶瓷生片111A。该陶瓷生片111A经过后述的层叠工序、压紧工序、以及烧成工序，烧成后的厚度成为10μm。接着，例如使用激光或金属模具，对基板用陶瓷生片111A以规定的图形形成通孔后，对该通孔充填导体性糊料，形成未烧成通路导体114B。作为导电性糊料，例如使用以Ag为主要成分的糊料。然后，例如利用丝网印刷法，将同一导电性糊料以规定的图形印刷在基板用陶瓷生片111A上，形成未烧成面内导体114A。另外，同样制成以规定的图形形成了未烧成面内导体114A、未烧成通路导体114B、以及未烧成表面电极114C的陶瓷生片111A，例如全部准备了5片陶瓷生片111A。
2)收缩抑制用陶瓷未烧成体(收缩抑制用陶瓷生片)的制造
收缩抑制用陶瓷生片包含用低温共烧陶瓷材料的烧成温度不烧结的难烧结性陶瓷粉末作为主要成分。例如准备氧化铝粉末作为难烧结性陶瓷粉末，使该氧化铝粉末分散在有机媒液中，调制浆料，利用铸造法将这浆料成形为片状，从而制成规定片数的图2(a)所示的收缩抑制用陶瓷生片100及100A。这些收缩抑制用陶瓷生片100及100A的烧结温度为1500～1600℃，由于具有比低温共烧陶瓷粉末制成的基板用陶瓷生片111A的烧结温度(1050℃以下)明显要高的烧结温度，因此在基板用陶瓷生片111A的烧成温度下实质上不烧结。例如图2(a)所示，各制成3片这些收缩抑制用陶瓷生片100及100A。收缩抑制用陶瓷生片100及100A实质上是相同的。作为难烧结性陶瓷粉末，例如除了氧化铝以外，还可以使用氧化锆、氧化镁等陶瓷粉末。作为这些收缩抑制用陶瓷生片100及100A，最好包含与基板用陶瓷生片111A中包含的陶瓷成分相同的材料。
3)复合层叠体的制造
如图2(b)所示，将3片收缩抑制用陶瓷生片100A进行层叠，在其上将具有未烧成通路导体114B及未烧成表面电极114C的基板用陶瓷生片111A使其未烧成表面电极114C朝下进行层叠，在其上将3片具有未烧成面内导体114A及未烧成通路导体114B的基板用陶瓷生片111A进行层叠，再在其上将具有未烧成通路导体114B及未烧成表面电极114C的基板用陶瓷生片111A使其未烧成表面电极114C朝上进行层叠。接着，在这些之上将3片收缩抑制用陶瓷生片100进行层叠后，若从层叠方向(上下方向)以0.2～1.5Mpa的压力将各层进行压制，从而压紧，将这些层形成一体化，则能够形成图2(b)所示的复合层叠体110。
4)复合层叠体的烧成
若将上述复合层叠体110以例如1050℃以下的规定温度(例如870℃)进行烧成，则由于收缩抑制用陶瓷生片1001及100A实质上不烧结，实质上在面方向没有收缩，因此即使5片基板用陶瓷生片111A烧结后形成一体化，由于收缩抑制用陶瓷生片100及100A的作用，在面方向实质上没有收缩，能够制成实质上仅沿层叠方向(厚度方向)收缩、具有高精度的布线图形14的图2(c)所示的布线基板11。由于布线基板11实质上仅沿厚度方向收缩，因此能够有助于电子元器件10降低高度。通过该烧成，收缩抑制用陶瓷生片100及100A的有机媒液烧掉，成为氧化铝粉末的聚集体。氧化铝粉末的聚集体能够利用喷砂处理等简单地除去，通过除去氧化铝粉末，从而容易得到布线基板11。例如20μm的基板用陶瓷生片111A，用5层虽是100μm，但利用该烧成，沿高度方向收缩，能够得到50μm厚的布线基板11。
5)镀层处理
在制成布线基板11后，对表面电极14C加以例如镀金等镀层处理，提高与焊锡等接合构件的浸润性。
2.覆盖构件的制造
1)顶部用陶瓷未烧成体(顶部用陶瓷生片)的制造
覆盖构件12使用与布线基板11相同的材料、根据同一要领制造。首先，如图3(a)所示，制成规定片数(例如2片)的顶部用陶瓷生片113A。这些顶部用陶瓷生片113A形成20μm厚。在一片顶部用陶瓷生片113A的上表面利用导电性糊料的全面印刷，形成大面积的未烧成屏蔽电极层113C。另外，对于其它的顶部用陶瓷生片113A形成以规定的图形配置的多个通孔，对这些通孔内充填导电性糊料，形成多个未烧成通路导体113D。若将这些顶部用陶瓷生片113A进行层叠，则使多个未烧成通路导体113D分别位于未烧成屏蔽电极层113C的周边部分。
2)收缩抑制用陶瓷生片的制造
与布线基板11的情况相同，制成规定片数(例如6片)的收缩抑制用陶瓷生片。对3片收缩抑制用陶瓷生片200使用激光或金属模具以规定的图形形成脚部用的通孔后，对该通孔内充填导电性糊料，形成未烧成脚部113B。未烧成脚部113B所需要的尺寸是，烧成后的高度与表面安装元器件12的安装高度为相同程度或比它要高，其高度是利用收缩抑制用陶瓷生片200的使用片数来进行调整。另外，未烧成脚部113B在烧成后的横向截面形状可以是圆形，也可以是多边形，圆形的直径(多边形时是通过其中心的最大尺寸)只要是0.1～1mm即可。在本实施形态中，如图3(a)、(b)所示，例如制成3片收缩抑制用陶瓷生片200。另外，如该图所示，例如还制成3片不包含未烧成脚部113B的抑制收缩用陶瓷生片200A。另外，在不需要取得电导通时，可以对柱状构件用的通孔充填陶瓷糊料(以低温共烧陶瓷为主要成分)，通过这样用作为脚部。在这种情况下，由陶瓷糊料形成的柱状构件也与布线基板通过同时烧成而形成一体化。
3)复合层叠体的制造
然后，如图3(a)所示，将3片没有未烧成脚部的收缩抑制用陶瓷生片200A进行层叠，在其上将具有未烧成屏蔽电极层113C的顶部用陶瓷生片113A使其未烧成屏蔽电极层113C朝上进行层叠，在其上将具有未烧成通路导体113D的顶部用陶瓷生片113A进行层叠。接着，在其上将3片具有未烧成脚部113B的收缩抑制用陶瓷生片200进行层叠。这时，将收缩抑制用陶瓷生片200的未烧成脚部113B与顶部用陶瓷生片113A的未烧成通路导体113D进行位置对准。然后，将收缩抑制用陶瓷生片200以规定的压力(例如0.2～1.5MPa)进行压紧，制成图3(b)所示的复合层叠体130，之后将该复合层叠体130用规定温度(例如870℃)进行烧成，从而可以制成图3(c)所示的覆盖构件13。
在本实施形态中，将屏蔽电极层13C形成作为顶部13A的内层，但也可以在顶部13A的外表面形成。但是，屏蔽电极层13C不形成顶部13A的内表面(覆盖构件13的内表面)为好。若在覆盖构件13的内表面形成屏蔽电极层13C，则在特性分选时等夹具的压力作用下顶部13A向内侧弯曲，有可能与安装在布线基板11上的表面安装元器件12接触等，而不能进行高精度的特性分选。换句话说，若在覆盖构件13的内层或外表面形成屏蔽电极层13C，则能够以高精度进行特性分选。
3.对布线基板安装表面安装元器件及覆盖构件
在布线基板11上安装表面安装元器件12时，如图4(a)所示，将安装表面安装元器件12的面朝上配置，例如使用金属掩膜，对表面安装元器件用的表面电极14C、及连接覆盖构件13的脚部的通路导体14B涂布焊锡糊料等接合材料P之后，如图4(a)所示，使用安装机械(未图示)，将表面安装元器件12安装、配置在布线基板11上。再进一步，如图4(b)所示，使用安装机械，将覆盖构件13安装、配置在布线基板11上。接着，对布线基板11进行回流焊等热处理，通过这样使焊锡熔融，如图4(c)所示，将表面安装元器件12及覆盖构件13分别安装在布线基板11上。在这样安装时使用金属掩膜的情况下，由于安装面为平坦面，因此能够使金属掩膜与安装面高精度地紧贴。
在以上的说明中，说明了制成一个电子元器件10的情况，但工业上如图5及图6所示，以集合基板状态同时制成多个电子元器件10。在同时制成多个电子元器件10时也同样，除了取得多个布线基板及覆盖构件以外，能够以上述制造顺序无任何变化进行制造。即，根据与制造一个电子元器件10的情况同一要领，制成矩阵状排列多个布线基板的第1集合基板51(参照图6)，同时制成矩阵状排列多个覆盖构件13的第2集合基板53(参照图5及图6)。在第2集合基板53上形成分割为一个个覆盖构件13的假想分割线L，沿假想分割线L的两侧排列一个个覆盖构件13的脚部13B，呈矩形框状。然后，使用安装机械，在第1集合基板51的一个个布线基板11上安装表面安装元器件12之后，安装第2集合基板53，进行热处理，形成一体化，通过这样能够制成图6所示的电子元器件集合体50。然后，若沿着电子元器件集合体50的假想分割线L切割电子元器件集合体50，则能够得到一个个电子元器件10。
另外，第1及第2集合基板也可以如图7所示那样形成。即，图7所示的第2集合基板53A的覆盖构件13的成为脚部13B的部分排列在第2集合基板53A的假想分割线L上，呈矩形状。另外，与各脚部13B相对应的布线基板11的通路导体14B如图8所示，沿着第1集合基板51A的假想分割线L形成。然后，使用安装机械，在第1集合基板51A的一个个布线基板上安装表面安装元器件之后，安装第2集合基板53A，形成一体化，制成图8所示的电子元器件集合体50A。然后，若沿着电子元器件集合体50A的假想分割线L切割电子元器件集合体50，则沿着假想分割线L将成为脚部13B的部分及成为通路导体14B的部分一分为二，能够得到一个个电子元器件10。在这种情况下，由于覆盖构件13的脚部13B及布线基板11的一部分的面内导体14A及通路导体14B与电子元器件10的端面对齐，因此在电子元器件10安装时也可以用作为侧面电极。
如上所述，根据本实施形态，覆盖布线基板11上的表面安装元器件12的覆盖构件13，具有利用平板状的陶瓷构件形成的顶部13A、以及至少具有表面安装元器件的高度的由柱状构件形成的多个脚部13B，由于顶部13A利用平板状的陶瓷构件形成，因此能够形成作为没有以往那样厚度不同的部分、烧成时沿厚度方向均匀收缩来进行烧结、不产生弯曲等的平坦的顶部13A，能够促使电子元器件10降低高度。另外，由于覆盖构件13的顶部13A是陶瓷构件，因此在电子元器件10进行特性分选时等情况下，即使顶部13A弯曲，在与表面安装元器件12之间也不会短路。
另外，由于顶部13A是陶瓷构件，因弯曲而对表面安装元器件12几乎没有影响，因此能够减小顶部13A与表面安装元器件12之间的间隙，能够更促使降低高度。例如图9(a)所示，在顶部13A的厚度为50μm时，即使在与表面安装元器件12之间设置相当于顶部13a的厚度的间隙50μm，则从表面安装元器件12的上表面到顶部13A的外表面的尺寸也只要100μm就行。但是，以往的金属制覆盖构件2如图9(b)所示，若考虑到机械强度，则覆盖构件的厚度的极限是100μm，若设置相当于覆盖构件的厚度的间隙100μm，则从表面安装元器件的上表面到覆盖构件的外表面的尺寸成为200μm。因而，本实施形态中的覆盖构件13确实能够使电子元器件10降低高度。
另外，根据本实施形态，由于顶部13A具有将多个陶瓷层进行层叠而构成的多层结构，而且配置屏蔽电极层13C作为其内层，再有屏蔽电极层13C通过陶瓷层中设置的通路导体13D与由柱状金属构成的脚部13B连接，因此与布线基板11的成为接地电位的布线图形14连接的覆盖构件13，能够利用其屏蔽电极层13C，将布线基板11上的表面安装元器件12对外部的电磁场环境进行屏蔽，加以保护。
另外，根据本实施形态，由于屏蔽电极层13C与脚部13B的柱状金属通过同时烧成而形成一体化，因此在覆盖构件13安装时，对覆盖构件13不需要另外形成连接用的焊锡凸点等，能够与表面安装元器件12相同，利用安装机械将覆盖构件13对布线基板11进行安装，能够简化制造工序。
另外，根据本实施形态，通过使用收缩抑制用陶瓷生片100及100A的无收缩工艺来制成布线基板11，从而能够制成无变形、具有高精度的布线图形14的布线基板11，而且由于利用无收缩工艺来抑制面方向的收缩，因此沿层叠方向(厚度方向)的收缩大，能够形成更薄的布线基板11，能够促使电子元器件10降低高度。通过使用收缩抑制用陶瓷生片200及200A的无收缩工艺来制成覆盖构件13，从而如上所述，能够减薄顶部13A，而不产生弯曲，而且能够将脚部13B与顶部13A同时进行烧成而形成一体化。另外，由于覆盖构件13的顶部13A是平坦面，因此能够使用安装机械将覆盖构件13对布线基板11进行高精度安装。
第2实施形态
关于本实施形态的电子元器件，对于与第1实施形态同一或相当部分附加同一标号进行说明。在上述实施形态中，对于用覆盖构件13的屏蔽电极层13C全部覆盖多个表面安装元器件12的电子元器件10进行了说明。但是，在表面安装元器件12中，例如像某种SAW滤波器组件那样，有时表面安装元器件12的特性根据它与覆盖构件13的接地电位即屏蔽电极层13C的距离而变化。例如，若在电子元器件10进行特性分选时，有时覆盖构件13的顶部13A由于夹具等的作用而弯曲，则覆盖构件13的屏蔽电极层13C与表面安装元器件12之间的距离变化，表面安装元器件12的特性受到影响。
因此，本实施形态的电子元器件10A，除了具有图10中用○标记包围的特定的表面安装元器件12C、以及在该表面安装元器件12C进行特性分选时等情况下对其特性不产生影响的覆盖构件13以外，与上述实施形态同样构成。对于该覆盖构件13的屏蔽电极层13C，如图10所示，在位于特定的表面安装元器件12C的正上方的部分形成开口部13E，在相当于顶部13A的开口部13E的部分仅利用陶瓷材料形成。该覆盖构件13除了对顶部用陶瓷生片全面印刷具有开口部的未烧成屏蔽电极层以外，能够根据与上述实施形态同一要领制成。
因而，根据本实施形态，由于覆盖构件13的顶部13A的特定的表面安装元器件12C的正上方利用陶瓷构件形成，因此即使在电子元器件10A进行特性分选时等情况下，覆盖构件13的顶部13A弯曲，特定的表面安装元器件12C也不因屏蔽电极层13C而受到电磁场的影响，能够测定特定的表面安装元器件12C的本来特性，能够高精度挑选电子元器件10A的好坏。因而，不会将合格品抛弃，或者不会将不合格品上市。其它，在本实施形态中，也能够期望有与上述实施形态同样的作用效果。
第3实施形态
本实施形态的电子元器件如图11(a)所示，除了覆盖构件13的脚部13B的形状不同以外，与第1实施形态同样构成。因而，对于与第1实施形态同一或相当部分附加同一标号，来说明本实施形态。
在上述各实施形态中，覆盖构件13的脚部13B如图11(b)所示，说明的是直筒状的脚部，但如图11(a)所示，本实施形态中的脚部13B形成为轴心方向的截面呈锥状的形状、即倒圆截锥形状或倒方锥形状。该脚部13B可这样形成，即利用激光对收缩抑制片加工通孔，使得截面形状呈锥形，再对该通孔充填导电性糊料而形成。另外，上述各实施形态的轴向截面形状为直筒状的脚部13B可这样形成，即分别利用金属模具等进行冲孔加工，从而加工成直筒状的通孔，再对该通孔充填导电性糊料而形成。
因而，根据本实施形态，如图11(a)所示，包含焊锡焊缝F的脚部13B的与布线基板11的连接面积、即直径d’，比图11(b)所示的直筒状的情况下的直径d要小。即，能够用脚部13B的上端面和下端面(连接覆盖构件13的布线基板11的连接面)相同的连接面积将覆盖构件13与布线基板11上连接。其它，在本实施形态中，也能够期望有与上述实施形态同样的作用效果。另外，脚部13B也可以是截面锥状的部分沿上下方向连接多个的脚部。
第4实施形态
本实施形态的电子元器件如图12(a)所示，除了覆盖构件13没有屏蔽电极层、在覆盖构件13与布线基板11之间不需要导通以外，与第1实施形态同样构成。因而，在本实施形态中，对于与第1实施形态同一或相当部分也附加同一标号，来说明本实施形态。
本实施形态中的覆盖构件13能够如图12(b)所示那样制成。即，如该图所示，例如将2片20μm厚的陶瓷生片进行层叠，作为顶部用陶瓷生片113A，在其下面配置例如250μm厚的没有未烧成脚部的收缩抑制用陶瓷层200A，在其上面配置例如250μm厚的有未烧成脚部113B的收缩抑制用陶瓷层200，将它们进行层叠，进行压紧，从而制成复合层叠体(未图示)。通过烧成该复合层叠体，能够制成图12(a)所示的由顶部13A及脚部13B构成的覆盖构件13。顶部13A形成20μm厚。作为未烧成脚部113B，可以使用例如以低温共烧陶瓷为主要成分的陶瓷糊料。另外，根据需要，也可以使覆盖构件13混合存在没有导通性的脚部与有导通性的脚部。在这种情况下，在顶部13A形成屏蔽电极层。其它，在本实施形态中，也能够得到与第1实施形态同样有助于降低高度的覆盖构件13。
第5实施形态
本实施形态的电子元器件如图13(a)所示，除了在布线基板11上具有通过键合引线12D进行安装、而且用树脂R进行封装的表面安装元器件12以外，与第1实施形态同样构成。因而，在本实施形态中，对于与第1实施形态同一或相当部分也附加同一标号，来说明本实施形态。
本实施形态中的表面安装元器件12由于在布线基板11上以树脂封装的状态进行安装，因此在将覆盖构件13安装到布线基板11上时，不能使用金属掩膜对通路导体14B直接涂布焊锡糊料。
所以，在本实施形态中，采用如图13(b)所示的对覆盖构件13的脚部13B的前端面涂布接合材料的方法。作为接合材料，只要是液体状或半液体状即可，最好使用焊锡糊料或导电性树脂等。即，例如图13(b)所示，使覆盖构件13的脚部13B与容器A内的液体状的接合材料P接触，将接合材料P直接转印到脚部13B的前端面。然后，如图13(a)所示，在将覆盖构件13的脚部13B与布线基板11的通路导体14B进行位置对准后，将覆盖构件13重叠在布线基板11上，进行热处理，通过这样能够将覆盖构件13安装到布线基板11上。
根据本实施形态，即使不能利用金属掩膜将接合材料涂布在布线基板11的通路导体14B及表面电极14C上，也能够通过对覆盖构件13的脚部13B的下端转印接合材料P，很容易将覆盖构件13安装并固定在布线基板11上。其它，在本实施形态中，也能够期望有与第1实施形态同样的作用效果。
第6实施形态
本实施形态的电子元器件如图14(a)所示，除了在覆盖构件13的顶部13A内设置厚膜电阻体13F及其布线图形13G以代替屏蔽电极层13C以外，与第1实施形态同样构成。因而，本实施形态中的覆盖构件13实质上可以根据与第1实施形态同一要领制成。因而，在本实施形态中，对于与第1实施形态同一或相当部分也附加同一标号，来说明本实施形态。
图14(a)所示的覆盖构件13具有厚膜电阻体13F及其布线图形13G，以代替屏蔽电极层13C。在制造该覆盖构件13时，制成规定片数的顶部用陶瓷生片(未图示)，在规定的顶部用陶瓷生片上以规定的图形形成通孔，对该通孔内充填导电性糊料，在陶瓷生片上形成未烧成通路导体。接着，在以规定的图形印刷导电性糊料形成未烧成面内导体后，印刷电阻糊料，形成未烧成厚膜电阻体。作为电阻糊料，例如可以采用以氧化钌为主要成分的电阻材料等以往众所周知的电阻材料。另外，在制成与第1实施形态同样具有未烧成脚部的收缩抑制片及没有未烧成脚部的收缩抑制片后，根据与第1实施形态同一要领，将顶部用陶瓷生片与收缩抑制片进行层叠，制成复合层叠体，通过烧成该复合层叠体，能够制成覆盖构件13。该覆盖构件13如图14(a)所示，具有厚膜电阻体13F及布线图形13G。烧成后对覆盖构件13的厚膜电阻体13F照射激光，进行微调，从而能够得到所希望的电阻值。
根据图14(a)所示的实施形态，由于通常安装在布线基板11上的所需要的电阻芯片作为厚膜电阻体13F置于覆盖构件13内，因此在布线基板11上不需要安装电阻芯片，能够节省其安装面积所占的空间，能够使电子元器件小型化，实现功能的高密度化。其它，在本实施形态中，也能够得到与第4实施形态同样有助于降低高度的覆盖构件13。
在图14(a)中，说明了在覆盖构件13的顶部13A内设置厚膜电阻体13F及其布线图形13G的情况，但也可以如图14(b)～(d)所示，对覆盖构件13的屏蔽电极层13C附设厚膜电阻体13F及其布线图形13G。在图14(b)～(d)所示的覆盖构件的情况下，除了屏蔽电极层13C以外，再增加一片形成厚膜电阻体13F及其布线图形13G用的陶瓷生片，除此之外，能够根据与第1实施形态同一要领制成覆盖构件。因而，图14(b)～(d)所示的覆盖构件的制造方法的说明省略。
在图14(b)所示的覆盖构件13的顶部13A内，形成屏蔽电极层13C和厚膜电阻体13F及其布线图形13G，厚膜电阻体13F及其布线图形13G配置在屏蔽电极层13C的上方形成。厚膜电阻体13F的微调可以通过从顶部13A的上方对厚膜电阻体13F照射激光来进行。
另外，在图14(c)所示的覆盖构件13的情况下，在顶部13A的上表面形成屏蔽电极层13C，在顶部13A的内部，形成厚膜电阻体13F及其布线图形13G。对于屏蔽电极层13C，在厚膜电阻体13F的正上方位置形成微调用的开口部13E，能够从顶部13A的上方照射激光，很好地进行厚膜电阻体13F的微调。
在图14(d)所示的覆盖构件13的情况下，在顶部13A内，形成屏蔽电极层13C和厚膜电阻体13F及其布线图形13G，厚膜电阻体13F及其布线图形13G配置在屏蔽电极层13C的下方形成。对于屏蔽电极层13C，在厚膜电阻体13F的正上方位置形成微调用的开口部13E，能够从顶部13A的上方照射激光，很好地进行厚膜电阻体13F的微调。
根据图14(b)～(d)所示的本实施形态，能够使电子元器件小型化，实现多功能化，另外能够期望有与第1实施形态同样的作用效果。
第7实施形态
本实施形态的电子元器件如图15(a)～(c)所示，除了设置片状陶瓷电子元器件13H以代替第6实施形态的厚膜电阻体13F以外，按照图14(a)、(c)、(d)所示的实施形态构成。片状陶瓷电子元器件13H将陶瓷烧结体作为坯体，在其两端具有外部端子电极。作为片状陶瓷电子元器件13H，可以举出有例如层叠陶瓷电容器、层叠电感器等无源电子元器件。因而，本实施形态中的覆盖构件13实质上可以根据与第1实施形态同一要领制成。因而，在本实施形态中，对于与第1实施形态同一或相当部分也附加同一标号，来说明本实施形态。
图15(a)所示的覆盖构件13具有片状陶瓷电子元器件13H，以代替图14(a)的厚膜电阻体13F。该片状陶瓷电子元器件13H从覆盖构件13的顶部13A的下表面侧与内部的布线图形13G连接。在制造覆盖构件13时，与第6实施形态相同，在顶部用陶瓷生片上形成规定的未烧成布线图形(未烧成面内导体及未烧成通路导体)。将规定片数的顶部用陶瓷生片层叠在收缩抑制用陶瓷生片上，形成在层叠体的上表面未烧成连接盘部以规定的图形露出表面的层叠体。然后，使用喷射器等在层叠体的上表面涂布有机系粘接剂，形成有机系粘接剂层之后，使用安装机械(未图示)，对未烧成连接盘部安装片状陶瓷电子元器件13H，在未烧成连接盘部上接合、固定片状陶瓷电子元器件。接着，将具有未烧成脚部的收缩抑制用陶瓷生片进行层叠，进行压紧，从而制成复合层叠体。通过该压紧，片状陶瓷电子元器件13H与未烧成连接盘部一起，从层叠体的上表面稍微被埋入。若将该复合层叠体进行烧成，则片状陶瓷电子元器件13H的外部端子电极与连接盘部13I形成一体化进行烧结，能够制成将片状陶瓷电子元器件13H部分埋入的覆盖构件13(参照图15(a))。片状陶瓷电子元器件13H埋入顶部13A内的埋入量比较好的是1μm以上，特别好的是1～200μm。
根据本实施形态，由于安装在覆盖构件13上的片状陶瓷电子元器件13H从顶部13A的下表面埋入，因此在将覆盖构件13安装、固定在布线基板11上时，即使进行回流焊等热处理，片状陶瓷电子元器件13H与连接盘部的连接部分也不会恶化，能够长时间内确保连接可靠性，其它能够期望有与第1实施形态同样的作用效果。
在图15(b)所示的覆盖构件13的情况下，在顶部13A的上表面形成屏蔽电极层13C，在顶部13A的内部形成布线图形13G，片状陶瓷电子元器件13H与图15(a)所示的情况相同，与该布线图形13G连接。
在图15(c)所示的覆盖构件13的情况下，在顶部13A内形成屏蔽电极层13C及片状陶瓷电子元器件13H用的布线图形13G，布线图形13G配置在屏蔽电极层13C的下方形成。片状陶瓷电子元器件13H与图15(a)所示的情况相同，与该布线图形13G连接。
根据图15(b)、(c)所示的本实施形态，能够长时间内确保片状陶瓷电子元器件13H的连接可靠性，同时能够在外部的电磁场环境中确实加以保护，其它能够期望有与第1实施形态同样的作用效果。
在将图15(a)～(c)所示的覆盖构件13安装在布线基板11上时，如图16(a)所示，最好在布线基板11上的片状陶瓷电子元器件13H的相对面不安装表面安装元器件12。这样，在电子元器件10进行特性分选时，即使因夹具而使覆盖构件13的顶部13A弯曲，片状陶瓷电子元器件13H也不会在布线基板11上短路。另外，即使要安装表面安装元器件12，也如图16(b)所示，在布线基板11上的片状陶瓷电子元器件13H的相对面安装利用树脂封装的表面安装元器件12C。若表面安装元器件12C是利用树脂封装的，则即使覆盖构件13的顶部13A弯曲，片状陶瓷电子元器件13H与表面安装元器件12C接触，也不会短路，能够高精度地评价特性。
另外，本发明不受上述各实施形态的任何限制，只要不违反本发明的宗旨，都包含在本发明中。
工业上的实用性
本发明可适用于作为各种电子设备等使用的电子元器件。

Claims (18)

1.一种电子元器件，其特征在于，包括：
具有布线图形的布线基板；
安装在该布线基板的主表面上的表面安装元器件；以及
覆盖该表面安装元器件的覆盖构件，
所述覆盖构件包括：利用平板状的陶瓷构件形成的顶部；以及利用至少具有在所述表面安装元器件的高度以上的高度的柱状构件形成的脚部，
所述柱状构件是柱状金属，该柱状金属与所述平板状的陶瓷构件通过同时烧成而形成一体化。
2.如权利要求1所述的电子元器件，其特征在于，
所述顶部具有将多个陶瓷层进行层叠而构成的多层结构，而且在其内层部分及/或外侧表面部分配置屏蔽电极层，所述屏蔽电极层通过设置在所述陶瓷层的通路导体，与所述柱状金属连接。
3.如权利要求2所述的电子元器件，其特征在于，
所述屏蔽电极层与所述柱状金属通过同时烧成而形成一体化。
4.如权利要求2或3所述的电子元器件，其特征在于，
所述屏蔽电极层中在至少与一个所述表面安装元器件相对的部分形成开口部。
5.如权利要求1至3中的任一项所述的电子元器件，其特征在于，
所述顶部具有将多个陶瓷层进行层叠而构成的多层结构，而且在其内层部分及/或内侧表面部分及/或外侧表面部分配置厚膜电阻体，所述厚膜电阻体通过设置在所述陶瓷层的通路导体，与所述柱状金属连接。
6.如权利要求5所述的电子元器件，其特征在于，
所述顶部在其内层部分及/或外侧表面部分配置屏蔽电极层，所述屏蔽电极层中在与所述厚膜电阻体相对的部分形成开口部。
7.如权利要求1至3中的任一项所述的电子元器件，其特征在于，
在所述顶部设置将陶瓷烧结体作为坯体、而且具有端子电极的片状陶瓷电子元器件，该片状陶瓷电子元器件的至少一部分埋入所述顶部。
8.如权利要求1至3中的任一项所述的电子元器件，其特征在于，
所述布线基板形成作为将多个第1低温共烧陶瓷层进行层叠而构成的陶瓷多层基板，在其内层具有以银或铜为主要成分的布线图形。
9.如权利要求8所述的电子元器件，其特征在于，
所述顶部具有将多个第2低温共烧陶瓷层进行层叠而构成的层叠结构，该第2低温共烧陶瓷层与所述第1低温共烧陶瓷层由相同的材料组成。
10.一种电子元器件的制造方法，其特征在于，包括以下工序：
制造具有布线图形的布线基板的工序；
制造具有平板状的顶部、以及与该顶部形成一体化而且由该顶部沿垂直方向延伸的柱状构件构成的脚部的覆盖构件的工序；以及
将所述覆盖构件重叠在布线基板的主表面上、并通过所述脚部与所述布线基板连接的工序，
制造所述覆盖构件的工序包括以下工序：
制造以低温共烧陶瓷为主要成分、而且在内层部分及/或表面部分具有未烧成屏蔽电极层的顶部用陶瓷未烧成体的工序；
制造以在所述低温共烧陶瓷的烧成温度下不烧结的难烧结陶瓷为主要成分、而且具有成为所述柱状构件的未烧成柱状构件的收缩抑制用陶瓷未烧成体的工序；
在所述顶部用陶瓷未烧成体的一个主表面上重叠所述收缩抑制用陶瓷未烧成体的工序；
将所述顶部用陶瓷未烧成体及所述收缩抑制用陶瓷未烧成体用所述低温共烧陶瓷的烧成温度进行烧成、使所述顶部用陶瓷未烧成体进行烧结同时使所述未烧成屏蔽电极层与所述未烧成柱状构件通过同时烧结而形成一体化的工序；以及
除去所述收缩抑制用陶瓷未烧成体的工序。
11.如权利要求10所述的电子元器件的制造方法，其特征在于，
所述顶部具有将多个陶瓷层进行层叠而构成的多层结构，在其内层部分及/或表面部分配置屏蔽电极层，所述柱状构件是通过与所述屏蔽电极层同时烧结而形成一体化的柱状金属。
12.如权利要求10所述的电子元器件的制造方法，其特征在于，
所述顶部用陶瓷未烧成体在其内层部分及/或表面部分，具有未烧成厚膜电阻体。
13.如权利要求10所述的电子元器件的制造方法，其特征在于，
所述未烧成屏蔽电极层中，在至少与一个安装在所述布线基板的主表面上的表面安装元器件相对的部分，具有开口部。
14.如权利要求10所述的电子元器件的制造方法，其特征在于，
所述顶部用陶瓷未烧成体在所述主表面上具有将陶瓷烧结体作为坯体、而且具有端子电极的片状陶瓷电子元器件。
15.如权利要求10至14中的任一项所述的电子元器件的制造方法，其特征在于，
将所述柱状构件形成为截面是锥状。
16.如权利要求10至14中的任一项所述的电子元器件的制造方法，其特征在于，
将所述覆盖构件的柱状构件通过接合材料与设置在所述布线基板的表面的所述布线图形连接。
17.如权利要求10至14中的任一项所述的电子元器件的制造方法，其特征在于，
具有以集合基板状态将所述布线基板与所述覆盖构件进行连接、并将它分割成一个个电子元器件的工序。
18.如权利要求17所述的电子元器件的制造方法，其特征在于，
在分割所述集合基板状态的材料时，也分割所述柱状构件，得到将该柱状构件的分割面作为侧面电极的电子元器件。
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