JP2014207347A - セラミック多層配線基板およびこれを備えるモジュール - Google Patents
セラミック多層配線基板およびこれを備えるモジュール Download PDFInfo
- Publication number
- JP2014207347A JP2014207347A JP2013084567A JP2013084567A JP2014207347A JP 2014207347 A JP2014207347 A JP 2014207347A JP 2013084567 A JP2013084567 A JP 2013084567A JP 2013084567 A JP2013084567 A JP 2013084567A JP 2014207347 A JP2014207347 A JP 2014207347A
- Authority
- JP
- Japan
- Prior art keywords
- mounting
- wiring board
- multilayer wiring
- via conductors
- ceramic multilayer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000919 ceramic Substances 0.000 title claims abstract description 100
- 239000004020 conductor Substances 0.000 claims abstract description 195
- 238000010304 firing Methods 0.000 claims description 5
- 238000002955 isolation Methods 0.000 claims description 3
- 238000003475 lamination Methods 0.000 claims 1
- 238000000926 separation method Methods 0.000 claims 1
- 230000007547 defect Effects 0.000 abstract description 10
- 238000001354 calcination Methods 0.000 abstract 1
- 229910000679 solder Inorganic materials 0.000 description 12
- 239000011229 interlayer Substances 0.000 description 7
- 239000000758 substrate Substances 0.000 description 7
- 238000013461 design Methods 0.000 description 5
- 239000011347 resin Substances 0.000 description 5
- 229920005989 resin Polymers 0.000 description 5
- 238000009736 wetting Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 239000010410 layer Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 239000011230 binding agent Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000008602 contraction Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000011812 mixed powder Substances 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000002002 slurry Substances 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000007429 general method Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G2/00—Details of capacitors not covered by a single one of groups H01G4/00-H01G11/00
- H01G2/02—Mountings
- H01G2/06—Mountings specially adapted for mounting on a printed-circuit support
- H01G2/065—Mountings specially adapted for mounting on a printed-circuit support for surface mounting, e.g. chip capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F17/00—Fixed inductances of the signal type
- H01F17/0006—Printed inductances
- H01F17/0013—Printed inductances with stacked layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F27/00—Details of transformers or inductances, in general
- H01F27/28—Coils; Windings; Conductive connections
- H01F27/29—Terminals; Tapping arrangements for signal inductances
- H01F27/292—Surface mounted devices
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0364—Conductor shape
- H05K2201/0367—Metallic bump or raised conductor not used as solder bump
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/09427—Special relation between the location or dimension of a pad or land and the location or dimension of a terminal
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10007—Types of components
- H05K2201/10015—Non-printed capacitor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10636—Leadless chip, e.g. chip capacitor or resistor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
【解決手段】モジュール1は、積層されたセラミックグリーンシートが焼成されて成る積層体4と、それぞれ積層体4の一方主面4aに、端面が露出して設けられた複数の部品実装用の実装端子5a1,5b1,5c1と、各実装端子5a1,5b1,5c1それぞれに対応して前記積層体4内に設けられ、それぞれ対応する実装端子5a1,5b1,5c1に平面視で重なる位置に配置された複数のビア導体6a1,6b1,6c1とを備え、各実装端子5a1,5b1,5c1の各所定点a1,b1,c1が、同一平面に位置するように各ビア導体6a1,6b1,6c1の長さが調整されている。
【選択図】図1
Description
本発明の第1実施形態にかかるモジュールの一例について、図1〜図3を参照して説明する。なお、図1は第1実施形態にかかるモジュール1の断面図、図2はモジュール1が備えるセラミック多層配線基板の平面図、図1のモジュール1の部分拡大断面図であり、ビア導体6a1およびその周辺の積層体4を示している。なお、図1は図2におけるA―A断面図である。
次に、各実装端子5a1〜5a4,5b1〜5b4,5c1〜5c4の変形例について、図4を参照して説明する。なお、図4は各実装端子5a1〜5a4,5b1〜5b4,5c1〜5c4の変形例を説明するための図であり、セラミック多層配線基板2の平面図である。
本発明の第2実施形態にかかるモジュール1aについて、図5を参照して説明する。なお、図5はモジュール1aの断面図である。
本発明の第3実施形態にかかるモジュール1bについて、図6を参照して説明する。なお、図6はモジュール1bの断面図である。
2 セラミック多層配線基板
3 部品
3a 外部端子
4 積層体
4a 積層体の一方主面
5a1〜5a4,5b1〜5b4,5c1〜5c4,9a1〜9a4,9b1〜9b4,9c1〜9c4 実装端子
6a1〜6a4,6b1〜6b4,6c1〜6c4 ビア導体
6b1a,6b1b 分離ビア導体
Claims (8)
- 積層されたセラミックグリーンシートが焼成されて成る積層体と、
それぞれ前記積層体の一方主面に、端面が露出して設けられた3個以上の部品実装用の実装端子と、
前記各実装端子それぞれに対応して前記積層体内に設けられ、それぞれ対応する前記実装端子に平面視で重なる位置に配置された複数のビア導体とを備え、
前記各実装端子の露出した前記端面における所定点が、同一平面に位置するように前記各ビア導体の長さが調整されている
ことを特徴とするセラミック多層配線基板。 - 前記各実装端子が一列に並んで設けられ、
前記各ビア導体それぞれは、前記各実装端子の配列順に、その長さが長くなるよう形成されていることを特徴とする請求項1に記載のセラミック多層配線基板。 - 隣り合う2つの前記ビア導体間の間隔と、当該両ビア導体の長さの差との関係が、略比例関係にあることを特徴とする請求項2に記載のセラミック多層配線基板。
- 前記各ビア導体の長さが略同一であることを特徴とする請求項1に記載のセラミック多層配線基板。
- 前記各ビア導体のうちの少なくとも1つが、それぞれ前記積層体内に設けられ積層方向において分離配置された複数の分離ビア導体により構成されていることを特徴とする請求項1ないし4のいずれかに記載のセラミック多層配線基板。
- 前記各分離ビア導体のうちの少なくとも1つが、他の導体に接続されないダミー導体であることを特徴とする請求項5に記載のセラミック多層配線基板。
- 前記各実装端子の少なくとも1つは、対応する前記ビア導体の前記積層体の前記一方主面から露出した端面により形成されていることを特徴とする請求項1ないし6のいずれかに記載のセラミック多層配線基板。
- 前記請求項1ないし7のいずれかに記載のセラミック多層配線基板と、
複数の外部端子が設けられた部品とを備え、
前記部品の前記各外部端子が、前記各実装端子に直接接続されていることを特徴とするモジュール。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013084567A JP5799973B2 (ja) | 2013-04-15 | 2013-04-15 | セラミック多層配線基板およびこれを備えるモジュール |
US14/246,280 US10002710B2 (en) | 2013-04-15 | 2014-04-07 | Ceramic multilayer wiring substrate and module including the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013084567A JP5799973B2 (ja) | 2013-04-15 | 2013-04-15 | セラミック多層配線基板およびこれを備えるモジュール |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2014207347A true JP2014207347A (ja) | 2014-10-30 |
JP5799973B2 JP5799973B2 (ja) | 2015-10-28 |
Family
ID=51686659
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2013084567A Expired - Fee Related JP5799973B2 (ja) | 2013-04-15 | 2013-04-15 | セラミック多層配線基板およびこれを備えるモジュール |
Country Status (2)
Country | Link |
---|---|
US (1) | US10002710B2 (ja) |
JP (1) | JP5799973B2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2020188134A (ja) * | 2019-05-15 | 2020-11-19 | 日本特殊陶業株式会社 | 配線基板およびその製造方法 |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10260961B2 (en) | 2015-12-21 | 2019-04-16 | Intel Corporation | Integrated circuit packages with temperature sensor traces |
US10178763B2 (en) * | 2015-12-21 | 2019-01-08 | Intel Corporation | Warpage mitigation in printed circuit board assemblies |
US10880994B2 (en) | 2016-06-02 | 2020-12-29 | Intel Corporation | Top-side connector interface for processor packaging |
WO2018212273A1 (ja) * | 2017-05-19 | 2018-11-22 | 株式会社村田製作所 | 積層型電子部品 |
US11581583B2 (en) * | 2018-07-09 | 2023-02-14 | Ford Global Technologies, Llc | Cell-mounted monolithic integrated circuit for measuring, processing, and communicating cell parameters |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03112191A (ja) * | 1989-09-27 | 1991-05-13 | Toshiba Corp | セラミック配線基板およびその製造方法 |
JPH11298142A (ja) * | 1998-04-09 | 1999-10-29 | Nec Corp | 多層セラミック基板の実装構造と実装方法 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10107437A (ja) | 1996-09-30 | 1998-04-24 | Kyocera Corp | 回路基板の製造方法 |
US6114187A (en) * | 1997-01-11 | 2000-09-05 | Microfab Technologies, Inc. | Method for preparing a chip scale package and product produced by the method |
JP3889856B2 (ja) * | 1997-06-30 | 2007-03-07 | 松下電器産業株式会社 | 突起電極付きプリント配線基板の製造方法 |
JP2001203318A (ja) * | 1999-12-17 | 2001-07-27 | Texas Instr Inc <Ti> | 複数のフリップチップを備えた半導体アセンブリ |
US6528735B1 (en) * | 2001-09-07 | 2003-03-04 | International Business Machines Corporation | Substrate design of a chip using a generic substrate design |
JP4239530B2 (ja) | 2002-09-04 | 2009-03-18 | 株式会社村田製作所 | 多層セラミック基板 |
JP4203435B2 (ja) * | 2003-05-16 | 2009-01-07 | 日本特殊陶業株式会社 | 多層樹脂配線基板 |
JP2005191134A (ja) | 2003-12-24 | 2005-07-14 | Ngk Spark Plug Co Ltd | セラミック配線基板の製造方法及びセラミック配線基板 |
US20080185705A1 (en) * | 2005-12-23 | 2008-08-07 | Tessera, Inc. | Microelectronic packages and methods therefor |
JP2007266111A (ja) * | 2006-03-27 | 2007-10-11 | Sharp Corp | 半導体装置、それを用いた積層型半導体装置、ベース基板、および半導体装置の製造方法 |
KR101096039B1 (ko) * | 2009-11-09 | 2011-12-19 | 주식회사 하이닉스반도체 | 인쇄회로기판 및 이를 이용한 반도체 패키지 |
JP2011243612A (ja) * | 2010-05-14 | 2011-12-01 | Sony Corp | 半導体装置及びその製造方法並びに電子機器 |
US9332629B2 (en) * | 2010-11-02 | 2016-05-03 | Integrated Device Technology, Inc. | Flip chip bump array with superior signal performance |
-
2013
- 2013-04-15 JP JP2013084567A patent/JP5799973B2/ja not_active Expired - Fee Related
-
2014
- 2014-04-07 US US14/246,280 patent/US10002710B2/en not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03112191A (ja) * | 1989-09-27 | 1991-05-13 | Toshiba Corp | セラミック配線基板およびその製造方法 |
JPH11298142A (ja) * | 1998-04-09 | 1999-10-29 | Nec Corp | 多層セラミック基板の実装構造と実装方法 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2020188134A (ja) * | 2019-05-15 | 2020-11-19 | 日本特殊陶業株式会社 | 配線基板およびその製造方法 |
JP7142604B2 (ja) | 2019-05-15 | 2022-09-27 | 日本特殊陶業株式会社 | 配線基板およびその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
US20140307406A1 (en) | 2014-10-16 |
JP5799973B2 (ja) | 2015-10-28 |
US10002710B2 (en) | 2018-06-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5799973B2 (ja) | セラミック多層配線基板およびこれを備えるモジュール | |
KR100659521B1 (ko) | 내부도체의 접속구조 및 다층기판 | |
US8139368B2 (en) | Component-containing module | |
US10231331B2 (en) | Multilayer wiring board and probe card having the same | |
US9538644B2 (en) | Multilayer wiring substrate and module including same | |
US8541694B2 (en) | Multilayer wiring board | |
JP6698826B2 (ja) | 電子部品搭載用基板、電子装置および電子モジュール | |
JP4160923B2 (ja) | 電子部品 | |
JP2023091083A (ja) | 電子素子実装用基板、電子装置および電子モジュール | |
JP2010258189A (ja) | 電子部品搭載用基板の製造方法および電子部品搭載用母基板の製造方法 | |
JP7011563B2 (ja) | 回路基板および電子部品 | |
JP2013207204A (ja) | 配線母基板 | |
CN110326101B (zh) | 布线基板、电子装置及电子模块 | |
JP4558004B2 (ja) | 電子部品、シールドカバー、多数個取り用母基板、配線基板及び電子機器 | |
WO2023026904A1 (ja) | 電子素子実装用基板、電子装置および電子モジュール | |
JP7025845B2 (ja) | 配線基板、電子装置および電子モジュール | |
JP7438656B2 (ja) | 集合基板 | |
JP4733061B2 (ja) | 複数個取り配線基台、配線基台および電子装置、ならびに複数個取り配線基台の分割方法 | |
KR100519813B1 (ko) | 다층기판의 단자구조 및 그 형성방법 | |
US9929067B2 (en) | Ceramic package, method of manufacturing the same, electronic component, and module | |
JPH03133136A (ja) | 集積回路用パッケージの製造方法 | |
JP4511573B2 (ja) | 電子部品およびこれを備えた電子機器 | |
JP4558058B2 (ja) | 電子部品 | |
JP4276284B2 (ja) | 電子部品の製造方法および電子部品用母基板 | |
JP4511513B2 (ja) | 電子部品及びその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20141010 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20150326 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20150407 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20150602 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20150728 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20150810 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5799973 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
LAPS | Cancellation because of no payment of annual fees |