CN100446246C - 半导体器件及其制造方法 - Google Patents
半导体器件及其制造方法 Download PDFInfo
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- CN100446246C CN100446246C CNB2004100120014A CN200410012001A CN100446246C CN 100446246 C CN100446246 C CN 100446246C CN B2004100120014 A CNB2004100120014 A CN B2004100120014A CN 200410012001 A CN200410012001 A CN 200410012001A CN 100446246 C CN100446246 C CN 100446246C
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 54
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 229920005989 resin Polymers 0.000 claims abstract description 157
- 239000011347 resin Substances 0.000 claims abstract description 157
- 229910052751 metal Inorganic materials 0.000 claims description 50
- 239000002184 metal Substances 0.000 claims description 50
- 238000000465 moulding Methods 0.000 claims description 31
- 238000000034 method Methods 0.000 claims description 13
- 230000004927 fusion Effects 0.000 claims description 9
- 238000010438 heat treatment Methods 0.000 claims description 4
- 239000007787 solid Substances 0.000 claims description 3
- 238000002360 preparation method Methods 0.000 claims description 2
- 238000009413 insulation Methods 0.000 abstract description 11
- 239000000945 filler Substances 0.000 description 19
- 239000003822 epoxy resin Substances 0.000 description 7
- 230000017525 heat dissipation Effects 0.000 description 7
- 229920000647 polyepoxide Polymers 0.000 description 7
- 238000007789 sealing Methods 0.000 description 7
- 239000004411 aluminium Substances 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 5
- 239000010931 gold Substances 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 5
- 239000012212 insulator Substances 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 3
- 238000001816 cooling Methods 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 239000004332 silver Substances 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000001721 transfer moulding Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
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Abstract
提供一种散热特性优良、绝缘性高,并且可小型化的用于电力的半导体器件。芯片被树脂模塑的半导体器件包括:具有表面和背面且包含管芯垫的框架;装载于所述管芯垫的所述表面上的功率芯片;具有相对的第一面和第二面的绝缘性树脂片,配置成使所述管芯垫的所述背面与该绝缘性树脂片的第一面接触;以及在所述树脂片的所述第一面上设置成密封所述功率芯片的模塑树脂,其特征在于,所述树脂片的导热率比所述模塑树脂的导热率大。
Description
技术领域
本发明涉及半导体器件,特别涉及包含功率芯片的电力用半导体器件。
背景技术
在现有的电力用半导体器件中,功率芯片和IC芯片被分别管芯键合(die-bonded)在框架上,而且,这些芯片通过树脂来密封。功率芯片因散热量大,例如在半导体器件的背面安装冷却扇,提高散热效率。装载功率芯片的框架被树脂覆盖,与安装于背面的冷却扇绝缘(例如,专利文献1)。
此外,为了提高半导体器件的散热性,还提出在半导体器件的背面上安装由氧化铝等构成的薄板绝缘体的半导体器件(例如,专利文献2)。
[专利文献1]特开2000-138343号公报
[专利文献2]特开2001-156253号公报
但是,在前者的半导体器件中,为了提高散热特性,需要使覆盖装载了功率芯片的框架的树脂,具体地说,装载了功率芯片的框架的背面和半导体器件背面之间的树脂薄,但如果这部分的树脂薄,则相反有绝缘特性下降的问题。
另一方面,在后者的半导体器件中,由于绝缘体和树脂的热膨胀系数大不相同,所以有因功率芯片的发热而使绝缘体从树脂上剥离的问题。此外,由于在绝缘体和树脂之间可形成界面,为了确保这样的界面中的表面绝缘,必须确保表面绝缘距离,还存在半导体器件大型化的问题。
发明内容
因此,本发明的目的在于提供散热特性优良、绝缘性高、并且可小型化的半导体器件。
本发明提供一种树脂模塑有芯片的半导体器件,包括:具有表面和背面且包含管芯垫的框架;装载于所述管芯垫的所述表面上的功率芯片;具有相对的第一面和第二面的绝缘性树脂片,配置成使所述管芯垫的所述背面与该绝缘性树脂片的第一面接触,该绝缘性树脂片具有可以包含所述管芯垫的尺寸;在所述树脂片的所述第一面上设置成密封所述功率芯片的模塑树脂;设置在所述树脂片的所述第二面上的金属箔;和在所述树脂片与所述模塑树脂之间、由构成所述树脂片和所述模塑树脂的树脂混合而成的混合层,其中,所述树脂片的第一面与所述管芯垫的背面直接固定,在作为所述树脂片的第一面与所述管芯垫的所述背面直接固定的部分的固定部分上,所述树脂片为一层,所述固定部分被所述混合层包围。
此外,本发明提供一种树脂模塑了芯片的半导体器件的制造方法,包括:准备树脂片的工序,该树脂片是绝缘性的,具有第一面和第二面,其导热率大于用于树脂模塑的模塑树脂,该树脂片的第二面由金属箔所覆盖,该树脂片包括具有在常温下为固体、而在高温下一旦熔融后趋向于完全固化的特征的半固化状态的树脂;准备具有表面和背面且带有管芯垫的框架的框架准备工序;在所述管芯垫的所述表面上装载功率芯片的工序;准备树脂密封用金属模的工序;在所述树脂密封用金属模内配置所述树脂片,以使所述金属箔接触所述树脂密封用金属模的内部底面上的工序;在所述树脂片的所述第一面上配置所述框架,以使所述管芯垫的所述背面接触所述树脂片的所述第一面的工序;以及将液化了的模塑树脂注入所述树脂密封用金属模内并填充在该金属模内,并且在该金属模内使模塑树脂和所述树脂片加热固化,以形成混合层的模塑工序;其中,所述模塑工序是在将所述管芯垫的背面与所述树脂片的第一面固定,并且以将作为所述树脂片的第一面与所述管芯垫的背面直接固定的部分的固定部分包围的方式形成所述混合层的工序。
在本发明的半导体器件中,通过使用树脂片,散热特性优良,并且可提高绝缘性。而且,还可进行半导体器件的小型化。
附图说明
图1是本发明实施方式1的半导体器件的立体图。
图2是本发明实施方式1的半导体器件的背面图。
图3是本发明实施方式1的半导体器件的剖面图。
图4是表示本发明实施方式的半导体器件的一部分内部的立体图。
图5是本发明实施方式1的半导体器件的制造工序的剖面图。
图6是本发明实施方式1的半导体器件的制造工序的剖面图。
图7是树脂片的放大剖面图。
图8是本发明实施方式2的半导体器件的剖面图。
图9是本发明实施方式3的半导体器件的背面图。
图10是本发明实施方式3的半导体器件的剖面图。
具体实施方式
实施方式1
图1是整体用100表示的本实施方式的半导体器件的立体图。而图2是图1的半导体器件100的背面图,图3是图1的半导体器件100的I-I方向上观察的剖面图。而且,图4是图1的半导体器件100的一部分内部的立体图。
如图1所示,半导体器件100构成树脂模塑型封装结构,包含在两侧设置有多个金属制的框架1的模塑树脂2。模塑树脂2最好由环氧树脂构成。
如图2所示,在模塑树脂2的背面上,例如设置在背面安装有由铜构成的金属箔4的绝缘性树脂片3。树脂片3最好由包含填料的环氧树脂构成。填料最好由从SiO2、Al2O3、AlN、Si3N4、及BN中选择的一种或多种材料构成。树脂片3的导热率比模塑树脂2的导热率大。
如图3所示,半导体器件100包含多个框架1。如图4更详细地所示,在一个框架1中,装载逻辑芯片这样的IC芯片7。而另一框架1包含管芯垫部1a和台阶部1b,在管芯垫部1a上,装载IGBT5a和续流二极管5b这样的功率芯片5。功率芯片5、IC芯片7、及框架1之间,例如用金或铝构成的键合线6、8来连接,通过IC芯片7控制功率芯片5的动作。
一般地,将功率芯片5和IC芯片7使用焊料或银膏固定在框架1上。而在功率芯片5的连接上,使用铝键合线8,在IC芯片7的连接上,使用直径比其小的金键合线6。
再有,功率芯片5和IC芯片7也可以根据半导体器件100的功能而设置多个。
如上述那样,模塑树脂2包含安装了金属箔4的绝缘性树脂片3,从模塑树脂2的背面露出金属箔4。这样的金属箔4保护树脂片3免受损伤,所以树脂片3可维持良好的绝缘性。作为这样的损伤,例如是将半导体器件100螺纹固定在外部散热片(未图示)上时,在半导体器件100和外部散热片之间啮入异物下进行螺纹固定时产生的损伤。再有,在不易产生损伤时,也可以采用不设置金属箔4的结构。这种情况下,从模塑树脂2的背面露出树脂片3。
在树脂片3上装载框架1,以直接接触管芯垫部1a的背面。树脂片3的面积比管芯垫部1a的面积大。而且,功率芯片5、IC芯片7等被模塑树脂2密封。
在树脂片3和模塑树脂2接触的区域中,形成混合了双方的树脂的混合层9。这样,经由混合层9来连接树脂片3和模塑树脂2,所以与没有混合层9的情况相比,树脂片3和模塑树脂2之间的导热性高,使散热性提高。后面论述有关混合层9的形成方法。
树脂片3的导热率比模塑树脂2的导热率大,特别是最好大于等于两倍。由此,可以获得散热特性优良的半导体器件100。
下面,参照图5、图6,说明半导体器件100的制造方法。这样的制造方法包含以下的工序1~8。再有,图5、图6是在与图1的I-I相同的方向上观察的剖面图。
工序1:如图5(a)所示,例如准备铜构成的框架1。接着,在一个框架1上用焊料或银膏等来固定IC芯片7,在另一框架1的管芯垫部1a上用焊料或银膏来固定功率芯片6。
工序2:如图5(b)所示,使用铝键合线6,将功率芯片5彼此之间、功率芯片5和框架1之间、框架1彼此之间进行连接(铝键合工序)。再有,就键合线6来说,也可以使用以铝为主要成分的合金或其他金属。
工序3:如图5(c)所示,使用金键合线,连接IC芯片7和框架1(金键合工序)。再有,就键合线7而言,也可以使用以金为主要成分的合金或其他金属。
工序4:如图5(d)所示,准备树脂密封用金属模20。树脂密封用金属模20可分为上部金属模21和下部金属模22。接着,准备在背面安装了金属箔4的绝缘性树脂片3,并配置在树脂密封用金属模20的内部规定位置。这种情况下,以金属箔4的背面可接触下部金属模22的内部底面来配置树脂片3。这里,就树脂片3来说,使用半固化状态的树脂。树脂片3例如由环氧树脂构成,如上述那样,最好包含填料。
再有,半固化状态的树脂指常温下为固体,而在高温下一旦熔融后进行完全固化的未完全固化状态的热固化树脂。
工序5:如图6(e)所示,将安装了功率芯片5等的框架1配置在树脂密封用金属模20中的规定位置。这种情况下,配置框架1,以使框架1的管芯垫部的背面接触树脂片3的上表面。
工序6:如图6(f)所示,在下部金属模22上安装并固定上部金属模21。接着,通过转移模塑成形法,例如将环氧树脂构成的密封树脂12填充在树脂密封用金属模20内。在图6(f)中,从左方进行填充。
在这样的工序中,设置于树脂密封用金属模20内的半固化状态的树脂片3首先从高温的树脂密封用金属模20中接受热,并临时熔融。进而,熔融的树脂片3和管芯垫1a通过加压状态下注入的密封树脂12被加压、粘合。
工序7:如图6(g)所示,将密封树脂2、树脂片3加热固化。在这样的工序中,树脂片3和密封树脂12在同时熔融的状态下接触,所以进行混合,在该接触部分形成混合层9。
工序4~7为所谓的转移模塑工序。在这样的工序中,树脂片3在熔融时被加压,而树脂密封用金属模20内整体被密封树脂12加压,所以树脂片3的厚度大体不变化。另一方面,树脂密封用金属模20内的各部不一定通过密封树脂12被同时填充,在各部中直至压力均等所需的时刻上,产生略微的时间偏差。因此,作为树脂片3的特性,期望熔融时的流动性小。
工序8:在从树脂密封用金属模20取出后,进行用于使模塑树脂完全固化的后固化、连杆(tie bar)等框架多余部分的切断等。而且,通过进行框架(外部端子)1的成形,完成图1所示的半导体器件100。
再有,树脂片3以环氧树脂为主要成分,从主要提高导热性来看,如上所述,最好是填充SiO2等绝缘性填料。这些填料具有减小树脂片3的线膨胀系数的效果,所以管芯垫1a和金属箔4的热膨胀系数之差变小。因此,不易产生温度变化造成的剥离,在可靠性上优良。
此外,密封树脂12也与树脂片3同样,如果形成以环氧树脂作为主要成分的材料,则可以稳定形成混合层9。这样的情况下,没有密封树脂12和树脂片3的明显界面,不需要考虑其间的表面绝缘,其结果,可进行半导体器件的小型化。
而且,在树脂片3中,通过使填料的形状为鳞片状,与形成粒状的情况相比,可以稳定地确保绝缘性,如后述那样,从实验可知,
在这样的实验中,使用填充了鳞片状填料的树脂片和填充了同量的粒状填料的树脂片,来制作半导体器件100,并进行绝缘试验。绝缘试验的结果示于表1。
(表1)
鳞片状r/N=0/10
粒状r/N=3/10
这里,r为不合格的样本的数量,N表示试验中投入的样本的数量。
而且,在鳞片状填料中,与粒状填料相比,由于填料的比表面积大,所以与片树脂的接触面积也大,可以减小熔融时的流动性。
此外,关于填料的尺寸,也可以将大尺寸的(最大直径大的)填料和小尺寸的(最大直径小的)填料混合使用。图7是包含两种尺寸的填料的树脂片3的剖面的放大图。树脂片3为在环氧树脂等树脂层33中包含了大尺寸的填料31和小尺寸的填料32的结构。
如图7所示,在大尺寸的填料31间的间隙中,可以填充小尺寸的填料32,所以进一步提高树脂片3的导热性。
如以上那样,在本实施方式的半导体器件100中,使用可以预先规定绝缘层厚度的绝缘性树脂片3。因此,通过调整树脂片3的膜厚,可以进行兼顾绝缘特性和散热特性的控制。
此外,由于只在必要的区域中设置树脂片3,所以可削减无用的成本。
而且,在半导体器件100中,在树脂片3和模塑树脂2的界面上形成混合层9,所以不需要考虑表面绝缘,其结果,可使半导体器件小型化。
再有,在本实施方式1中,用健合线来连接IC芯片7等,但例如也可以使用金属薄板等其他构件。而且,IC芯片7和功率芯片5之间的连接示出了经由临时中继框架来连接的例子,但直接连接也可以。
实施方式2
图8是整体用200表示的本实施方式的半导体器件的剖面图。图8是在与图1的I-I相同的方向观察的剖面图。图8中,与图1~图3相同的标号表示相同或相当的部位。
在本实施方式2的半导体器件200中,安装了金属箔4的树脂片3有覆盖模塑树脂2的整个背面的大小。其他结构与上述半导体器件100相同。
在半导体器件200中,在提高了散热特性的同时,在制造工序中不需要树脂片3的配置定位。即,由于树脂片3与树脂密封用金属模20的内部底面的尺寸相等,所以不需要正确地控制配置位置。由此,制造工序被简化。
实施方式3
图9是整体用300表示的本实施方式的半导体器件的剖面图。而图10是在IHV-IIIV方向上观察图9的剖面图。图9、图10中,与图1~图3相同的标号表示相同或相当的部位。
半导体器件300沿树脂片3的周围有多个凹部40。此外,有用于安装冷却扇(未图示)的螺纹孔35。
在上述工序4(图5(d))中,为了在树脂片3上容易进行定位,在树脂密封用金属模20的内部底面上,为了设置多个突起部(未图示)而形成这样的凹部40。在树脂密封用金属模20的内部底面上,沿树脂片3的配置区来设置突起部。
这样,通过在树脂密封用金属模20的内部底面上设置突起部。使树脂片3的定位容易,可简化制造工序。
再有,在图9、图10中,将凹部40的形状形成为大致圆柱形状,但只要是具有这种功能的形状,即使其他的形状也可以。此外,只要具有这样的功能,凹部40的数目多少都可以。
而且,凹部40的深度最好是比金属箔4的厚度薄。这是因为即使凹部40错误重叠在金属箔4上,其前端也不到达树脂片3,树脂片3不受到损伤。
Claims (3)
1.一种树脂模塑有芯片的半导体器件,包括:
具有表面和背面且包含管芯垫的框架;
装载于所述管芯垫的表面上的功率芯片;
具有相对的第一面和第二面的绝缘性树脂片,配置成使所述管芯垫的背面与该绝缘性树脂片的第一面接触,该绝缘性树脂片的面积大于所述管芯垫的面积;
在所述树脂片的所述第一面上设置成密封所述功率芯片的模塑树脂;
设置在所述树脂片的所述第二面上的金属箔;和
在所述树脂片与所述模塑树脂之间、由构成所述树脂片和所述模塑树脂的树脂混合而成的混合层,
其中,所述树脂片的第一面与所述管芯垫的背面直接接触,
作为所述树脂片的第一面与所述管芯垫的背面直接接触的部分的接触部分被所述混合层包围。
2.如权利要求1所述的半导体器件,其特征在于,所述树脂片的所述第一面由所述接触部分和所述混合层所覆盖。
3.一种树脂模塑了芯片的半导体器件的制造方法,包括:
准备树脂片的工序,该树脂片是绝缘性的,具有第一面和第二面,其导热率大于用于树脂模塑的模塑树脂,该树脂片的第二面由金属箔所覆盖,该树脂片包括具有在常温下为固体、而在高温下一旦熔融后趋向于完全固化的特征的半固化状态的树脂;
准备具有表面和背面且带有管芯垫的框架的框架准备工序;
在所述管芯垫的表面上装载功率芯片的工序;
准备树脂密封用金属模的工序;
在所述树脂密封用金属模内配置所述树脂片,以使所述金属箔接触所述树脂密封用金属模的内部底面上的工序;
在所述树脂片的所述第一面上配置所述框架,以使所述管芯垫的背面接触所述树脂片的所述第一面的工序;以及
将模塑树脂注入所述树脂密封用金属模内并填充在该金属模内,并且在该金属模内使模塑树脂和所述树脂片加热固化,以形成混合层的模塑工序;
其中,所述模塑工序是在将所述管芯垫的背面与所述树脂片的第一面相接触,并且以将作为所述树脂片的第一面与所述管芯垫的背面直接接触的部分的接触部分包围的方式形成所述混合层的工序。
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Also Published As
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KR20060104964A (ko) | 2006-10-09 |
US7671453B2 (en) | 2010-03-02 |
US20050067719A1 (en) | 2005-03-31 |
KR20050031877A (ko) | 2005-04-06 |
KR20070104497A (ko) | 2007-10-26 |
JP2005109100A (ja) | 2005-04-21 |
KR100806479B1 (ko) | 2008-02-21 |
CN1604324A (zh) | 2005-04-06 |
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