CN100446216C - 半导体技术中产生间距细分的方法 - Google Patents
半导体技术中产生间距细分的方法 Download PDFInfo
- Publication number
- CN100446216C CN100446216C CNB2006101009901A CN200610100990A CN100446216C CN 100446216 C CN100446216 C CN 100446216C CN B2006101009901 A CNB2006101009901 A CN B2006101009901A CN 200610100990 A CN200610100990 A CN 200610100990A CN 100446216 C CN100446216 C CN 100446216C
- Authority
- CN
- China
- Prior art keywords
- spacer
- layer
- separator
- complementation
- gap
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims description 26
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 238000005516 engineering process Methods 0.000 title claims description 7
- 125000006850 spacer group Chemical group 0.000 claims abstract description 102
- 230000000737 periodic effect Effects 0.000 claims abstract description 25
- 239000000463 material Substances 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 8
- 230000011218 segmentation Effects 0.000 claims description 3
- 230000000295 complement effect Effects 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 62
- 239000013067 intermediate product Substances 0.000 description 15
- 230000004048 modification Effects 0.000 description 6
- 238000012986 modification Methods 0.000 description 6
- 239000000047 product Substances 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000009413 insulation Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Inorganic Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Semiconductor Memories (AREA)
- Drying Of Semiconductors (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
在周期结构的图案层的条状部分的侧壁上形成隔离物。去除图案层,并且用另外的隔离层覆盖该隔离物,接着将其构造成第二侧壁隔离物。用互补层填充隔离物之间的间隙。将上表面平面化到较低的表面水平,保留第一隔离物、第二隔离物和互补层的剩余部分的周期顺序。以去除保留层的一层或两层提供更小间距的周期图案的方式修改横向尺寸。
Description
技术领域
本发明涉及半导体器件的周期结构或图案的制造方法。
背景技术
类似半导体存储器的一些类型的半导体器件包括至少在一个维度上是周期性的结构元件或图案化层。例如,字线和位线通常沿着彼此平行延伸的直线设置。线的宽度和在相邻线之间的距离在整个器件内是恒定的。这样,这些线的顺序在一个方向上是周期性的,优选最小尺寸,其能够实现最小面积的存储单元阵列。线的尺寸和它们的间隔在周期性顺序的方向上连续重复。这些周期中的一个的长度称为图案的间距。
应用于构造周期图案的制造技术限制了间距的值。一些限制是由于在构造工艺中采用的掩模技术。在使用掩模的常规蚀刻工艺中,对可获得的尺寸限制较小。另一方面,器件的进一步小型化,使得必须提供能够实现更小间距的制造方法。只有在制造的结构足够精确以满足器件性能的需要的情况下,这些方法才是可应用的。
发明内容
在一个方面中,本发明涉及半导体器件中具有比至今可能的间距更小的间距的周期图案的制造方法。
本发明的另一个目的是通过基于标准半导体技术的方法步骤来减小间距。
本发明使用重复的隔离物技术,以便用更小且更窄的致使间距细分的间隔元件代替规则的周期图案。该方法包括以下步骤:提供具有图案层的衬底,其被构造成彼此平行延伸且在它们之间具有相同的横向尺寸和相同的距离的分开的条状部分;在图案层上共形地施加第一隔离层;各向异性地蚀刻第一隔离层以在条状部分的侧壁上形成第一隔离物;去除图案层,使第一隔离物每个具有两个主侧壁;共形地施加第二隔离层;各向异性地蚀刻第二隔离层以在第一隔离物的主侧壁上形成第二隔离物,从而在相邻的第二隔离物之间保留空余空间;施加互补层以填充这些空余空间;形成第一隔离物、第二隔离物和互补层的上表面的平坦表面;以及去除第一隔离物、或第二隔离物、或互补层、或第一和第二隔离物、或第一隔离物和互补层、或第二隔离物和互补层。
由随后的附图的简要说明、详细描述和所附权利要求和附图,本发明的这些和其它的目的、特征和优点将变得明显。
附图说明
为了更完全地理解本发明和它的优点,现在参考下文中结合附图的描述,其中:
图1示出了本发明方法的第一变型的第一中间产品的截面图。
图2示出了根据图1在施加隔离层之后的另外的中间产品的截面图。
图3示出了根据图2在隔离物形成之后的截面图。
图4示出了根据图3在施加第二隔离层之后的截面图。
图5示出了根据图4在形成第二隔离物以及施加互补层之后的截面图。
图6示出了根据图5在平面化步骤之后的截面图。
图7示出了为了形成半间距的周期图案,根据图6在去除隔离物之后的截面图。
图8示出了根据图6的包括不同尺寸的所述方法的变型的截面图。
图9示出了根据图7的能够从图8的中间产品获得的产品的截面图。
图10示出了根据图2的包括其它横向尺寸的所述方法的变型的截面图。
图11示出了根据图10的在施加第二隔离层之后的另外的中间产品的截面图。
图12示出了根据图11在形成第二隔离物以及施加互补层之后的截面图。
图13示出了根据图7的可从根据图12的中间产品获得的产品的截面图。
图14示出了根据图13的可从根据图12的中间产品获得的另外的产品的截面图。
图15示出了根据所述方法的另外的应用的中间产品的截面图。
具体实施方式
图1示出了所述方法的第一变型的第一中间产品的截面图。在衬底1的主表面上施加图案层2,其可包括不同材料的层或半导体器件结构。这在图1中没有详细示出,因为对于该方法来说没有必要描述它。图案层2被提供有彼此平行延伸的分开的条状部分的结构。可通过硬掩模3获得该结构。硬掩模3可以是氮化物,例如,其可通过包括施加光致抗蚀剂层的光刻步骤来构造。图案层2的条状部分具有侧壁,其理想地垂直于衬底的主表面。条状部分的横向尺寸,它们的宽度,始终是相同的。对于所有相邻部分的对,在两个相邻的条状部分之间的距离也是相同的。因此,图案层2具有周期结构,每个周期包括一个条状部分和在两个相邻条状部分之间的一个间隔。周期的长度在图1中表示为图案的最初间距10。当然,代表周期性的部分可沿着图1中的箭头的任一方向移动,但是周期的长度是固定的且限定图案的间距。优选在执行下面的工艺步骤之前去除硬掩模3。
图2示出了在共形的施加第一隔离层4之后的另外的中间产品。第一隔离层4的材料可以是电绝缘或导电的且被选择为不同于图案层2的材料,以便可以相对于第一隔离层4选择性地去除图案层2。在图2中由虚线表示由第一隔离层4形成的第一隔离物5的形状。通过各向异性蚀刻步骤制作第一隔离物5,其在垂直于衬底1的主表面的方向上减少了第一隔离层4。继续进行该工艺直到完全去除在图案2之上和在要形成的第一隔离物5之间的区域中的第一隔离物4的材料为止。然后去除图案层2。
图3示出了根据图2去除图案层2之后的截面图。第一隔离物5留在衬底1上且形成新的周期图案,相邻的第一隔离物5彼此间隔开。所述最初间距10也表示在图3中。在最初间距10的每个周期中有两个第一隔离物5。在图3中示出的实施例中,选择图案层2的条状部分的横向尺寸和第一隔离物5的横向尺寸或厚度使得第一隔离物5被相等地间隔开。这样,获得周期性的新图案,其具有为最初间距10的一半的间距。
图4示出了根据图3在施加第二隔离层6之后的截面图,该第二隔离层可以是任何材料,例如,尤其是衬垫。它也被共形地施加以使在随后的各向异性蚀刻之后保留第二隔离物。这样提供了如图5中所示的第一隔离物5和第二隔离物7的结构。
图5示出了第一隔离物5在其两个相对的主侧壁上都被提供了第二隔离物7,第一隔离物5的高度可能在第二蚀刻步骤中被略微地减小了。在图5中再次标示最初间距10。用互补层8覆盖获得的结构,其填充隔离物之间的间隙。根据半导体器件的实施例的需要以及也考虑随后的构造步骤来选择互补层8的材料。
接着平面化根据图5的中间产品的上表面以及优选地将其向下抛光到图6中示出的典型水平,其也示出了互补层8的条状剩余部分、第二隔离物7、第一隔离物5,以及第二隔离物7等周期性地在垂直于层条的纵向延伸的方向上的接连次序。为了获得最初间距的一半的周期图案,去除第一和第二隔离物。
图7示出了在去除隔离物之后的产品,仅留下互补层8的条状剩余部分。在图7中标示最初间距10以示出通过前面的方法步骤该间距已经被二等分。
图8示出了根据图6的截面图的包括其它横向尺寸的所述方法的变型的中间产品。这里已调整图案层2的条状部分的尺寸以及第一隔离物5和第二隔离物7的厚度以便第一隔离物、第二隔离物和互补层8的剩余部分的条都具有相同的横向尺寸。如果至少互补层8的所述部分和第一隔离物5的横向尺寸是相同的就足够了。这确保了第二隔离物7的顺序和第一隔离物5和互补层8的所述部分的交替顺序都形成最初间距10的四分之一的周期图案。
图9示出了去除第二隔离物7时获得的最初间距10的四分之一的周期图案的实例。如果去除第一隔离物5和互补层8的所述部分则形成包括第二隔离物7的互补的周期图案。通过去除在根据图8的中间产品中存在的任何单层或层的组合,可获得多种其它周期图案。这样,通过仅去除第一隔离物5,或仅第二隔离物7,或仅互补层8,或去除第一和第二隔离物,或第一隔离物和互补层,或第二隔离物和互补层,可获得不同的图案。
图10示出了根据图2的截面图的中间产品的另外的实施例的截面图。图10的实施例与图2的实施例在图案层2的条状部分的横向尺寸上不同。在此将该尺寸选择成大于每两个位于两个相邻的条状部分的彼此面对的侧壁上的第一隔离物5之间的距离的两倍。
图11示出了根据图10的在施加第二隔离层6之后的另外的中间产品的截面图。在第一隔离物的顺序上第一隔离物5之间的距离大小交替。在第一隔离物5之间的较小的间隙被第二隔离层6的材料完全填充。在较大的间隙中,在共形沉积的第二隔离层6的侧壁部分之间存在小空隙。
图12示出了根据图11在形成第二隔离物7之后的截面图。优选地选择第二隔离层6的厚度以便在相邻的第二隔离物7之间留下的空隙具有与第一隔离物5相同的尺寸。如果也适当地选择图案层2的条状部分的横向尺寸,则位于第一隔离物5之间的较窄间隙内的第二隔离层6的剩余部分的厚度和第二隔离物7的厚度相等。在这种情况下,第二隔离层6的所有剩余部分以相等的距离间隔开。随后的平面化步骤,通过该步骤将所述材料去除到图12中的水平虚线表示的水平,将提供类似于图8中示出的结构,但是具有比较厚的第二隔离物7。与图11的比较表明该变型提供了第二隔离物7的周期图案,其中在最初间距10的间隔内总是存在三个第二隔离物7。因此新的间距是最初间距的三分之一。
图13示出了去除第一隔离物5和互补层8之后的另外的中间产品。保留的第二隔离物7都具有相同的宽度并且被相等地间隔开。
图14示出了互补结构,其中去除了第二隔离物7且第一隔离物5和互补层8保留在衬底1上。因为调整了尺寸使得第一隔离物5和互补层8的所述部分具有相同的厚度,所以根据图14的产品的结构具有最初间距10的三分之一的周期图案。
图15示出了根据图13的在衬底1和第二隔离物7的图案之间具有所示的另外的器件层9的产品。该实例说明通过本方法获得的已细分的最初间距的图案可用作掩模,以将另外的器件层9构造为比至今可能有的间距更小的间距的周期图案。在该实例中,优选地,由适合于硬掩模的材料形成第二隔离物7,例如氮化硅。以同样的方式,图7、图9或图14的图案和通过本方法可获得的其它规则图案可在另外的构造步骤中用作掩模,通过所述步骤将器件层9构造为具有更小的间距。器件层9具体地说可以是包括栅极电介质的字线层,特别是包括存储层、多晶硅层、金属或金属硅化物层和顶电绝缘层的一种,其被构造成字线叠层。但是通过本方法的间距细分的可能的应用不限于存储器件。可以使用从包括第二隔离物和互补层、第一隔离物和互补层、第一和第二隔离物、互补层、第二隔离物、以及第一隔离物的组中选择的至少一个保留层作为掩模来蚀刻位于条状部分之下的另外的层或层序列,从而制造半导体器件的周期结构或图案。
尽管已经详细地说明了本发明和它的优点,但是应该理解在不脱离由所附权利要求限定的本发明的精神和范围的情况下可以在其中进行多种变化、替代和改变。
参考数字列表
1衬底
2图案层
3硬掩模
4第一隔离层
5第一隔离物
6第二隔离层
7第二隔离物
8互补层
9器件层
10最初间距
Claims (3)
1.半导体技术中制造间距细分的方法,包括:
-提供具有图案层的衬底,其被构造成具有相同宽度且彼此间隔地且彼此平行延伸的分开的条状部分,从而形成周期图案;
-在所述图案层上共形地施加厚度均匀的第一隔离层;
-各向异性地蚀刻所述第一隔离层以在所述条状部分的侧壁上形成第一隔离物;
-去除所述图案层,使所述第一隔离物被间隙隔开,
调整所述条状部分的宽度、相邻条状部分之间的距离、以及所述第一隔离层的厚度,从而使得相邻第一隔离物之间的间隙交替地较大和较小,
每个较大间隙的宽度为较小间隙的宽度加上一个第一隔离物的宽度的两倍;
-共形地施加第二隔离层,以利用所述第二隔离层填充所述较小间隙;
-各向异性地蚀刻第二隔离层以在所述第一隔离物的侧壁上形成第二隔离物,每个第二隔离物具有与所述较小间隙的宽度相同的宽度;
-施加互补层以填充所述第二隔离物之间的剩余间隙;
-通过去除部分所述第一隔离物、所述第二隔离物和所述互补层而形成平坦表面;以及
-去除所述第二隔离物的剩余部分或者所述第一隔离物和所述互补层两者的剩余部分。
2.根据权利要求1的方法,进一步包括:
-另外的层或层序列,所述图案层施加于其上;
-通过适于硬掩模的材料形成所述第二隔离物;
-去除所述第一隔离物和所述互补层两者的剩余部分;以及
-将所述第二隔离物的剩余部分用作掩模,以将所述另外的层或层序列蚀刻成条状部分。
3.根据权利要求2的方法,其中:
所述另外的层或层序列被设置成用于存储器件的字线。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/194,489 US7291560B2 (en) | 2005-08-01 | 2005-08-01 | Method of production pitch fractionizations in semiconductor technology |
US11/194489 | 2005-08-01 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1909205A CN1909205A (zh) | 2007-02-07 |
CN100446216C true CN100446216C (zh) | 2008-12-24 |
Family
ID=36888553
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2006101009901A Expired - Fee Related CN100446216C (zh) | 2005-08-01 | 2006-08-01 | 半导体技术中产生间距细分的方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US7291560B2 (zh) |
JP (1) | JP4405484B2 (zh) |
CN (1) | CN100446216C (zh) |
GB (1) | GB2428882B (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11985807B2 (en) | 2020-09-17 | 2024-05-14 | Changxin Memory Technologies, Inc. | Method for manufacturing semiconductor structure and semiconductor structure |
Families Citing this family (123)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7151040B2 (en) | 2004-08-31 | 2006-12-19 | Micron Technology, Inc. | Methods for increasing photo alignment margins |
US7910288B2 (en) | 2004-09-01 | 2011-03-22 | Micron Technology, Inc. | Mask material conversion |
US7115525B2 (en) | 2004-09-02 | 2006-10-03 | Micron Technology, Inc. | Method for integrated circuit fabrication using pitch multiplication |
US7655387B2 (en) | 2004-09-02 | 2010-02-02 | Micron Technology, Inc. | Method to align mask patterns |
US7390746B2 (en) | 2005-03-15 | 2008-06-24 | Micron Technology, Inc. | Multiple deposition for integration of spacers in pitch multiplication process |
US7253118B2 (en) | 2005-03-15 | 2007-08-07 | Micron Technology, Inc. | Pitch reduced patterns relative to photolithography features |
US7611944B2 (en) | 2005-03-28 | 2009-11-03 | Micron Technology, Inc. | Integrated circuit fabrication |
US7429536B2 (en) * | 2005-05-23 | 2008-09-30 | Micron Technology, Inc. | Methods for forming arrays of small, closely spaced features |
US7560390B2 (en) | 2005-06-02 | 2009-07-14 | Micron Technology, Inc. | Multiple spacer steps for pitch multiplication |
US7396781B2 (en) | 2005-06-09 | 2008-07-08 | Micron Technology, Inc. | Method and apparatus for adjusting feature size and position |
US7413981B2 (en) | 2005-07-29 | 2008-08-19 | Micron Technology, Inc. | Pitch doubled circuit layout |
US8123968B2 (en) | 2005-08-25 | 2012-02-28 | Round Rock Research, Llc | Multiple deposition for integration of spacers in pitch multiplication process |
US7816262B2 (en) | 2005-08-30 | 2010-10-19 | Micron Technology, Inc. | Method and algorithm for random half pitched interconnect layout with constant spacing |
US7829262B2 (en) | 2005-08-31 | 2010-11-09 | Micron Technology, Inc. | Method of forming pitch multipled contacts |
US7416943B2 (en) | 2005-09-01 | 2008-08-26 | Micron Technology, Inc. | Peripheral gate stacks and recessed array gates |
US7687342B2 (en) | 2005-09-01 | 2010-03-30 | Micron Technology, Inc. | Method of manufacturing a memory device |
US7776744B2 (en) | 2005-09-01 | 2010-08-17 | Micron Technology, Inc. | Pitch multiplication spacers and methods of forming the same |
US7572572B2 (en) | 2005-09-01 | 2009-08-11 | Micron Technology, Inc. | Methods for forming arrays of small, closely spaced features |
US7393789B2 (en) | 2005-09-01 | 2008-07-01 | Micron Technology, Inc. | Protective coating for planarization |
US7759197B2 (en) | 2005-09-01 | 2010-07-20 | Micron Technology, Inc. | Method of forming isolated features using pitch multiplication |
US7557032B2 (en) | 2005-09-01 | 2009-07-07 | Micron Technology, Inc. | Silicided recessed silicon |
US7476933B2 (en) | 2006-03-02 | 2009-01-13 | Micron Technology, Inc. | Vertical gated access transistor |
US7842558B2 (en) | 2006-03-02 | 2010-11-30 | Micron Technology, Inc. | Masking process for simultaneously patterning separate regions |
US7902074B2 (en) | 2006-04-07 | 2011-03-08 | Micron Technology, Inc. | Simplified pitch doubling process flow |
US8003310B2 (en) | 2006-04-24 | 2011-08-23 | Micron Technology, Inc. | Masking techniques and templates for dense semiconductor fabrication |
US7488685B2 (en) | 2006-04-25 | 2009-02-10 | Micron Technology, Inc. | Process for improving critical dimension uniformity of integrated circuit arrays |
US7795149B2 (en) | 2006-06-01 | 2010-09-14 | Micron Technology, Inc. | Masking techniques and contact imprint reticles for dense semiconductor fabrication |
US7723009B2 (en) | 2006-06-02 | 2010-05-25 | Micron Technology, Inc. | Topography based patterning |
US8852851B2 (en) | 2006-07-10 | 2014-10-07 | Micron Technology, Inc. | Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same |
KR20080012055A (ko) * | 2006-08-02 | 2008-02-11 | 주식회사 하이닉스반도체 | 마스크 패턴 형성 방법 |
US7611980B2 (en) | 2006-08-30 | 2009-11-03 | Micron Technology, Inc. | Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures |
US7666578B2 (en) | 2006-09-14 | 2010-02-23 | Micron Technology, Inc. | Efficient pitch multiplication process |
US7807575B2 (en) | 2006-11-29 | 2010-10-05 | Micron Technology, Inc. | Methods to reduce the critical dimension of semiconductor devices |
US7923373B2 (en) | 2007-06-04 | 2011-04-12 | Micron Technology, Inc. | Pitch multiplication using self-assembling materials |
US8143156B2 (en) * | 2007-06-20 | 2012-03-27 | Sandisk Technologies Inc. | Methods of forming high density semiconductor devices using recursive spacer technique |
US8563229B2 (en) | 2007-07-31 | 2013-10-22 | Micron Technology, Inc. | Process of semiconductor fabrication with mask overlay on pitch multiplied features and associated structures |
JP4976977B2 (ja) * | 2007-10-17 | 2012-07-18 | 株式会社東芝 | 半導体装置の製造方法 |
US7737039B2 (en) | 2007-11-01 | 2010-06-15 | Micron Technology, Inc. | Spacer process for on pitch contacts and related structures |
US7659208B2 (en) | 2007-12-06 | 2010-02-09 | Micron Technology, Inc | Method for forming high density patterns |
US7790531B2 (en) | 2007-12-18 | 2010-09-07 | Micron Technology, Inc. | Methods for isolating portions of a loop of pitch-multiplied material and related structures |
JP5315689B2 (ja) * | 2007-12-28 | 2013-10-16 | 東京エレクトロン株式会社 | パターン形成方法、半導体製造装置及び記憶媒体 |
US8030218B2 (en) | 2008-03-21 | 2011-10-04 | Micron Technology, Inc. | Method for selectively modifying spacing between pitch multiplied structures |
US20090246706A1 (en) * | 2008-04-01 | 2009-10-01 | Applied Materials, Inc. | Patterning resolution enhancement combining interference lithography and self-aligned double patterning techniques |
US7989307B2 (en) | 2008-05-05 | 2011-08-02 | Micron Technology, Inc. | Methods of forming isolated active areas, trenches, and conductive lines in semiconductor structures and semiconductor structures including the same |
US10151981B2 (en) * | 2008-05-22 | 2018-12-11 | Micron Technology, Inc. | Methods of forming structures supported by semiconductor substrates |
JP2009289974A (ja) * | 2008-05-29 | 2009-12-10 | Toshiba Corp | 半導体装置の製造方法 |
US8076208B2 (en) | 2008-07-03 | 2011-12-13 | Micron Technology, Inc. | Method for forming transistor with high breakdown voltage using pitch multiplication technique |
US8222159B2 (en) * | 2008-08-25 | 2012-07-17 | Elpida Memory, Inc. | Manufacturing method of semiconductor device |
JP2010056443A (ja) * | 2008-08-29 | 2010-03-11 | Toshiba Corp | 不揮発性半導体メモリ及びその製造方法 |
US8101497B2 (en) | 2008-09-11 | 2012-01-24 | Micron Technology, Inc. | Self-aligned trench formation |
US8492282B2 (en) | 2008-11-24 | 2013-07-23 | Micron Technology, Inc. | Methods of forming a masking pattern for integrated circuits |
US8273634B2 (en) * | 2008-12-04 | 2012-09-25 | Micron Technology, Inc. | Methods of fabricating substrates |
US8796155B2 (en) * | 2008-12-04 | 2014-08-05 | Micron Technology, Inc. | Methods of fabricating substrates |
US8247302B2 (en) * | 2008-12-04 | 2012-08-21 | Micron Technology, Inc. | Methods of fabricating substrates |
US7862962B2 (en) * | 2009-01-20 | 2011-01-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit layout design |
US7989355B2 (en) * | 2009-02-12 | 2011-08-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of pitch halving |
JP5330004B2 (ja) * | 2009-02-03 | 2013-10-30 | 株式会社東芝 | 半導体装置の製造方法 |
US8268543B2 (en) * | 2009-03-23 | 2012-09-18 | Micron Technology, Inc. | Methods of forming patterns on substrates |
JP4901898B2 (ja) | 2009-03-30 | 2012-03-21 | 株式会社東芝 | 半導体装置の製造方法 |
US9330934B2 (en) * | 2009-05-18 | 2016-05-03 | Micron Technology, Inc. | Methods of forming patterns on substrates |
US7972926B2 (en) | 2009-07-02 | 2011-07-05 | Micron Technology, Inc. | Methods of forming memory cells; and methods of forming vertical structures |
US8110466B2 (en) | 2009-10-27 | 2012-02-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cross OD FinFET patterning |
KR101098062B1 (ko) * | 2009-11-05 | 2011-12-26 | 주식회사 하이닉스반도체 | 반도체 소자의 형성방법 |
US20110129991A1 (en) * | 2009-12-02 | 2011-06-02 | Kyle Armstrong | Methods Of Patterning Materials, And Methods Of Forming Memory Cells |
US8026178B2 (en) | 2010-01-12 | 2011-09-27 | Sandisk 3D Llc | Patterning method for high density pillar structures |
KR101736983B1 (ko) | 2010-06-28 | 2017-05-18 | 삼성전자 주식회사 | 반도체 소자 및 반도체 소자의 패턴 형성 방법 |
US9130058B2 (en) | 2010-07-26 | 2015-09-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Forming crown active regions for FinFETs |
US8518788B2 (en) | 2010-08-11 | 2013-08-27 | Micron Technology, Inc. | Methods of forming a plurality of capacitors |
US8455341B2 (en) | 2010-09-02 | 2013-06-04 | Micron Technology, Inc. | Methods of forming features of integrated circuitry |
US8314034B2 (en) * | 2010-12-23 | 2012-11-20 | Intel Corporation | Feature size reduction |
KR101732936B1 (ko) | 2011-02-14 | 2017-05-08 | 삼성전자주식회사 | 반도체 소자의 미세 패턴 형성 방법 |
CN102693898B (zh) * | 2011-03-21 | 2016-02-24 | 华邦电子股份有限公司 | 缩小间距的方法 |
US8575032B2 (en) | 2011-05-05 | 2013-11-05 | Micron Technology, Inc. | Methods of forming a pattern on a substrate |
JP5595977B2 (ja) | 2011-05-27 | 2014-09-24 | 株式会社東芝 | 半導体記憶装置、その製造方法及びコンタクト構造の形成方法 |
JP2013004669A (ja) * | 2011-06-15 | 2013-01-07 | Toshiba Corp | パターン形成方法、電子デバイスの製造方法及び電子デバイス |
KR101751476B1 (ko) * | 2011-10-17 | 2017-06-28 | 삼성전자주식회사 | 반도체 기억 소자의 형성 방법 |
US9076680B2 (en) | 2011-10-18 | 2015-07-07 | Micron Technology, Inc. | Integrated circuitry, methods of forming capacitors, and methods of forming integrated circuitry comprising an array of capacitors and circuitry peripheral to the array |
KR101671082B1 (ko) | 2011-12-29 | 2016-10-31 | 인텔 코포레이션 | 스페이서 보조 피치 분할 리소그래피 |
US9177794B2 (en) | 2012-01-13 | 2015-11-03 | Micron Technology, Inc. | Methods of patterning substrates |
JP5818710B2 (ja) | 2012-02-10 | 2015-11-18 | 東京応化工業株式会社 | パターン形成方法 |
KR101881750B1 (ko) | 2012-02-29 | 2018-07-25 | 삼성전자주식회사 | 정보 저장 소자 및 그 제조 방법 |
US9153440B2 (en) * | 2012-03-23 | 2015-10-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming a semiconductor device |
US8629048B1 (en) | 2012-07-06 | 2014-01-14 | Micron Technology, Inc. | Methods of forming a pattern on a substrate |
KR20140008863A (ko) * | 2012-07-12 | 2014-01-22 | 에스케이하이닉스 주식회사 | 더블 spt를 이용한 반도체 소자의 미세패턴 형성방법 |
KR102015568B1 (ko) * | 2012-08-27 | 2019-08-28 | 삼성전자주식회사 | 반도체 소자의 제조 방법 |
US9711368B2 (en) * | 2013-04-15 | 2017-07-18 | United Microelectronics Corp. | Sidewall image transfer process |
US9406331B1 (en) | 2013-06-17 | 2016-08-02 | Western Digital (Fremont), Llc | Method for making ultra-narrow read sensor and read transducer device resulting therefrom |
US8969206B1 (en) | 2013-09-04 | 2015-03-03 | Sandisk Technologies Inc. | Triple patterning NAND flash memory with stepped mandrel |
US9613806B2 (en) | 2013-09-04 | 2017-04-04 | Sandisk Technologies Llc | Triple patterning NAND flash memory |
US8932955B1 (en) * | 2013-09-04 | 2015-01-13 | Sandisk Technologies Inc. | Triple patterning NAND flash memory with SOC |
US9177797B2 (en) * | 2013-12-04 | 2015-11-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lithography using high selectivity spacers for pitch reduction |
US9136106B2 (en) * | 2013-12-19 | 2015-09-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for integrated circuit patterning |
CN103972057A (zh) * | 2014-05-27 | 2014-08-06 | 上海华力微电子有限公司 | 一种半导体精细特征尺寸图形的形成方法 |
US9224744B1 (en) | 2014-09-03 | 2015-12-29 | Sandisk Technologies Inc. | Wide and narrow patterning using common process |
JPWO2016093087A1 (ja) * | 2014-12-09 | 2017-09-07 | 東京エレクトロン株式会社 | パターン形成方法、ガスクラスターイオンビーム照射装置及びパターン形成装置 |
KR102339781B1 (ko) | 2014-12-19 | 2021-12-15 | 삼성전자주식회사 | 반도체 소자 및 그 제조 방법 |
US9673059B2 (en) * | 2015-02-02 | 2017-06-06 | Tokyo Electron Limited | Method for increasing pattern density in self-aligned patterning integration schemes |
US9390922B1 (en) | 2015-02-06 | 2016-07-12 | Sandisk Technologies Llc | Process for forming wide and narrow conductive lines |
US9472414B2 (en) * | 2015-02-13 | 2016-10-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-aligned multiple spacer patterning process |
US9425047B1 (en) | 2015-02-19 | 2016-08-23 | Sandisk Technologies Llc | Self-aligned process using variable-fluidity material |
US9312064B1 (en) | 2015-03-02 | 2016-04-12 | Western Digital (Fremont), Llc | Method to fabricate a magnetic head including ion milling of read gap using dual layer hard mask |
US9502428B1 (en) | 2015-04-29 | 2016-11-22 | Sandisk Technologies Llc | Sidewall assisted process for wide and narrow line formation |
US9595444B2 (en) | 2015-05-14 | 2017-03-14 | Sandisk Technologies Llc | Floating gate separation in NAND flash memory |
US10957561B2 (en) | 2015-07-30 | 2021-03-23 | Lam Research Corporation | Gas delivery system |
US9837286B2 (en) | 2015-09-04 | 2017-12-05 | Lam Research Corporation | Systems and methods for selectively etching tungsten in a downstream reactor |
US10192751B2 (en) | 2015-10-15 | 2019-01-29 | Lam Research Corporation | Systems and methods for ultrahigh selective nitride etch |
WO2017111822A1 (en) * | 2015-12-24 | 2017-06-29 | Intel Corporation | Pitch division using directed self-assembly |
US10825659B2 (en) | 2016-01-07 | 2020-11-03 | Lam Research Corporation | Substrate processing chamber including multiple gas injection points and dual injector |
US9640409B1 (en) * | 2016-02-02 | 2017-05-02 | Lam Research Corporation | Self-limited planarization of hardmask |
US10651015B2 (en) | 2016-02-12 | 2020-05-12 | Lam Research Corporation | Variable depth edge ring for etch uniformity control |
US10699878B2 (en) | 2016-02-12 | 2020-06-30 | Lam Research Corporation | Chamber member of a plasma source and pedestal with radially outward positioned lift pins for translation of a substrate c-ring |
US10147588B2 (en) | 2016-02-12 | 2018-12-04 | Lam Research Corporation | System and method for increasing electron density levels in a plasma of a substrate processing system |
US10438833B2 (en) | 2016-02-16 | 2019-10-08 | Lam Research Corporation | Wafer lift ring system for wafer transfer |
US9882028B2 (en) * | 2016-06-29 | 2018-01-30 | International Business Machines Corporation | Pitch split patterning for semiconductor devices |
CN109564936B (zh) | 2016-08-10 | 2023-02-17 | 英特尔公司 | 量子点阵列装置 |
US10410832B2 (en) | 2016-08-19 | 2019-09-10 | Lam Research Corporation | Control of on-wafer CD uniformity with movable edge ring and gas injection adjustment |
US10453686B2 (en) * | 2016-08-31 | 2019-10-22 | Tokyo Electron Limited | In-situ spacer reshaping for self-aligned multi-patterning methods and systems |
US9911619B1 (en) * | 2016-10-12 | 2018-03-06 | Globalfoundries Inc. | Fin cut with alternating two color fin hardmask |
US10170328B1 (en) * | 2017-08-28 | 2019-01-01 | Nanya Technology Corporation | Semiconductor pattern having semiconductor structures of different lengths |
CN110690117B (zh) * | 2018-07-05 | 2023-10-20 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
US11792973B2 (en) | 2020-07-28 | 2023-10-17 | Changxin Memory Technologies, Inc. | Storage device and forming method having a strip-shaped bitline contact structure |
CN112786536B (zh) * | 2021-01-29 | 2022-07-08 | 长鑫存储技术有限公司 | 存储器的制备方法 |
CN116741626A (zh) * | 2022-03-04 | 2023-09-12 | 长鑫存储技术有限公司 | 一种半导体结构的制备方法及半导体结构 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6133132A (en) * | 2000-01-20 | 2000-10-17 | Advanced Micro Devices, Inc. | Method for controlling transistor spacer width |
CN1378264A (zh) * | 2001-03-29 | 2002-11-06 | 华邦电子股份有限公司 | 一种具有牺牲型填充柱的自行对准接触方法 |
CN1385889A (zh) * | 2001-05-14 | 2002-12-18 | 世界先进积体电路股份有限公司 | 下埋式微细金属连线的制造方法 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5286410A (en) * | 1988-03-10 | 1994-02-15 | Merck Patent Gesellschaft Mit Beschrankter Haftung | Supertwist liquid-crystal display |
US5296410A (en) | 1992-12-16 | 1994-03-22 | Samsung Electronics Co., Ltd. | Method for separating fine patterns of a semiconductor device |
JP3715021B2 (ja) * | 1996-04-09 | 2005-11-09 | Jsr株式会社 | 液状硬化性樹脂組成物 |
US6121123A (en) * | 1997-09-05 | 2000-09-19 | Advanced Micro Devices, Inc. | Gate pattern formation using a BARC as a hardmask |
US6063688A (en) | 1997-09-29 | 2000-05-16 | Intel Corporation | Fabrication of deep submicron structures and quantum wire transistors using hard-mask transistor width definition |
US6180468B1 (en) * | 1998-10-23 | 2001-01-30 | Advanced Micro Devices Inc. | Very low thermal budget channel implant process for semiconductors |
US6248637B1 (en) * | 1999-09-24 | 2001-06-19 | Advanced Micro Devices, Inc. | Process for manufacturing MOS Transistors having elevated source and drain regions |
US6429123B1 (en) | 2000-10-04 | 2002-08-06 | Vanguard International Semiconductor Corporation | Method of manufacturing buried metal lines having ultra fine features |
US6667237B1 (en) | 2000-10-12 | 2003-12-23 | Vram Technologies, Llc | Method and apparatus for patterning fine dimensions |
US6638441B2 (en) | 2002-01-07 | 2003-10-28 | Macronix International Co., Ltd. | Method for pitch reduction |
US6743368B2 (en) * | 2002-01-31 | 2004-06-01 | Hewlett-Packard Development Company, L.P. | Nano-size imprinting stamp using spacer technique |
-
2005
- 2005-08-01 US US11/194,489 patent/US7291560B2/en active Active
-
2006
- 2006-07-03 GB GB0613201A patent/GB2428882B/en not_active Expired - Fee Related
- 2006-07-28 JP JP2006206784A patent/JP4405484B2/ja not_active Expired - Fee Related
- 2006-08-01 CN CNB2006101009901A patent/CN100446216C/zh not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6133132A (en) * | 2000-01-20 | 2000-10-17 | Advanced Micro Devices, Inc. | Method for controlling transistor spacer width |
CN1378264A (zh) * | 2001-03-29 | 2002-11-06 | 华邦电子股份有限公司 | 一种具有牺牲型填充柱的自行对准接触方法 |
CN1385889A (zh) * | 2001-05-14 | 2002-12-18 | 世界先进积体电路股份有限公司 | 下埋式微细金属连线的制造方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11985807B2 (en) | 2020-09-17 | 2024-05-14 | Changxin Memory Technologies, Inc. | Method for manufacturing semiconductor structure and semiconductor structure |
Also Published As
Publication number | Publication date |
---|---|
US7291560B2 (en) | 2007-11-06 |
GB2428882A (en) | 2007-02-07 |
CN1909205A (zh) | 2007-02-07 |
US20070026684A1 (en) | 2007-02-01 |
JP4405484B2 (ja) | 2010-01-27 |
GB0613201D0 (en) | 2006-08-09 |
JP2007043156A (ja) | 2007-02-15 |
GB2428882B (en) | 2007-12-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN100446216C (zh) | 半导体技术中产生间距细分的方法 | |
US9472422B2 (en) | Semiconductor device structure and manufacturing methods | |
TWI482199B (zh) | 在半導體裝置中形成精細圖案之方法 | |
CN102422411B (zh) | 在集成电路的制造中形成多个导电线的方法,形成导电线阵列的方法以及集成电路 | |
US10121782B2 (en) | 3D cross-point memory manufacturing process having limited lithography steps | |
JP6457581B2 (ja) | コンタクト・パッド構造およびそれを作製するための方法 | |
US20120175745A1 (en) | Methods for fabricating semiconductor devices and semiconductor devices using the same | |
US20190019542A1 (en) | Memory device and manufacturing method thereof | |
CN102468304A (zh) | 存储装置及其制造方法 | |
KR100651317B1 (ko) | 그 위에 적어도 두 개의 금속 구조물이 배치된 기판 및 그제조 방법 | |
CN113178449A (zh) | 用于双重图案化工艺的临界尺寸控制 | |
US8399955B2 (en) | Method of forming patterns of semiconductor device | |
KR101389518B1 (ko) | 반도체 소자의 제조방법 | |
EP2973679B1 (en) | Forming fence conductors in trenches formed by a spacer etching technique | |
CN103531526B (zh) | 金属互连结构及其制作方法 | |
US10748815B2 (en) | Three-dimensional semiconductor device and method of manufacturing same | |
CN110890326B (zh) | 用于在半导体鳍片阵列上产生栅极切割结构的方法 | |
TWI532123B (zh) | 記憶裝置及記憶裝置結構的製備方法 | |
TWI626716B (zh) | 記憶元件及其製造方法 | |
CN101383346A (zh) | 半导体器件及其制造方法 | |
US20150004785A1 (en) | Self-aligned patterning technique for semiconductor device features | |
JP2005150751A (ja) | ストレージノードを有する半導体装置およびその製造方法 | |
CN105336741B (zh) | 半导体结构 | |
KR100451613B1 (ko) | 하나 이상의 커패시터를 구비한 집적 회로 배열 및 그제조 방법 | |
CN105826321B (zh) | 半导体元件及其制造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C41 | Transfer of patent application or patent right or utility model | ||
TR01 | Transfer of patent right |
Effective date of registration: 20151231 Address after: German Berg, Laura Ibiza Patentee after: Infineon Technologies AG Address before: Munich, Germany Patentee before: QIMONDA AG |
|
CF01 | Termination of patent right due to non-payment of annual fee | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20081224 Termination date: 20170801 |