JP4405484B2 - 半導体技術における微細ピッチの製造方法 - Google Patents
半導体技術における微細ピッチの製造方法 Download PDFInfo
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- JP4405484B2 JP4405484B2 JP2006206784A JP2006206784A JP4405484B2 JP 4405484 B2 JP4405484 B2 JP 4405484B2 JP 2006206784 A JP2006206784 A JP 2006206784A JP 2006206784 A JP2006206784 A JP 2006206784A JP 4405484 B2 JP4405484 B2 JP 4405484B2
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- 239000004065 semiconductor Substances 0.000 title claims description 9
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 238000005516 engineering process Methods 0.000 title claims description 5
- 125000006850 spacer group Chemical group 0.000 claims description 149
- 239000000758 substrate Substances 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 10
- 238000000034 method Methods 0.000 description 31
- 230000000737 periodic effect Effects 0.000 description 18
- 239000000463 material Substances 0.000 description 12
- 230000000295 complement effect Effects 0.000 description 3
- 238000010276 construction Methods 0.000 description 3
- 230000015654 memory Effects 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 102100026827 Protein associated with UVRAG as autophagy enhancer Human genes 0.000 description 1
- 101710102978 Protein associated with UVRAG as autophagy enhancer Proteins 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- Microelectronics & Electronic Packaging (AREA)
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- Inorganic Chemistry (AREA)
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- Semiconductor Memories (AREA)
- Drying Of Semiconductors (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
本発明は、半導体装置の周期的な構造またはパターンの製造方法に関する。
半導体メモリのような特定の種類の半導体装置では、少なくとも一次元において、構造素子もしくはパターン化された層が周期的に設けられている。例えばワード線およびビット線は、その多くが各々平行に延びた直線状に配されており、その線幅や、隣接している線と線との間の距離が装置全体において一定となっている。上記のような線の並びは周期的であって、その寸法は最小であることが好ましい。最小にすることによって、領域が最小のメモリセルアレイを実現することができる。線の寸法および、線と線との間の寸法は、周期的に並んだ方向に連続している。これら周期のうちの1つの長さは、パターンのピッチと呼ばれる。
〔特許文献1〕US6,063,688
〔特許文献2〕US5,296,410
〔特許文献3〕US6,410,387
一形態では、本発明は、従来よりも小さいピッチを有した半導体デバイスにおいて周期パターンを形成する方法に関する。
2 パターン層
3 ハードマスク
4 第1のスペーサ層
5 第1のスペーサ
6 第2のスペーサ層
7 第2のスペーサ
8 補充層
9 デバイス層
10 オリジナルピッチ
Claims (3)
- 半導体技術における微細ピッチの製造方法であって、
互いに等間隔、かつ平行に延びて配置される、同一構造の側壁および同一の横寸法を有する複数の細片様構造が形成されているパターン層を主面に有する基板を準備した後に、上記パターン層の上に第1のスペーサ層を塗布し、塗布後に、上記第1のスペーサ層を異方性エッチングして上記パターン層の側壁に第1のスペーサを形成する工程(A)であって、隣り合う2つの上記パターン層の間に形成された第1のスペーサ同士の距離が、上記パターン層の横寸法の2分の1未満となるように、上記パターン層及び上記第1のスペーサを形成する工程(A)と、
上記第1のスペーサを残すように、上記パターン層を除去する工程(B)と、
上記パターン層を除去した後に、上記第1のスペーサを覆うように第2のスペーサ層を塗布する工程(C)であって、もともと上記パターン層を形成していなかった箇所において隣り合っている2つの第1のスペーサの間を、上記第2のスペーサ層によって完全に充填する工程(C)と、
上記第2のスペーサ層を異方性エッチングして、上記第1のスペーサの側壁に第2のスペーサを形成する工程(D)であって、上記工程(C)において除去される前に上記パターン層が在った箇所では、隣り合っている2つの第1のスペーサにおける、該箇所の側に対向している側壁にそれぞれ設けられた該第2のスペーサ同士の間に空隙が残るように第2のスペーサ層が異方性エッチングされ、一方、もともと上記パターン層が存在していなかった箇所において隣り合っている2つの第1のスペーサの間に充填された上記第2のスペーサ層は、該第1のスペーサ同士の距離と等しい横寸法をもつ上記第2のスペーサとなる工程(D)と、
上記空隙に補充層を充填する工程(E)と、
上記補充層を充填した後に、上記第1のスペーサ、上記第2のスペーサ、および上記補充層の上端を除去することによって、上記第1のスペーサと、上記第2のスペーサと、上記補充層との上部表面を平坦にする工程(F)と、
上記第1のスペーサと、上記第2のスペーサと、上記補充層と、上記第1のスペーサ及び第2のスペーサと、上記第1のスペーサ及び補充層と、第2のスペーサ及び補充層とからなる群から選択される少なくとも1つを除去する工程(G)と、を含むことを特徴とする製造方法。 - 隣り合う2つの上記補充層の間には、3つの上記第2のスペーサが、第2のスペーサと第2のスペーサとの間に上記第1のスペーサを挟むようにして設けられていることを特徴とする請求項1に記載の製造方法。
- 第2のスペーサ及び補充層と、第1のスペーサ及び補充層と、第1のスペーサ及び第2のスペーサと、第2のスペーサと、第1のスペーサとからなる群から選択された少なくとも1つの層をマスクとして利用して、上記パターン層の下部において別の層または別の連続層をエッチングすることを特徴とする請求項1または2に記載の製造方法。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/194,489 US7291560B2 (en) | 2005-08-01 | 2005-08-01 | Method of production pitch fractionizations in semiconductor technology |
Publications (2)
Publication Number | Publication Date |
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JP2007043156A JP2007043156A (ja) | 2007-02-15 |
JP4405484B2 true JP4405484B2 (ja) | 2010-01-27 |
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JP2006206784A Expired - Fee Related JP4405484B2 (ja) | 2005-08-01 | 2006-07-28 | 半導体技術における微細ピッチの製造方法 |
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Country | Link |
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US (1) | US7291560B2 (ja) |
JP (1) | JP4405484B2 (ja) |
CN (1) | CN100446216C (ja) |
GB (1) | GB2428882B (ja) |
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2005
- 2005-08-01 US US11/194,489 patent/US7291560B2/en active Active
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2006
- 2006-07-03 GB GB0613201A patent/GB2428882B/en not_active Expired - Fee Related
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US7291560B2 (en) | 2007-11-06 |
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GB2428882A (en) | 2007-02-07 |
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US20070026684A1 (en) | 2007-02-01 |
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