CN100391007C - 高击穿电压mos晶体管的结构及其制造方法 - Google Patents

高击穿电压mos晶体管的结构及其制造方法 Download PDF

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CN100391007C
CN100391007C CNB200410092153XA CN200410092153A CN100391007C CN 100391007 C CN100391007 C CN 100391007C CN B200410092153X A CNB200410092153X A CN B200410092153XA CN 200410092153 A CN200410092153 A CN 200410092153A CN 100391007 C CN100391007 C CN 100391007C
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西部荣次
八柳俊佑
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Abstract

一种半导体装置及其制造方法。其提高了高击穿电压MOS晶体管的工作击穿电压，同时抑制热载流子造成的饱和电流Idsat的变动。其在P型半导体衬底(1)上形成栅极绝缘膜(2)。在栅极绝缘膜(2)上形成栅电极(3)。通过将栅电极(3)作为掩模，将双电荷磷离子(31P++)进行倾斜离子注入，形成第一低浓度源极层(4a)和第一低浓度漏极层(5a)。另外，通过将磷离子(31P+)进行倾斜离子注入，形成第二低浓度源极层(4b)和第二低浓度漏极层(5b)。进而，为提高形成有第一低浓度源极层(4a)和第一低浓度漏极层(5a)、第二低浓度源极层(4b)和第二低浓度漏极层(5b)的P型半导体衬底(1)的最表面浓度，较浅地注入砷离子(75As+)，形成表面注入层(4c、5c)。

Description

高击穿电压MOS晶体管的结构及其制造方法
技术领域
本发明涉及半导体装置及其制造方法，特别是涉及高击穿电压MOS晶体管的结构及其制造方法。
背景技术
图5是表示现有例的N沟道型高击穿电压MOS晶体管的结构的剖面图。在P型硅衬底50上介由栅极绝缘膜51形成栅电极52。在栅电极52的侧壁形成由绝缘膜构成的侧壁隔层53。另外，形成由N-型源极层54a和N+型源极层54b构成的源极层54，由N-型漏极层55a和N+型漏极层55b构成的漏极层55。
在该高击穿电压MOS晶体管中，通过与栅电极52邻接而设置N-型漏极层55a，在离开栅电极52的位置设置N+型漏极层55b，而减缓漏极电场，得到高的漏极击穿电压。
另外，这种高击穿电压MOS晶体管例如在以下的专利文献1中公开。
专利文献1特开平5-218070号公报
发明内容
为提高漏极击穿电压，必须减少N-型漏极层55a的形成用离子注入的剂量，降低N-型漏极层55a的杂质浓度。但是，单纯地降低N-型漏极层55a的杂质浓度，会使N-型漏极层55a的最表面的浓度变得过稀。
若这样过度地降低N-型漏极层55a的杂质浓度，向其高击穿电压MOS晶体管流通沟道电流，发生热载流子(HC)，则在热载流子注入栅极绝缘膜2前后，存在高击穿电压MOS晶体管的饱和电流Idsat大幅度变动的问题。另外，存在若不降低杂质浓度则工作击穿电压(电流流向晶体管时的漏极击穿电压)恶化的问题。
图4(b)表示热载流子注入前后的源漏问电流Ids特性。晶体管的饱和电流Idsat大幅度变动是因为受到陷入(トラツプ)栅极绝缘膜2的热载流子的电荷影响使N-型漏极层55a最表面的电阻值变动。
因此，本发明提供一种使高击穿电压MOS晶体管的工作击穿电压提高，同时抑制热载流子造成的饱和电流Idsat的变动。
本发明的半导体装置具有：半导体衬底；在上述半导体衬底上介由栅极绝缘膜形成的栅电极；形成在上述半导体衬底的表面，延伸至上述栅电极下面的第一低浓度漏极层；形成在上述第一低浓度漏极层上的上述半导体衬底表面，具有比该第一低浓度漏极层浓度高的杂质的表面注入层；在上述半导体衬底的表面形成的高浓度漏极层。
并且，在上述结构基础上，还具有第二低浓度漏极层，该第二低浓度漏极层形成得比上述第一低浓度漏极层浅，比上述表面注入层深，并且具有比上述第一低浓度漏极层浓度低的杂质。
另外，本发明的半导体装置制造方法具有：在第一导电型半导体衬底上形成栅极绝缘膜的工序；在上述栅极绝缘膜上形成栅电极的工序；将上述栅电极作为掩模，以第一离子束的倾斜角将第二导电型杂质向上述半导体衬底较深地离子注入，形成第一低浓度漏极层的第一离子注入工序；将上述栅电极作为掩模，以小于上述第一离子束倾斜角的第二离子束的倾斜角将第二导电型杂质向上述半导体衬底较浅地进行离子注入，提高上述第一低浓度漏极层的表面浓度的第二离子注入工序。
另外，在上述工序的基础上，还包括：将上述栅电极作为掩模，以第三离子束的倾斜角，将第二导电型杂质向上述半导体衬底进行离子注入，形成比第一低浓度漏极层浅，并且具有低杂质浓度的第二低浓度漏极层的第三离子注入工序。
根据本发明，因为由第一低浓度漏极层衰减漏极电场，在该第一低浓度漏极层上的半导体衬底最表面上形成，具有浓度比该第一低浓度漏极层高的杂质的表面注入层，所以使高击穿电压MOS晶体管的工作击穿电压提高，同时能够抑制热载流子导致的饱和电流Idsat的变动。
附图说明
图1(a)、图1(b)、图1(c)是说明本发明实施例的半导体的装置制造方法的剖面图；
图2(a)、图2(b)是说明本发明的实施例的半导体装置的制造方法的剖面图；
图3(a)、图3(b)是表示沿高击穿电压MOS晶体管的所形成的P型半导体衬底1的最表面的杂质浓度曲线图；
图4(a)、图4(b)是表示热载流子注入前后的源漏间电流Ids的特性图；
图5是表示现有例的半导体装置的剖面图。
具体实施方式
接着，说明实施本发明的最佳方式(以下称为实施例)。参照附图说明本发明实施例的半导体装置及其制造方法。首先，参照图1和图2说明第一实施例。图1和图2是表示这种半导体装置制造方法的剖面图。
如图1(a)所示，在P型半导体衬底1(例如P型硅衬底)的表面上利用热氧化法等形成栅极绝缘膜2。在该栅极绝缘膜2上形成栅电极3。该工序中，首先，全面利用LPCVD法淀积多晶硅层，向其掺杂磷等的杂质使其低电阻化后，局部蚀刻该多晶硅层而形成栅电极3。
其次，如图1(b)所示，在以栅电极3为掩模不穿透其的条件下，通过将双电荷磷离子(31P++)进行倾斜离子注入而形成第一低浓度源极层4a和第一低浓度漏极层5a。
在该离子注入的工序中，双电荷磷离子(31P++)的离子束的倾斜角θ1以垂直方向为基准成45度，为确保源极漏极的对称性从栅电极3的左右方向进行该离子注入。若考虑高击穿电压MOS晶体管的各种图形配置，为不依赖于图形配置而确保源极漏极的对称性，使离子束相对半导体衬底旋转的同时而进行离子注入是合适。这时，可固定P型半导体衬底1而旋转照射离子束的离子枪，相反，也可固定离子束的照射方向，使P型半导体衬底1旋转。
通过该倾斜离子注入工序，离子束到达栅电极3的下方。由于第一低浓度漏极层5a延伸至栅电极3的下方，这样第一低浓度漏极层5a的宽度(载流子的漂移区域的宽度)变得更宽。因此，可不对晶体管尺寸进行设计变更而提高工作击穿电压。离子束绕垂直方向的倾斜角度最好为45度，然而不限于此，只要在35度～55度范围内就能得到一定程度的效果。
而且，为衰减漏区电场，第一低浓度漏极层5a必须形成得深，最好其加速电压为100KeV(因双电荷故实际上是200KeV)，剂量为1.8×1013/cm3左右是令人满意的。
另外，如图1(c)  所示，在以栅电极3为掩模而不穿透其的条件下，通过将单电荷磷离子(31P+)进行倾斜离子注入，形成第二低浓度源极层4b和第二低浓度漏极层5b。该第二低浓度源极层4b和第二低浓度漏极层5b，与第一低浓度源极层4a和第一低浓度漏极层5a重叠而形成，并比这些层注入得浅，具有低的杂质浓度。
其离子注入条件最好是加速电压为100KeV，剂量为1×1012/cm3左右。另外，该离子注入工序与图2(b)  的双电荷磷离子(31P++)  的离子注入一样是倾斜离子注入，离子束的倾斜角θ2最好以垂直方向为基准成45度。
其次，如图2(a)所示，为提高形成有第一低浓度源极层4a和第一低浓度漏极层5a，第二低浓度源极层4b和第二低浓度漏极层5b的P型半导体衬底1最表面的浓度，在以栅电极3为掩模并不穿透其的条件下，较浅地注入砷离子(75As+)，形成表面注入层4c、5c。由此，使高击穿电压MOS晶体管的工作击穿电压提高，同时抑制热载流子导致的饱和电流Idsat的变动。
其离子注入的条件最好是加速电压为70KeV，剂量为3×1012/cm3左右。并且，离子束的倾斜角θ3，最好比上述离子注入的离子束倾斜角θ1、θ2小。这是因为在栅电极3下面形成表面注入层4c、5c，可防止漏极击穿电压降低。
具体地，该离子束的倾斜角θ3最好以垂直方向为基准成7度。离子束的倾斜角θ3即使是0度附近也无妨，然而必需考虑到防止沟道效应。
其次，如图2(b)所示，在栅电极3的侧面形成侧壁隔层6。本工序中，全面利用LPCVD法淀积氧化硅膜等绝缘膜，通过将该绝缘膜进行各向异性蚀刻，在栅电极3的侧面形成侧壁隔层6。然后，向P型硅衬底1的表面高浓度地离子注入磷、砷等N型杂质，在与栅电极3的端部邻接或离开栅电极5端部的位置形成高浓度型源极层4d和高浓度漏极层5d。
该高浓度源极层4d和高浓度漏极层5d与第一低浓度源极层4a和第一低浓度漏极层5a、第二低浓度源极层4b和第二低浓度漏极层5b、表面注入层4c、5c相比浓度高。为防止受栅电极3端部的强电场影响造成漏极漏电流GIDL(Gate Induced Drain Leakage current)，高浓度漏极层5d最好形成在离开栅电极3的端部位置。
图3是表示沿该高击穿电压MOS晶体管的所形成的P型半导体衬底1最表面的杂质浓度曲线图，图3(a)表示本实施例的杂质浓度曲线，图3(b)表示现有例的杂质浓度曲线。图中，CH是高击穿电压MOS晶体管的沟道区域，其右侧表示低浓度漏极层(第一低浓度漏极层5a、第二低浓度漏极层5b、表面注入层5c)的曲线。
在图3(b)的现有例中，在低浓度漏极层的端部出现杂质浓度曲线的「凹部」。在此杂质浓度突然降低，其缘于热载流子注入导致电阻、饱和电流Idsat变动。与此相对，在图3(a)的本实施例的杂质曲线中，这样的杂质浓度曲线「凹部」被消除。这是形成了表面注入层5c的效果。因此，如图4(a)所示，根据本实施例，在热载流子的注入前后，饱和电流Idsat不变动。
另外可知，相对于在图3(b)的现有例中低浓度漏极的杂质曲线急剧上升，在图3(a)的本实施例杂质曲线中平稳上升，沿P型半导体衬底1的最表面杂质浓度平稳变化。这是设置了第一低浓度漏极层5a的效果，能够防止工作击穿电压、漏极击穿电压的降低。
进而，根据本实施例，因为第一低浓度漏极层5a延伸至栅电极3的下方，所以也可得到如下效果。现在将漏极电压Vd施加到高浓度漏极层5d，将栅电压Vg施加到栅电极3。这时，施加比栅极·源极间电压Vgs高的漏极·源极间电压Vds时(Vds＞Vgs)，在与栅电极3下面重叠的第一低浓度漏极层5a部分的表面生成表面耗尽层。于是，流到高击穿电压MOS晶体管的沟道电流(电子电流)避免遇到第一低浓度漏极层5a的端部表面的电场集中部分，而流经其表面耗尽层下方的第一低浓度漏极层5a的深区域，因此衬底电流Isub降低，工作击穿电压提高。
另外，在本实施例中，源极侧和漏极侧具有同样的结构，然而仅向漏极侧施加高电压时，源极侧也可是仅具有N+型源极层4d的单侧高击穿电压结构。

Claims (6)

1.一种半导体装置，其特征在于，具有：半导体衬底；在上述半导体衬底上介由栅极绝缘膜形成的栅电极；形成于上述半导体衬底的表面，延伸至上述栅电极下面的第一低浓度漏极层；形成于上述第一低浓度漏极层上的上述半导体衬底表面，具有比该第一低浓度漏极层浓度高的杂质的表面注入层；在所述半导体衬底的表面形成的高浓度漏极层；具有第二低浓度漏极层，该第二低浓度漏极层形成得比所述第一低浓度漏极层浅，比所述表面注入层深，并且具有比所述第一低浓度漏极层浓度低的杂质。
2.一种半导体装置的制造方法，其特征在于，具有：在第一导电型半导体衬底上形成栅极绝缘膜的工序；在所述栅极绝缘膜上形成栅电极的工序；将所述栅电极作为掩模，以第一离子束的倾斜角，将第二导电型杂质向所述半导体衬底较深地离子注入，形成第一低浓度漏极层的第一离子注入工序；将所述栅电极作为掩模，以小于所述第一离子束倾斜角的第二离子束的倾斜角将第二导电型杂质向所述半导体衬底较浅地离子注入，提高所述第一低浓度漏极层表面浓度的第二离子注入工序；将所述栅电极作为掩模，以第三离子束的倾斜角将第二导电型杂质向所述半导体衬底离子注入，形成比第一低浓度漏极层浅且具有低杂质浓度的第二低浓度漏极层的第三离子注入工序；以及，在所述半导体衬底的表面形成的高浓度漏极层工序。
3.按照权利要求2所述的半导体装置制造方法，其特征在于，所述第一离子束倾斜角以垂直方向为基准成45度，所述第二离子束倾斜角以垂直方向为基准成7度。
4.按照权利要求2所述的半导体装置制造方法，其特征在于，在所述第一和第二离子注入工序中，离子束与所述半导体衬底相对旋转的同时照射。
5.按照权利要求2所述的半导体装置制造方法，其特征在于，所述第三离子束倾斜角以垂直方向为基准成45度。
6.按照权利要求2所述的半导体装置制造方法，其特征在于，在所述第三离子注入工序中，离子束与所述半导体衬底相对旋转的同时照射。
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