BR9712840A - Célula de memória não volátil - Google Patents

Célula de memória não volátil

Info

Publication number
BR9712840A
BR9712840A BR9712840-6A BR9712840A BR9712840A BR 9712840 A BR9712840 A BR 9712840A BR 9712840 A BR9712840 A BR 9712840A BR 9712840 A BR9712840 A BR 9712840A
Authority
BR
Brazil
Prior art keywords
memory cell
volatile memory
recess
surface region
mos transistor
Prior art date
Application number
BR9712840-6A
Other languages
English (en)
Portuguese (pt)
Inventor
Georg Tempel
Original Assignee
Siemens Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag filed Critical Siemens Ag
Publication of BR9712840A publication Critical patent/BR9712840A/pt

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
  • Micro-Organisms Or Cultivation Processes Thereof (AREA)
BR9712840-6A 1996-09-23 1997-09-15 Célula de memória não volátil BR9712840A (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19639026A DE19639026C1 (de) 1996-09-23 1996-09-23 Selbstjustierte nichtflüchtige Speicherzelle
PCT/DE1997/002066 WO1998013878A1 (de) 1996-09-23 1997-09-15 Selbstjustierte nichtflüchtige speicherzelle

Publications (1)

Publication Number Publication Date
BR9712840A true BR9712840A (pt) 2000-12-05

Family

ID=7806628

Family Applications (1)

Application Number Title Priority Date Filing Date
BR9712840-6A BR9712840A (pt) 1996-09-23 1997-09-15 Célula de memória não volátil

Country Status (11)

Country Link
EP (1) EP0948816B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JP2001501034A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
KR (1) KR20000048526A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
CN (1) CN1135628C (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
AT (1) ATE265091T1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
BR (1) BR9712840A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (2) DE19639026C1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
IN (1) IN191647B (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
RU (1) RU2205471C2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
UA (1) UA57034C2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
WO (1) WO1998013878A1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2810161B1 (fr) * 2000-06-09 2005-03-11 Commissariat Energie Atomique Memoire electronique a architecture damascene et procede de realisation d'une telle memoire
DE10162261B4 (de) * 2001-12-18 2005-09-15 Infineon Technologies Ag Speicherzelle mit Grabentransistor
TW575960B (en) * 2001-12-18 2004-02-11 Infineon Technologies Ag Memory cell with trench transistor
US6661053B2 (en) 2001-12-18 2003-12-09 Infineon Technologies Ag Memory cell with trench transistor
DE10204873C1 (de) 2002-02-06 2003-10-09 Infineon Technologies Ag Herstellungsverfahren für Speicherzelle
DE10226964A1 (de) * 2002-06-17 2004-01-08 Infineon Technologies Ag Verfahren zur Herstellung einer NROM-Speicherzellenanordnung
DE10229065A1 (de) * 2002-06-28 2004-01-29 Infineon Technologies Ag Verfahren zur Herstellung eines NROM-Speicherzellenfeldes
DE10306318B4 (de) * 2003-02-14 2010-07-22 Infineon Technologies Ag Halbleiter-Schaltungsanordnung mit Grabenisolation und Herstellungsverfahren
KR100674952B1 (ko) * 2005-02-05 2007-01-26 삼성전자주식회사 3차원 플래쉬 메모리 소자 및 그 제조방법
US7365382B2 (en) * 2005-02-28 2008-04-29 Infineon Technologies Ag Semiconductor memory having charge trapping memory cells and fabrication method thereof
US7312490B2 (en) * 2005-03-31 2007-12-25 Intel Corporation Vertical memory device and method
KR100707217B1 (ko) * 2006-05-26 2007-04-13 삼성전자주식회사 리세스-타입 제어 게이트 전극을 구비하는 반도체 메모리소자 및 그 제조 방법
KR101131136B1 (ko) * 2006-10-19 2012-04-03 삼성전자주식회사 리세스-타입 제어 게이트 전극을 구비하는 반도체 메모리소자의 동작 방법
CN101221955B (zh) * 2006-11-20 2010-06-09 旺宏电子股份有限公司 有扩散阻挡结构的栅极二极管非易失性存储器及制造方法
JP5301123B2 (ja) 2007-07-25 2013-09-25 スパンション エルエルシー 半導体装置及びその製造方法
JP5546740B2 (ja) * 2008-05-23 2014-07-09 ローム株式会社 半導体装置
WO2010114406A1 (ru) * 2009-03-30 2010-10-07 Murashev Viktor Nikolaevich Ячейка памяти для быстродействующего эсппзу и способ ее программирования
RU2436190C1 (ru) * 2010-04-13 2011-12-10 Учреждение Российской академии наук Физико-технологический институт РАН (ФТИАН) Ячейка энергонезависимой электрически перепрограммируемой памяти
RU2465659C1 (ru) * 2011-08-09 2012-10-27 Федеральное государственное автономное образовательное учреждение высшего профессионального образования "Национальный исследовательский технологический университет "МИСиС" Ячейка памяти для быстродействующего эсппзу с управляемым потенциалом подзатворной области
JP5815786B2 (ja) * 2014-04-09 2015-11-17 ローム株式会社 半導体装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0715953B2 (ja) * 1985-08-09 1995-02-22 株式会社リコー 書換え可能なメモリ装置とその製造方法
JPS6285468A (ja) * 1985-10-09 1987-04-18 Nippon Denso Co Ltd 不揮発性半導体記憶装置
US5045490A (en) * 1990-01-23 1991-09-03 Texas Instruments Incorporated Method of making a pleated floating gate trench EPROM
JP2925312B2 (ja) * 1990-11-30 1999-07-28 株式会社東芝 半導体基板の製造方法
RU2018994C1 (ru) * 1992-03-31 1994-08-30 Константин Иванович Баринов Элемент памяти
JP2889061B2 (ja) * 1992-09-25 1999-05-10 ローム株式会社 半導体記憶装置およびその製法
KR0125113B1 (ko) * 1993-02-02 1997-12-11 모리시타 요이찌 불휘발성 반도체 메모리 집적장치 및 그 제조방법
JPH0738002A (ja) * 1993-07-22 1995-02-07 Toshiba Corp 半導体装置及びその半導体装置を用いた不揮発性半導体メモリとそのメモリの駆動回路

Also Published As

Publication number Publication date
UA57034C2 (uk) 2003-06-16
CN1135628C (zh) 2004-01-21
EP0948816A1 (de) 1999-10-13
EP0948816B1 (de) 2004-04-21
JP2001501034A (ja) 2001-01-23
DE19639026C1 (de) 1998-04-09
KR20000048526A (ko) 2000-07-25
CN1238857A (zh) 1999-12-15
WO1998013878A1 (de) 1998-04-02
RU2205471C2 (ru) 2003-05-27
IN191647B (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 2003-12-13
ATE265091T1 (de) 2004-05-15
DE59711553D1 (de) 2004-05-27

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Legal Events

Date Code Title Description
B08F Application dismissed because of non-payment of annual fees [chapter 8.6 patent gazette]

Free format text: REFERENTE A 8A , 9A E 10A ANUIDADES.

B08K Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette]

Free format text: REFERENTE AO DESPACHO 8.6 PUBLICADO NA RPI 1905 DE 10/07/2007.