BR0011998A - Processo para a fabricação de uma célula de memória semicondutora não-volátil com janela de túnel separada - Google Patents

Processo para a fabricação de uma célula de memória semicondutora não-volátil com janela de túnel separada

Info

Publication number
BR0011998A
BR0011998A BR0011998-9A BR0011998A BR0011998A BR 0011998 A BR0011998 A BR 0011998A BR 0011998 A BR0011998 A BR 0011998A BR 0011998 A BR0011998 A BR 0011998A
Authority
BR
Brazil
Prior art keywords
memory cell
manufacture
tunnel window
semiconductor memory
volatile semiconductor
Prior art date
Application number
BR0011998-9A
Other languages
English (en)
Inventor
Peter Wawer
Oliver Springmann
Konrad Wolf
Olaf Heitzsch
Kai Huckels
Reinhold Rennekamp
Mayk Roehrich
Elard Stein Von Kamienski
Christoph Kutter
Christoph Ludwig
Original Assignee
Infineon Technologies Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag filed Critical Infineon Technologies Ag
Publication of BR0011998A publication Critical patent/BR0011998A/pt

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7883—Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass

Abstract

Patente de Invenção: "PROCESSO PARA A FABRICAçãO DE UMA CéLULA DE MEMóRIA SEMICONDUTORA NãO-VOLáTIL COM JANELA DE TúNEL SEPARADA". A invenção refere-se a um processo para a fabricação de uma célula de memória semicondutora não-volátil (SZ) com célula de janela de túnel separada (TF), sendo que uma zona de túnel (TG) é configurada, empregando-se a célula de janela de túnel (TF) como máscara, em uma etapa de implantação ulterior através de uma implantação de túnel (I~ T~). Desse modo, obtém-se uma célula de memória com pequena necessidade de superfície e uma grande quantidade de ciclos de programar/apagar.
BR0011998-9A 1999-06-28 2000-05-30 Processo para a fabricação de uma célula de memória semicondutora não-volátil com janela de túnel separada BR0011998A (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19929618A DE19929618B4 (de) 1999-06-28 1999-06-28 Verfahren zur Herstellung einer nichtflüchtigen Halbleiter-Speicherzelle mit separatem Tunnelfenster
PCT/DE2000/001769 WO2001001476A1 (de) 1999-06-28 2000-05-30 Vefahren zur herstellung einer nichtflüchtigen halbleiter-speicherzelle mit separatem tunnelfenster

Publications (1)

Publication Number Publication Date
BR0011998A true BR0011998A (pt) 2002-03-05

Family

ID=7912849

Family Applications (1)

Application Number Title Priority Date Filing Date
BR0011998-9A BR0011998A (pt) 1999-06-28 2000-05-30 Processo para a fabricação de uma célula de memória semicondutora não-volátil com janela de túnel separada

Country Status (11)

Country Link
US (1) US6645812B2 (pt)
EP (1) EP1192652A1 (pt)
JP (2) JP2003503851A (pt)
KR (1) KR100447962B1 (pt)
CN (1) CN1171293C (pt)
BR (1) BR0011998A (pt)
DE (1) DE19929618B4 (pt)
MX (1) MXPA01013170A (pt)
RU (1) RU2225055C2 (pt)
UA (1) UA73508C2 (pt)
WO (1) WO2001001476A1 (pt)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10235072A1 (de) * 2002-07-31 2004-02-26 Micronas Gmbh EEPROM-Struktur für Halbleiterspeicher
JP4393106B2 (ja) * 2003-05-14 2010-01-06 シャープ株式会社 表示用駆動装置及び表示装置、並びに携帯電子機器
JP4497290B2 (ja) * 2004-04-14 2010-07-07 富士通株式会社 半導体装置とその製造方法
CN113054001B (zh) * 2021-03-16 2021-11-09 中国电子科技集团公司第五十八研究所 可编程的电源开关器件及其制备方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57112078A (en) * 1980-12-29 1982-07-12 Fujitsu Ltd Manufacture of electrically rewritable fixed memory
US4477825A (en) * 1981-12-28 1984-10-16 National Semiconductor Corporation Electrically programmable and erasable memory cell
US4608585A (en) * 1982-07-30 1986-08-26 Signetics Corporation Electrically erasable PROM cell
JPS6325980A (ja) * 1986-07-17 1988-02-03 Nec Corp 不揮発性半導体記憶装置及びその製造方法
JPS6384168A (ja) * 1986-09-29 1988-04-14 Toshiba Corp 不揮発性半導体記憶装置
JP2792028B2 (ja) * 1988-03-07 1998-08-27 株式会社デンソー 半導体記憶装置およびその製造方法
JP2784765B2 (ja) * 1988-03-11 1998-08-06 セイコーインスツルメンツ株式会社 半導体不揮発性メモリの製造方法
JPH0334579A (ja) * 1989-06-30 1991-02-14 Toshiba Corp 不揮発性半導体記憶装置およびその製造方法
US5565371A (en) * 1990-04-12 1996-10-15 Texas Instruments Incorporated Method of making EPROM with separate erasing and programming regions
US5371031A (en) * 1990-08-01 1994-12-06 Texas Instruments Incorporated Method of making EEPROM array with buried N+ windows and with separate erasing and programming regions
JP3222705B2 (ja) * 1993-11-30 2001-10-29 東芝マイクロエレクトロニクス株式会社 不揮発性半導体記憶装置及びその製造方法
KR0147452B1 (ko) * 1993-11-30 1998-08-01 사토 후미오 불휘발성 반도체기억장치
US5793081A (en) * 1994-03-25 1998-08-11 Nippon Steel Corporation Nonvolatile semiconductor storage device and method of manufacturing
US5633186A (en) * 1995-08-14 1997-05-27 Motorola, Inc. Process for fabricating a non-volatile memory cell in a semiconductor device
EP0782196A1 (en) * 1995-12-28 1997-07-02 STMicroelectronics S.r.l. Method of fabricating EEPROM memory devices and EEPROM memory device so formed
TW437099B (en) * 1997-09-26 2001-05-28 Matsushita Electronics Corp Non-volatile semiconductor memory device and the manufacturing method thereof

Also Published As

Publication number Publication date
CN1171293C (zh) 2004-10-13
US6645812B2 (en) 2003-11-11
EP1192652A1 (de) 2002-04-03
KR100447962B1 (ko) 2004-09-08
MXPA01013170A (es) 2002-08-12
CN1361924A (zh) 2002-07-31
DE19929618A1 (de) 2001-01-11
US20020119626A1 (en) 2002-08-29
WO2001001476A1 (de) 2001-01-04
UA73508C2 (en) 2005-08-15
KR20020019472A (ko) 2002-03-12
JP2006319362A (ja) 2006-11-24
RU2225055C2 (ru) 2004-02-27
DE19929618B4 (de) 2006-07-13
JP2003503851A (ja) 2003-01-28

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Legal Events

Date Code Title Description
B08F Application dismissed because of non-payment of annual fees [chapter 8.6 patent gazette]

Free format text: REFERENTE A 10A ANUIDADE(S),

B08K Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette]

Free format text: REFERENTE AO DESPACHO 8.6 PUBLICADO NA RPI 2082 DE 30/11/2010.