TW575960B - Memory cell with trench transistor - Google Patents

Description

575960 ⑴ bump, invention description

(Explanation of the invention should state: the technical field to which the invention belongs, the prior art, the content, the embodiments, and the drawings are briefly explained) The present invention relates to a memory cell with a storage transistor, which includes a semiconductor body or a semiconductor layer on top A gate electrode on the surface, the electrode being located in a trench between a source region and a drain region, the trench being constructed in the semiconductor material of the semiconductor body or layer, and transverse to a longitudinal direction, at least The cross-section shows the same cross-section, and a dielectric layer (preferably a 10NO layer) is used as a storage medium between the gate electrode and the semiconductor material. ~

DE 100 39 441 A1 describes a memory cell with a trench transistor, which is located in a trench formed on the top surface of a semiconductor body. Arranged between the gate electrode installed in the trench, the laterally adjacent source region, and the adjacent non-electrode region on the other side is an oxide-nitridation-oxide layer sequence, which is used between the source and drain The pole captures charge carriers. This type of electric crystal is particularly suitable for the memory cell configuration of non-volatile memory (NVM). Areas with the electric field strength required for stylization and erasure are typically located at different locations in these transistors. Therefore, once the charges are programmed on the nitride, it is quite difficult to completely erase them. The programming operation requires an electron injection. The electrons must penetrate the oxidized boundary layer to reach the nitrided layer as a storage layer. Therefore, the electron must be a so-called "thermoelectron" with high kinetic energy. This type of electron exists only where the electric field strength is very strong in the channel below the gate electrode on the surface of the semiconductor material. -Figure 5 shows from left to right the gate electrode 4, the gate dielectric 9 (specifically, it may be a 100N storage layer), and the adjacent semiconductor material with the channel region 5. Energy is represented by an arrow drawn in the vertical direction, and the 575960 (2) invention page

The direction of the arrow increases. The drawn curves a and b represent the upper limit of the valence band and the lower limit of the conductive band, respectively. There are two Fermi energy levels Efl and Ef2. Up to these energy levels, the states that can only be occupied by Pauli's principle are filled with electrons. In the shaded area shown in Fig. 5, when the Fermi energy level Efl is low, only a few electrons are located in the conductive band at the boundary of the semiconductor material. It can be found that in the case of a higher Fermi energy level Ef2, more electrons and higher energy electrons are present in the conductive band. Therefore, higher energy electrons are more likely to penetrate the oxide layer adjacent to the nitrided storage layer. One

FIG. 6 shows a cross section of a typical transistor structure, which includes a source region 2, a drain region 3, a gate electrode 4, a gate dielectric 9 and a channel region 5. The dashed line indicates the boundary of a channel-forming space region of the channel. When the voltage required to program the transistor is applied, the electrons passing through the channel region are accelerated in the direction of the arrow. The length of the arrow (not drawn to scale) indicates the average kinetic energy of the electron. Obviously, the average kinetic energy of the electron increases rapidly as it approaches the drain region 3. Since the electric field strength rapidly increases as it approaches the drain region 3 to a point just before the drain region, the increase is extremely excessive. When the electrons reach the end of the channel region 5, their energy is high enough to enter the storage layer. In the example of a storage transistor placed in a trench, the region with the electrons suitable for stylized energy is also located at the end of the channel region. In this example, it ends on the side of the bottom of the trench, which is directly at pf. Below the connection between the electrically doped substrate and the conductive doped drain region. In the cross section of the source region on the left and the drain region on the right, the stylized region is located at the bottom of the trench, approximately on the right-hand side of the bottom. 575960 (3) Invention description For erasing operation, a hole injection (charge carrier with opposite sign) is required. It only has the effect of Gate Induced Drain Leakage (GIDL) effect. n-MOSFET. This effect occurs only near the drain region. Therefore, the positions where electron injection and hole injection occur may not be the same. In any case, a high voltage and / or a very long erase time can be used to erase such memory cells.

The object of the present invention is to construct a memory cell with a trench transistor, the programming and erasing time of which is significantly less than that of a conventional memory cell of this type. This can be achieved by a memory unit with features such as patent application scope 1, 3, 7 and 8.

According to the present invention, the trench depth is selected relative to a region where the charge carriers of the storage layer are neutralized in an erase operation, so that in a stylized operation, an electric field component acting on the charge carriers is The same region has a maximum value (the component is aligned parallel to a tangent to a wall or bottom of the trench and perpendicular to the longitudinal direction of the trench). In this way, the trench depth is optimized so that the locations of electron and hole injection are consistent. The connection at the source and drain regions doped to opposite signs (ie, the sign of the substrate or semiconductor body conductivity type) adjoins a curved area at the bottom of the trench or a lower curved area at the sidewall of the trench. Fig. 1 shows a cross section of two trenches, which is generated in a half body body 1 as a substrate or in a semiconductor layer on a substrate. At least the cross section of the trench is equal to the cross section of the trench in the longitudinal direction of the trench. Therefore, for the section on the front of the injection plane and the section behind the injection plane, the display in Figure 1 will be the same as in 575960 (4) Invention Description Continued. In the scope of this description and patent application, the longitudinal direction means that a vertical section does not change along that direction. -In a region of the corresponding top surface of the semiconductor body 1 or the semiconductor layer, a source region 2 and a drain region 3 are formed by mixing an impurity (here, as an example of a left-hand trench transistor). If the semiconductor body 1 is doped with p-conductivity, the source regions 2 and > and the electrode region 3 are formed to be η + conductive, respectively. On the contrary, the boundaries between the dopant areas (usually clearly indicated) are referred to here as connections 1 4 and their position in the semiconductor material is detectable (for example using SIMS). A gate electrode 4 (for example, a polycrystalline stone electrode) is installed in each trench. A channel region 5 is formed below the source and gate regions, opposite the gate electrode on the boundary surface of the semiconductor material.

The trench sidewalls 6, 8 and bottom 7 refer to the surface of the semiconductor material facing the trench. Located between the gate electrode 4 and the semiconductor material is a dielectric layer 9 which acts as a gate dielectric and covers the wall surface and bottom of the trench. The dielectric layer 9 is formed as a storage medium. To achieve this, the dielectric layer 9 is preferably multi-layered and includes at least a storage layer 11 located between the boundary layers 10, 12 in the example shown in FIG. The boundary layers 10 and 12 are oxides (specifically, they are dioxide fragments) ', and the storage layer 11 can be a chaotic compound (here, Si] N4). For example, in the operation of the semiconductor unit, for programming, there is a voltage of 10 volts in the source region, a voltage of 9 volts in the gate electrode 4, and a voltage of 6 volts in the drain region 3. The gate electrode has a voltage of 8 volts and a voltage of 5 volts in the drain region. In the figure, the dielectric layer 9 in the bottom of the trench is omitted from the left trench of the memory, which is indicated by the corresponding dashed line. In order to facilitate the following description, the drawing includes a horizontal arrow 575960 (5) Description of the invention continued on page 2 2 and a vertical arrow 23, which indicate the lateral direction from the source to the drain, and the vertical direction into the depth of the trench. In addition, the figure also includes the interval 24 between the walls of the ditch at the height of 14 and the depth of the ditch 2 5 below the height of 14 (that is, the entire ditch from a connection 14 to the deepest point of the ditch is vertical size). The voltage is applied to the source region 2 and the drain region 3 via contacts attached to the front and back sides of the implantation plane, respectively, and the gate voltage is supplied via a block line 13 extending laterally (that is, in the implantation plane). In a stylized operation, for a trench with #-φ bottom half-cylindrical shape, the set voltage generates an electric field intensity distribution that is right-handed under the connection of the components tangent to the bottom or wall of the trench in the section plane shown The side has a maximum value. These relationships are reproduced in Fig. 2, which shows the cross section shown in Fig. 1 for model calculation of a trench with a semi-cylindrical bottom. The curve represents the section

The electric field component Eγ on which the line 'is represented by the front has the same value. Some inferences can be drawn from this regarding the magnitude of the absolute value of the electric field component that extends within the section and is tangent to the wall or bottom of the trench, respectively. It can be clearly seen that in the left-handed memory unit (which has been precharged in Figure 1 for stylization using the corresponding voltage), when the direction of the arrow 22 'passes through the axis A forming the bottom half cylinder, the channel In the longitudinal direction, the rotation is set to approximately 30 downwards. The field component extending in the direction of the arrow 22 reaches a maximum value. At this time, effective programming of the memory cell occurs, and hole injection in the erase operation occurs in a region directly above the connection 14 of the drain region 3. FIG. 3 shows an optimized memory cell of this type according to the present invention, in which the corresponding region at the bottom of the groove of the trench -10- 960960 (6) is located between the drain region 3 and the oppositely doped semiconductor material. η is connected nearby. In a corresponding exemplary embodiment, the accuracy of the optimized memory unit can be obtained by calculating and simulating and / or experimentally using implemented structural elements using a model familiar to the skilled person without much effort. size. However, it is impossible to obtain corresponding digital data for all the specific embodiments within the scope of the present invention. Therefore, the principles constituting the present invention will now be explained in detail. This technical guide will be described in a way that will allow a person skilled in the art to manufacture such memory cells. First, it is important to understand that it is mainly the type of bend at the bottom of the ditch and the lower area of the side wall of the ditch, not just the length of the channel that determines the curve of the field component aligned tangentially to the wall of the ditch. The assumption so far is that the trench must be mounted deep enough in the semiconductor material that most of the trench wall surface lies below the source and drain regions. In contrast, in the memory cell according to the present invention, a side curve is located between the actual bottom of the trench and the substantially vertical side wall, and the region thereof is where the hole injection occurs during the erase operation. Therefore, the area programmed and erased by the charge carrier injection is directly aligned with the ρ η connection. To achieve this, the trench depth is reduced accordingly. This is shown in the section of Fig. 3, where the reference characters have the same meaning as the reference characters in the figure above. Between the top surface of the semiconductor body 1 or the semiconductor layer and the connection 1 4 (it is between the source region 2 or the drain region 3 and the oppositely doped semiconductor material, but the semiconductor material need not be a plane in practice, but can be constructed in A The vertical dimension of the source region 2 and the drain region 3 between the surface of the memory cell is only slightly smaller than the total vertical dimension of the trench in the memory cell. When using SIMS to determine the connection position, the average value of the continuation sheet of the invention description is used in a certain area. The vertical dimension of the trench has a downward overhang beyond the connection 14 and will be referred to as the depth of the trench 25 hereinafter. The measurement is performed from the level of connection 14 in the trench to the deepest point at the bottom of the trench (relative to the plane of the top surface of the semiconductor body or semiconductor layer) in a vertical direction, that is, perpendicular to the plane of the top surface of the semiconductor body or layer .

In a preferred exemplary embodiment, the depth 25 is at most only half of the trench wall spacing 24 (ditch width) at the height of the connection 14. The depth 2 5 is selected depending on the corresponding geometry of the trench section, so that the connections 1 4 respectively contact the wall surface of the trench in an area, wherein the curve of the trench wall surface in a cross section transverse to a longitudinal direction has a curve radius, which is at most Only two-thirds of the ditch wall surface at the height of the connection 14 is separated by 24. When the bottom of the ditch has a semi-cylindrical shape with a radius r, the distance 24 between the walls of the ditch at a height of 14 is at most twice the radius (that is, at most

2 r). Throughout this example, the radius of the curve at the bottom of the ditch is r, so the more convenient maximum of depth 25 is r, although it is better to be smaller. When the radius r of the semi-cylinder is, for example, 55 nm, the depth is 55 nm or less. Since the channel length cannot be too small, the value of 30 nanometers can be kept as the lower limit of the depth 2 5 as much as possible. Setting the depth 25 to 30 nm, the arc at the bottom of the ditch (which can be seen in the section below the connection 14 and approximately represents the length of the channel) has a radius r set to 55 nm and equals 120.88 nm, at f When the diameter r is 70 nm, it is equal to 134.76 nm. At the height of the connection 14, the channel wall spacing 24 is equal to 97.98 nm at 1: 55 nm and 114.89 nm at 1 * = 70 nm. Therefore, In any case, the connection 14 adjoins the trench wall surface -12- 575960 (8) Description of the invention The curve radius at this point on the following page is less than two thirds of the trench wall surface interval 24 at the height of the connection 14.

When the vertical dimensions of source region 2 and drain region 3 are, for example, 150 nm, the optimal total trench depth measured from the top surface of the semiconductor body or layer is between 180 nm and 55 nm with a radius r of 55 nm. The range of 205 nanometers is in the range of 180 nanometers to 220 nanometers when the radius I · is 70 nanometers. In this example, the bottom of the ditch does not need to have an entire semi-cylindrical shape. The side wall of the ditch can be directly connected to the curved bottom or there is a slight movement in the connection, so that only a part of the shape of the half of the cylinder at the bottom, that is, a central angle less than 180 ° Part of the shape of a half cylinder.

The trench depth must be adjusted accordingly to accommodate other curved radii at the bottom of the trench or other shapes at the bottom of the trench. The level of impurity concentration also plays a role, and additional implementations of channel region 5 may be considered if necessary. An embodiment to increase channel conductivity and reduce electric field at more significant bending points of the trench also makes it possible to provide a more curved curve in the bottom region of the trench, where charge carrier injection does not occur. Therefore, it is within the scope of the invention to provide an embodiment of a somewhat tapered trench bottom and doping impurities into the deepest point region of the bottom of the lower semiconductor material. It is preferred here to provide a greater channel length by selecting a depth 25 which is greater than the trench wall spacing 24-half at the height of the connection 14. However, also in this example, in a cross section perpendicular to the longitudinal direction of the ditch, the radius of the wall curve connecting the walls of the adjacent 14 ditch trenches is at most two thirds of the interval of 24. In some specific embodiments, it may be advantageous that the trench depth 25 is substantially less than half of the trench wall spacing 24 at the height of the connection 1 4, especially -13- 575960 (9) The bottom of the trench has a small curve or a flat interior and a very curved side portion, and most of the wall surface extends at least approximately vertically, so that a substantial curve exists only on the lower side of the bottom. However, in these specific embodiments, it must be taken into account that at a very shallow depth of 25 and a very flat trench bottom, the channel length may not be long enough, or because the rather small channel length offsets part of the invention best.化 purpose.

The side walls of the trench can tend to be vertical in its upper area (arrows 2 3 in Figure 1). FIG. 4 shows a corresponding cross section of an additional exemplary embodiment, the side wall of the t-ditch is obviously inclined in its upper region, and has an inclination angle of about 5 相对 with respect to the vertical direction. In this exemplary embodiment, the side walls 6, 8 have narrow areas 15, 17 just above the bottom 7 of the trench, extending in the longitudinal direction of the trench, in which the direction of the side wall in the section is slightly curved . In the lower regions 16 and 18 of the side wall, the tangent direction of the wall surface in the section is in a large angle range, up to 10 ° with respect to the vertical direction. Here, the trench bottom 7 is relatively slightly curved, so that the significantly larger curved area of the trench wall surface is located between the lower side regions 16 and 18 and the trench bottom 7. In this exemplary embodiment, the trench depth 25 is selected such that the pn connection (connection 14) between the source region and the oppositely doped semiconductor material or between the drain region and the oppositely doped semiconductor material is approximately at this significant The height of the bend may be just above this height. It can also be assumed here that stylization occurs in the area of the trench wall just above the area with the most significant bend. For illustrative purposes, the dielectric layer 9 in the lower region is omitted from the right-hand trench section of Fig. 4, which is also indicated by the dashed line. The graph includes curve radii 19, 20, and 21, which are not drawn to scale or accuracy. These lengths are just -14- 575960 (ίο) Description of the invention continued on the description that the radius of the curve 19 in the actual bottom side area is very small. Adjacent regions 16 and 18 of the side walls have a substantially larger curve radius 20. The curve radius 21 of the bottom 7 is also quite large.

Looking at the tangent of the trench wall surface, which extends in the injection plane transverse to the longitudinal direction of the trench, the wall surface portion formed by the side wall can be defined as a small inclination angle, up to 10 relative to the vertical direction (arrow 23). . In the ditch of the specific embodiment shown in FIG. 4, the wall portion of the ditch located between these side walls and a deepest point at the bottom has a radius of a curve in the cross-section of FIG. 4 (which is perpendicular to the longitudinal direction). Only the ditch wall surface at the height of the connection 14 is half spaced by the distance 24. The connections 1 4 adjoin the trench walls in these areas. It is assumed that the area where the hole injection occurred during the erasing operation is at least approximately consistent with the most significant curved area of the trench wall surface. Therefore, it is more advantageous to connect an area adjacent to the side wall of the ditch, where the bending radius is at most 10% greater than the minimum value it has on the wall of the ditch.

The memory cell preferably has a mirror-symmetrical structure as shown in the figure, because in this case, when the applied voltage is reversed, stylization and erasure can also occur in the storage layer area on the left side of the figure. Referring to FIG. 1 to FIG. 6, the above is a detailed description of the memory unit. Figure 1: A schematic cross-section through two adjacent trenches. Figure 2: A model is used to simulate the cross section of the two trenches shown in Figure 1, which has a downward E-field-component curve. Figures 3 and 4: Corresponding sections of a memory cell constructed according to the present invention. Figures 5 and 6: The diagrams described in this introduction. -15-575960 (ii) Explanation of symbol of formula (1) Semiconductor body 2 Source region 3 Drain region 4 Gate electrode 5 Channel region, 8 Side wall of trench 7 Bottom of trench 9 Gate dielectric 10, 12 Boundary layer 11 Storage Layer 13 word line 14 connects 15 and 17 narrow area 16 > 18 lower area 19-21 curve radius 22 horizontal arrow 22, arrow 23 vertical arrow 24 interval 25 depth a, b curve invention description continued page

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Claims (1)

575960 No. 091135418 Patent Application 92.11.20 Chinese Application for Patent Scope Replacement (November 1992) Pick up and apply for patent scope 1. A memory unit with a storage transistor, which is included in the semiconductive body (1) Or a gate electrode (4) on a top surface of the semiconductor layer, located in a trench between a source region (2) and a drain region (3), the channel is disposed in the semiconductor body or layer The semiconductor material has the same cross section transverse to a longitudinal direction and at least the cross section. The source region (2) and the drain region (3) are formed in the semiconductor material by the top surface. Doped to a corresponding junction (1 4), and the gate electrode system is isolated from the semiconductor material by a dielectric layer (9) configured as a storage medium, and is characterized in that the junction (1 4) is adjacent to the junction A section of a ditch wall surface, in which a section of the ditch wall mask perpendicular to the longitudinal direction has a curved radius, which at each point is at most one third of the ditch wall surface interval (24) at the height of the junction (14) The second is big. 2. For example, the memory unit of the scope of patent application, wherein the trench has side walls (6, 8) opposite to the longitudinal direction, which is oriented at a plane opposite to the top surface of the half-body (1) or layer Is perpendicular to the vertical direction and deviates from the vertical direction by at most 10 °, and there are some regions between the side wall (6, 8) and the deepest point of the trench opposite to the top surface plane, where it is perpendicular to the longitudinal position The wall surface of the ditch within a section has a curved radius, which is at most at half the gap (2 4) of the wall surface of the ditch at the height of the junction (14) at each point; and the junction (14) adjoins the wall of the canal. These areas. 3. —A memory unit with a storage transistor, which includes a gate electrode (4) on a semiconductive body (1) or on the top surface of a semiconductor layer, and the groove has a central electrode region and the There is a trench body guided by a domain. Its 575960 patent application is quite continuation sheet. It is located in a trench between a source region (2) and a drain region (3). The trench is placed in the semiconductor body or The semiconductor material of the layer has the same cross section transverse to a longitudinal direction and at least the cross section. The source region (· 2) and the drain region (3) are formed in the semiconductor material by The top surface is doped to a corresponding junction (1 4), and the gate electrode is isolated from the semiconductor material by a dielectric layer (9) configured as a storage medium, which is characterized by the trench depth (25 ), Which is measured between the junction (14) and a deepest point of the trench in an orthogonal perpendicular direction with respect to the semiconductor body (1) or the top surface plane of the layer, up to the height of the junction (14) The ditch wall surface interval (24) is half as large. 4. The memory unit according to item 3 of the scope of patent application, wherein the interface (1 4) is adjacent to an area of the trench wall surface, and the trench wall mask at a cross section perpendicular to the longitudinal direction has a curved radius, At each point, it is at most two-thirds of the ditch wall surface interval (24) at the height of the junction (14). 5. The memory unit according to any one of claims 1 to 4, wherein the bottom of the trench has a shape of a semi-cylindrical or cylindrical part, and the interface (14) abuts the bottom. 6. The memory unit according to any one of claims 1 to 4 in the scope of patent application, wherein the trench wall surface interval (24) at the height of the junction (1 4) is between 100 nm and 150 nm, And the trench depth (25) is measured between the junction (14) and a deepest point of the trench in an orthogonal vertical direction with respect to the semiconductor body (1) or the top surface plane of the layer, at least 3 0 nm, at most half of the interval (24). 575960 Patent application title page: A memory unit with a storage transistor, which includes a gate electrode (4) on a top surface of a semiconductor body (1) or a semiconductor layer, which is located in a source region ( 2) in a trench between a drain region (2), the trench is disposed in the semiconductor material of the semiconductor body or layer and has the same cross section transverse to a longitudinal direction and at least the cross section Wherein the source region (2) and the drain region (3) are formed in the semiconductor material by doping from the top surface to a corresponding junction (1 4), and the gate electrode system is formed by A dielectric layer (9) of a storage medium is isolated from the semiconductor material, and is characterized in that the interface (14) is adjacent to a region of the trench wall surface, wherein the trench wall surface in a cross section perpendicular to the longitudinal direction It has a curve radius that is at most 10% larger than a minimum value of the curve radius of the wall surface of the ditch. One of the sluice gates with the material-breaking shape including the pole groove material is one of them. Guide material 22, S1, J1's survey sheet 3) The conductor surface (3 levels, the It surface area or the Fengfei Department polar body breaks the top from the main body to the M body, and (3 crystal layers) And the guide area electric body (2) the half-square electrode storage guide area should be stored in the direction of the half-pole in the vertical # a) ^ source set one (2 (1 one settled in the area species in the system to the pole one main channel horizontal source) 11) The surface of the β-separated wall is 12 minutes apart, and the material is healthy (1 material should be layered in the trench field to obtain the electrical conductance W to be selected on one side and a half) In the selection, the direction of the opposite direction is m (9 degrees to the direction of the cladding, except for the horizontal and vertical direction of the ditch gate of the quality wiper channel, and the dielectric barrier is at the same level as the d-gate gate. The (11-phase area Lf line is layered on top of everything and there is a sub-M). The storage area of the M-unit is mixed with a special charge midsole or its electric operation or 575960 patent application. The same area has a maximum value on the continuation page. The memory cell of the eighth aspect of the patent, wherein the size is selected such that in the program and erase operation, the charge carriers penetrate a boundary layer (10) in a region through the drain region (3) Incorporated into the opposite Type region is electrically connected to the semiconductor material of the drain region (3) to the top surface direction.