ATE411604T1 - Gelatchte programmierung von speicher und verfahren - Google Patents

Gelatchte programmierung von speicher und verfahren

Info

Publication number
ATE411604T1
ATE411604T1 AT05749543T AT05749543T ATE411604T1 AT E411604 T1 ATE411604 T1 AT E411604T1 AT 05749543 T AT05749543 T AT 05749543T AT 05749543 T AT05749543 T AT 05749543T AT E411604 T1 ATE411604 T1 AT E411604T1
Authority
AT
Austria
Prior art keywords
group
memory
bit lines
lines
memory cells
Prior art date
Application number
AT05749543T
Other languages
English (en)
Inventor
Raul-Adrian Cernea
Original Assignee
Sandisk Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sandisk Corp filed Critical Sandisk Corp
Application granted granted Critical
Publication of ATE411604T1 publication Critical patent/ATE411604T1/de

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/10Programming or data input circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628Programming or writing circuits; Data input circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/04Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/10Programming or data input circuits
    • G11C16/12Programming voltage switching circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/24Bit-line control circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/30Power supply circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/08Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2216/00Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
    • G11C2216/12Reading and writing aspects of erasable programmable read-only memories
    • G11C2216/18Flash erasure of all the cells in an array, sector or block simultaneously
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2216/00Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
    • G11C2216/12Reading and writing aspects of erasable programmable read-only memories
    • G11C2216/22Nonvolatile memory in which reading can be carried out from one memory bank or array whilst a word or sector in another bank or array is being erased or programmed simultaneously

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
AT05749543T 2004-05-10 2005-05-06 Gelatchte programmierung von speicher und verfahren ATE411604T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/842,941 US7177197B2 (en) 2001-09-17 2004-05-10 Latched programming of memory and method

Publications (1)

Publication Number Publication Date
ATE411604T1 true ATE411604T1 (de) 2008-10-15

Family

ID=34969814

Family Applications (1)

Application Number Title Priority Date Filing Date
AT05749543T ATE411604T1 (de) 2004-05-10 2005-05-06 Gelatchte programmierung von speicher und verfahren

Country Status (8)

Country Link
US (3) US7177197B2 (de)
EP (1) EP1747560B1 (de)
JP (1) JP5280679B2 (de)
CN (1) CN100576358C (de)
AT (1) ATE411604T1 (de)
DE (1) DE602005010419D1 (de)
TW (1) TWI280582B (de)
WO (1) WO2005112039A1 (de)

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Also Published As

Publication number Publication date
CN1973337A (zh) 2007-05-30
US7177197B2 (en) 2007-02-13
CN100576358C (zh) 2009-12-30
US20040240269A1 (en) 2004-12-02
US7978533B2 (en) 2011-07-12
DE602005010419D1 (de) 2008-11-27
US7660156B2 (en) 2010-02-09
TWI280582B (en) 2007-05-01
US20070109859A1 (en) 2007-05-17
US20100103745A1 (en) 2010-04-29
JP5280679B2 (ja) 2013-09-04
JP2007537560A (ja) 2007-12-20
EP1747560B1 (de) 2008-10-15
TW200620301A (en) 2006-06-16
EP1747560A1 (de) 2007-01-31
WO2005112039A1 (en) 2005-11-24

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