ATE531049T1 - Abwechselndes lesen und schreiben auf zeilenbasis für nichtflüchtigen speicher - Google Patents
Abwechselndes lesen und schreiben auf zeilenbasis für nichtflüchtigen speicherInfo
- Publication number
- ATE531049T1 ATE531049T1 AT06849087T AT06849087T ATE531049T1 AT E531049 T1 ATE531049 T1 AT E531049T1 AT 06849087 T AT06849087 T AT 06849087T AT 06849087 T AT06849087 T AT 06849087T AT E531049 T1 ATE531049 T1 AT E531049T1
- Authority
- AT
- Austria
- Prior art keywords
- wln
- programmed
- word line
- word lines
- line
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/12—Programming voltage switching circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
- G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5628—Programming or writing circuits; Data input circuits
Landscapes
- Read Only Memory (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/321,259 US7349260B2 (en) | 2005-12-29 | 2005-12-29 | Alternate row-based reading and writing for non-volatile memory |
US11/321,346 US7443726B2 (en) | 2005-12-29 | 2005-12-29 | Systems for alternate row-based reading and writing for non-volatile memory |
PCT/US2006/049381 WO2007079124A1 (en) | 2005-12-29 | 2006-12-27 | Alternate row-based reading and writing for non-volatile memory |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE531049T1 true ATE531049T1 (de) | 2011-11-15 |
Family
ID=38009518
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT06849087T ATE531049T1 (de) | 2005-12-29 | 2006-12-27 | Abwechselndes lesen und schreiben auf zeilenbasis für nichtflüchtigen speicher |
Country Status (6)
Country | Link |
---|---|
EP (1) | EP1969604B1 (de) |
JP (1) | JP4892566B2 (de) |
KR (1) | KR100989181B1 (de) |
AT (1) | ATE531049T1 (de) |
TW (1) | TWI318406B (de) |
WO (1) | WO2007079124A1 (de) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101635504B1 (ko) | 2009-06-19 | 2016-07-04 | 삼성전자주식회사 | 3차원 수직 채널 구조를 갖는 불 휘발성 메모리 장치의 프로그램 방법 |
JP5242603B2 (ja) * | 2010-01-13 | 2013-07-24 | 株式会社東芝 | 半導体記憶装置 |
JP2011192827A (ja) | 2010-03-15 | 2011-09-29 | Toshiba Corp | Nand型不揮発性半導体記憶装置 |
JP5330421B2 (ja) * | 2011-02-01 | 2013-10-30 | 株式会社東芝 | 不揮発性半導体記憶装置 |
JP5542737B2 (ja) * | 2011-05-12 | 2014-07-09 | 株式会社東芝 | 不揮発性半導体記憶装置 |
JP2013118028A (ja) | 2011-12-02 | 2013-06-13 | Toshiba Corp | 半導体記憶装置 |
JP6088751B2 (ja) | 2012-06-07 | 2017-03-01 | 株式会社東芝 | 半導体メモリ |
US9966146B2 (en) | 2014-08-13 | 2018-05-08 | Toshiba Memory Corporation | Memory system and method of controlling non-volatile memory |
JP6433933B2 (ja) * | 2016-03-14 | 2018-12-05 | 東芝メモリ株式会社 | 半導体記憶装置及びメモリシステム |
US10395723B2 (en) | 2017-03-07 | 2019-08-27 | Toshiba Memory Corporation | Memory system that differentiates voltages applied to word lines |
US10062441B1 (en) * | 2017-08-31 | 2018-08-28 | Micron Technology, Inc. | Determining data states of memory cells |
JP2022520372A (ja) * | 2019-10-29 | 2022-03-30 | 長江存儲科技有限責任公司 | メモリデバイスのプログラミング方法、およびメモリデバイス |
CN115295054B (zh) * | 2022-09-30 | 2022-12-13 | 芯天下技术股份有限公司 | 一种存储芯片的读取方法、装置、电子设备及存储介质 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6542407B1 (en) * | 2002-01-18 | 2003-04-01 | Sandisk Corporation | Techniques of recovering data from memory cells affected by field coupling with adjacent memory cells |
JP3913704B2 (ja) * | 2003-04-22 | 2007-05-09 | 株式会社東芝 | 不揮発性半導体記憶装置及びこれを用いた電子装置 |
JP4005000B2 (ja) | 2003-07-04 | 2007-11-07 | 株式会社東芝 | 半導体記憶装置及びデータ書き込み方法。 |
JP4410188B2 (ja) * | 2004-11-12 | 2010-02-03 | 株式会社東芝 | 半導体記憶装置のデータ書き込み方法 |
-
2006
- 2006-12-27 EP EP06849087A patent/EP1969604B1/de not_active Not-in-force
- 2006-12-27 KR KR1020087018746A patent/KR100989181B1/ko active IP Right Grant
- 2006-12-27 JP JP2008548709A patent/JP4892566B2/ja not_active Expired - Fee Related
- 2006-12-27 AT AT06849087T patent/ATE531049T1/de not_active IP Right Cessation
- 2006-12-27 WO PCT/US2006/049381 patent/WO2007079124A1/en active Application Filing
- 2006-12-28 TW TW095149555A patent/TWI318406B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR20090007278A (ko) | 2009-01-16 |
TWI318406B (en) | 2009-12-11 |
EP1969604A1 (de) | 2008-09-17 |
WO2007079124A1 (en) | 2007-07-12 |
KR100989181B1 (ko) | 2010-10-22 |
JP2009522704A (ja) | 2009-06-11 |
EP1969604B1 (de) | 2011-10-26 |
JP4892566B2 (ja) | 2012-03-07 |
TW200741727A (en) | 2007-11-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
ATE531049T1 (de) | Abwechselndes lesen und schreiben auf zeilenbasis für nichtflüchtigen speicher | |
DE602007012157D1 (de) | Leseverfahren für nichtflüchtigen Speicher mit Kompensation der Floating-Gate Kopplung | |
CN1855304B (zh) | 集成电路器件、闪存阵列和操作闪存器件的方法 | |
CN101627440B (zh) | 通过使用不同的预充电启用电压而以减少的编程干扰对非易失性存储器进行编程 | |
CN101385089B (zh) | 用于非易失性存储器的基于行的交替读写 | |
JP4907925B2 (ja) | 不揮発性半導体記憶装置 | |
JP5150245B2 (ja) | 半導体記憶装置 | |
TW200608404A (en) | Operating non-volatile memory without read disturb limitations | |
ATE510287T1 (de) | Kopplungskompensation bei nichtflüchtiger speicherung | |
US20100091568A1 (en) | Nonvolatile Memory and Method With Reduced Program Verify by Ignoring Fastest and/or Slowest Programming Bits | |
DE60315532D1 (de) | Verfahren zur Reudzierung der Programmier- und Lese-Störungen eines nicht-flüchtigen Speichers | |
WO2007149678A3 (en) | Programming defferently sized margins and sensing with compensations at select states for improved read operations in non-volatile memory | |
US8514633B2 (en) | Method for operating semiconductor memory device | |
JP2010250891A (ja) | 不揮発性半導体記憶装置 | |
WO2004029983A3 (en) | Non-volatile memory and method of programming with reduced neighboring field errors | |
CN102067236A (zh) | 在快闪存储器装置上存储数据的方法 | |
CN101627439A (zh) | 通过移除对字线数据的预充电相依性而以减少的编程干扰对非易失性存储器进行编程 | |
WO2008083196A3 (en) | Margined neighbor reading for non-volatile memory read operations including coupling compensation | |
KR20100004791A (ko) | 프로그램 디스터브 현상을 개선하는 불휘발성 메모리 장치및 그 프로그램 방법 | |
TW200710861A (en) | Improved read mode for flash memory | |
US9330762B2 (en) | Semiconductor memory device | |
KR940018872A (ko) | 불휘발성 반도체기억장치 및 이를 이용한 기억시스템 | |
JP4876522B2 (ja) | 不揮発性半導体記憶装置 | |
US7558118B2 (en) | NAND flash memory device | |
JP2013069392A (ja) | 不揮発性半導体記憶装置及び不揮発性半導体記憶装置のデータ書き込み方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |