ATE255769T1 - Verfahren zur herstellung einer halbleitervorrichtung mit luftspalten für verbindungen mit ultraniedriger kapazität - Google Patents

Verfahren zur herstellung einer halbleitervorrichtung mit luftspalten für verbindungen mit ultraniedriger kapazität

Info

Publication number
ATE255769T1
ATE255769T1 AT98901841T AT98901841T ATE255769T1 AT E255769 T1 ATE255769 T1 AT E255769T1 AT 98901841 T AT98901841 T AT 98901841T AT 98901841 T AT98901841 T AT 98901841T AT E255769 T1 ATE255769 T1 AT E255769T1
Authority
AT
Austria
Prior art keywords
air gap
gaps
sacrificial material
ultra
making
Prior art date
Application number
AT98901841T
Other languages
English (en)
Inventor
Paul A Kohl
Qiang Zhao
Sue Ann Bidstrup Allen
Original Assignee
Georgia Tech Res Inst
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Georgia Tech Res Inst filed Critical Georgia Tech Res Inst
Application granted granted Critical
Publication of ATE255769T1 publication Critical patent/ATE255769T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/495—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/072—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/46—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising air gaps

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Addition Polymer Or Copolymer, Post-Treatments, Or Chemical Modifications (AREA)
  • Formation Of Insulating Films (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Polyoxymethylene Polymers And Polymers With Carbon-To-Carbon Bonds (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Ceramic Capacitors (AREA)
AT98901841T 1997-01-21 1998-01-21 Verfahren zur herstellung einer halbleitervorrichtung mit luftspalten für verbindungen mit ultraniedriger kapazität ATE255769T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US3584897P 1997-01-21 1997-01-21
PCT/US1998/001049 WO1998032169A1 (en) 1997-01-21 1998-01-21 Fabrication of a semiconductor device with air gaps for ultra-low capacitance interconnections

Publications (1)

Publication Number Publication Date
ATE255769T1 true ATE255769T1 (de) 2003-12-15

Family

ID=21885155

Family Applications (2)

Application Number Title Priority Date Filing Date
AT03022238T ATE415704T1 (de) 1997-01-21 1998-01-21 Herstellung eines halbleiterbauelements mit luftspalten für niedrigstkapazitive leiterbahnen
AT98901841T ATE255769T1 (de) 1997-01-21 1998-01-21 Verfahren zur herstellung einer halbleitervorrichtung mit luftspalten für verbindungen mit ultraniedriger kapazität

Family Applications Before (1)

Application Number Title Priority Date Filing Date
AT03022238T ATE415704T1 (de) 1997-01-21 1998-01-21 Herstellung eines halbleiterbauelements mit luftspalten für niedrigstkapazitive leiterbahnen

Country Status (10)

Country Link
US (2) US6165890A (de)
EP (2) EP0963603B1 (de)
JP (3) JP4535303B2 (de)
KR (1) KR100532801B1 (de)
CN (1) CN1252810C (de)
AT (2) ATE415704T1 (de)
AU (1) AU736875B2 (de)
DE (2) DE69840276D1 (de)
RU (1) RU2204181C2 (de)
WO (1) WO1998032169A1 (de)

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JP5144693B2 (ja) 2013-02-13
EP1376684A3 (de) 2004-11-10
DE69840276D1 (de) 2009-01-08
WO1998032169A1 (en) 1998-07-23
EP0963603B1 (de) 2003-12-03
JP2009275228A (ja) 2009-11-26
ATE415704T1 (de) 2008-12-15
EP1376684A2 (de) 2004-01-02
DE69820232T2 (de) 2004-09-16
KR100532801B1 (ko) 2005-12-02
EP0963603A1 (de) 1999-12-15
US6165890A (en) 2000-12-26
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AU5826998A (en) 1998-08-07
DE69820232D1 (de) 2004-01-15
JP2010147495A (ja) 2010-07-01
RU2204181C2 (ru) 2003-05-10
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CN1252810C (zh) 2006-04-19
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